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August 21, 2015June 14, 2019

Mentor 2Q Results

Mentor 2Q Results
by Paul McLellan on 08-21-2015 at 7:00 am
Categories: EDA, Siemens EDA

So it was Mentor’s turn yesterday after Synopsys on Wednesday. And yes, it really is the end of their second quarter. They produced some very good results. As Wally opened:The second quarter of fiscal 2016 was one of record for Q2. We substantially exceed our own expectations was revenue of $281.1 million and non-GAAP earnings per share of $0.36. This is largely the result of booking fiscal year 2016 expiring contracts earlier than planned. The majority of this upside was the result of users requiring more software than anticipated in their prior contracts.

Design to Silicon, which includes Calibre, grew 105%. One thing I hadn’t thought of is that in the questions Wally was asked whether they were worried about piracy in China for software and hardware. Firstly, he pointed out, that it would be pretty difficult to knock-off their hardware in any reasonable time (and by there would be a new generation). But he also pointed out that Calibre is used so late in the design process than people are just not going to risk using an unlicensed copy and risk their chip failing.

During SEMI Gartner seminar I wrote about China. It seems that the big investment program there is having some effect. Wally, again:In addition, my meetings with executives at China-based manufacturing established companies as well as principles at China IC investment funds make clear that the $20 billion China IC development program is stimulating increased R&D and other investment that will benefit the EDA industry.

Another area of growth has been emulation. This is a relatively new area and all of Mentor, Cadence and Synopsys (and no startups any more that I know of) have the technology, it has doubled over the last 5 years. It is increasingly seen as essential to getting a chip design done. In the questions Wally said he thought it was on track to being a $1B business on its own (not for Mentor alone, for all 3).

Both Lip-Bu and Aart have commented on consolidation in the customer base as being a possible headwind. Wally is more sanguine (and he has some data…Wally always does):One other topic that comes up in many of my meetings is concerned about the increased amount of M&A activity in the semiconductor industry, while the actual number of mergers and acquisitions is up only modestly in 2015 compared to prior history the magnitude of announced deals is up dramatically. Historically, these changes simply add to the strength of the standard leader in EDA in each tool category so there is some wins and some losses for every supplier. But the other concern is that the total R&D spending of the semiconductor industry could be reduced. That is of course possible, but for more than 30 years semiconductor R&D has averaged a constant 14% of revenue despite lots of structural changes.

In the questions he gave some more color, pointing out that semiconductor R&D is much less volatile than revenue, that can be affected by all sorts of things. But semiconductor companies don’t lightly lay off their design engineers, they will need them when the next upturn comes and they will need product already in the pipeline.

There were some surprises, at least to me, in the geographies. Greg, during his part of the call, said:By geography bookings were up in two of our four reporting regions. Europe was up 40% driven largely by semiconductor customers and products. Pac Rim up 15% on strength of foundry and emulation business, the Americas was flat and Japan was down 50% as its consumer and IC electronics business continues to shrink.

Say what? Europe up 40%, Japan down 50%. OK Japan has been weak forever, but Mentor has been reducing headcount in European sales due to weakness. They have closed some major European auto deals so I’m guess the upside might be there. After all, automotive is 15% to 20% of Mentor’s business these days. But those percentages mean Mentor’s business is now 40% North America, 25% Europe, 30% Asia-Pac and just 5% in Japan (at least this quarter). Mentor has been reducing its salesforce especially in Japan and you can see why.

I didn’t manage to find as good a picture as the one of Aart playing guitar at the San Jose Jazz festival a couple of weeks ago. Oh wait, what is the second image that Google Image Search finds for “Wally Rhines.” OK, that’ll do.

SeekingAlpha transcript of the call is here. There is a huge error in transcription. Mentor announced a dividend of $0.055 per share, but SA has $5.05. That would be nice on a $25 share.

August 20, 2015

Older Nodes Get New Life With Ultra Low Power Variants for IoT

Older Nodes Get New Life With Ultra Low Power Variants for IoT
by Tom Simon on 08-20-2015 at 12:00 pm
Categories: EDA, General, IoT, Mobile, TSMC

Ever since I can remember, and I’ve been in EDA since the early 80’s, new process development has largely focused on the latest nodes. Trailing nodes were quickly put into support mode. New nodes benefited the most from static and dynamic voltage reduction efforts, as well as improvements in flows and performance. Only a small number of niche processes, usually produced by smaller captive fabs, were tuned over time for improvements. But the IoT has changed this.

With projected volumes for IoT chips in the billions, foundries, EDA and IP vendors have put a new emphasis on revisiting their offering for larger nodes. The biggest motivation for this is the need for lower power and the proliferation of wireless. When we say lower power, it’s not about needing fewer cooling fans, its about running for months on solar power, or making a wearable last for weeks before it needs to be recharged.

For wearables, using a larger battery is not an option. A typical wearable LiPo battery might have less than 20 milliamp-hours at 3.7V. Sleep modes need to be in the uA, not milliamp range. Every trick in the book is needed: voltage Islands, power islands, low leakage libraries, sub threshold operating voltages.

Apparently TSMC has been thinking about these issues for a while and concluded that updating processes alone will not solve the power problems faced by new products. So TSMC has announced the development of IoT platforms with several of their OIP partners. For its part TSMC is rolling out ultra low power (ULP) versions of its 0.18u, 90nm, 55nm, 40nm and 28nm processes. Several of them will come with embedded flash and the ability to support radio design.

TSMC expects the ULP processes to reduce operating voltages by 20% to 30%. That combined with standby power reductions promises to offer 2X to 10X increases in battery life.

TSMC has announced that the following partners are participating:

ARM – IoT subsystems for the Cortex-M and Cordio radio IP. Running on the 55nm ULP process, they can run below one-volt, saving significant power.

Cadence – Also targeting 55nm ULP, they offer Tensilica Fusion DSP’s for sensor and peripheral interfaces operating at optimal power levels. Tensilica cores are available for WiFi/IoT connectivity for wearables and other IoT applications. 40ULP and 28ULP are also available.

Dolphin Integration – Bringing ultra low power methodologies and flows for designing ultra low power designs that include voltage and power islands. They are providing tools to effectively reduce dynamic and static power for designs targeted by the TSMC partnership.

Imagination – IP for ultra low power designs. They are providing processor cores, wireless and other ancillary functions implemented as reference IoT subsystems. Imagination offers comprehensive IP for building a large number of IoT applications.

Synopsys – Working on an integrated IoT platform on TSMC’s 40nm ULP process. This will include a broad range of DesignWare IP. The highlights are the ultra low power ARC EM5D processor core, power and area optimized libraries, memory compilers, NVM as well as a number of IO and sensing blocks.

All of this represents a large commitment on the part of TSMC and their partners to create the processes and flow enablers necessary to fulfill projected design and volume demands fron the explosive growth of ultra low power connected designs for the IoT.

For more information on applications for different process nodes look on their site.

August 20, 2015July 18, 2025

Synopsys Q3 Results

Synopsys Q3 Results
by Paul McLellan on 08-20-2015 at 7:00 am
Categories: EDA, IP, Synopsys

Synopsys announced their quarterly results this afternoon. It is the end of their Q3 (yes, they are not on the regular calendar year. Neither, for that matter, is Mentor who announce tomorrow). On the earnings call Aart started off:Good afternoon. I’m happy to report that our third quarter results were very strong, as we achieved revenue of $556 million, non-GAAP earnings per share of $0.63 and $275 million in cash flow from operations. In addition, we closed several key acquisitions, as we continue to strengthen and evolve the company for long-term growth. As a result, we are again raising our annual revenue guidance.

That is up 6.5% year on year, and in their guidance they said they expect 10% growth for the whole year. Some of that is Atrenta; in the questions someone asked whether that was in this quarter and not last year’s compare. But Aart sees at least signs of clouds on the horizon, which isn’t surprising given what looks like increasing weakness in China. He continued:Characterizing the customer environment around us, the semiconductor and systems industry results and outlook remain mixed. Customer growth rates appear more challenged than three months ago as some customers thrive while others struggle.

Like Lip-Bu on the Cadence call, he also pointed out that consolidations are continuing in the semiconductor (aka customer) space, which tends to be a headwind for EDA. Somehow an acquisition like Avago and Broadcom never seems to spend as much as the two companies did separately before. But at least they continue to invest in advanced designs.

Aart claimed that the number of active FinFET designs and tapeouts to-date is now nearly 240 and that Synopsys is “relied on” for 95% of these. That makes it sound like everyone is using DC and ICC2. I’m sure that is true in that some Synopsys tools are used but I don’t think Cadence would be close to making its numbers if it was only in 12 of those 240 designs. For ICC2 in particular Aart said they have 38 customer logos with over 100 production designs and tapeouts, way up from last quarter.

As I talked about when I interviewed John Koeter, Synopsys have been making a big push into automotive electronics. Aart talked a bit about that:In June, we rolled-out a broad set of IP optimized for automotive chip development. The portfolio now meets key safety, reliability and quality requirements while continually being enhanced to address new emerging standards. We have also worked with industry leaders such as Freescale, Infineon and Renesas to create Automotive Centers of Excellence with our virtual prototyping products, enabling our mutual customers to accelerate software development.

I spent a lot of time especially at VaST (which Synopsys acquired) trying to get virtual prototyping products into automotive companies and their suppliers, with some success. But automotive moves so slowly, working on model years that are so far out that as a startup you run out of money before the products proliferate (which, to be fair, is not only a problem with automotive. More startups fail by being too early than by being too late, it seems to me).

My Tryst with Semiconductors and EDA

My Tryst with Semiconductors and EDA
by Pawan Fangaria on 08-19-2015 at 4:00 pm
Categories: EDA, General

Yes, today I realize it feels like a tryst with semiconductors. In actual meaning; it wasn’t a love affair with semiconductors, but I must say the greatest thing it taught me about how it approaches towards perfection. And that became the guiding principle in my life; how can I do something better. Of course nothing is perfect in life and in science, as far as I know, however things can always move towards perfection. The semiconductor manufacturing professionals can tell how they strive to gain perfection in moving to newer and newer technology processes.

When I was in primary level school, I was told that light moves in a straight line; in secondary level school, it still moved in straight line, but it could refract and deflect. In college level, I learnt that light has waves and it is actually not a straight movement, of course we cannot see those waves. Now when I realize about these waves’ real implications during semiconductor manufacturing at the nanometer scale, it’s inspiring, that’s closer to perfection. The perfection is not over yet; now we are talking of EUV, 7nm and 5nm process.

Let me reflect a little on my encounter with semiconductors and EDA. During initial schooling I was fascinated towards aeronautical engineering; computer was not known to me at that time. But during undergraduate college level, I had chosen physics as my major subject and I was attracted towards solid state physics. Computers (PCs) had arrived during my engineering at Indian Institute of Science. And there were chips for CPUs, memories,… Seeing VLSI as a new, emerging field and its close to perfection designs and processes, I chose VLSI as my specialization subject.

In job, again it was VLSI (CAD) division of an Indian public sector company, ITI. Being a fresh grad out of college, I remember how I had to strive to get me assigned to that division. One can imagine what kind of salary one could expect from an Indian public sector company at that time, 1990; in fact my father ridiculed me on my salary! But, in my personal opinion the life at ITI was great, a golden period when I wrote several tools for gate array, full custom and standard cell based designs and learnt a lot. We, at ITI, had a 3 micron foundry at that time, and I remember how secluded it was and how perfect, dust proof environment, chemicals, and equipments had to be maintained. So, ITI was a true, perfect catalyst in my professional and working life for my ‘tryst’ with EDA and semiconductors :). We used to review at least 10 best papers from IEEEjournals, DAC proceeding, and so on before implementing anything in our tools, so that was a real fun. That’s when my admiration grew about these global technical institutions and forums.

At ITI, in my ~5 years, we had learnt the concepts of HLS, but it was only at the conceptual level. Implementation of logic synthesis was just starting and we saw Synopsystaking world wide lead into that area. I moved to Duet Technology (long ago acquired by Motorola, now Freescale) and then to Cadence in 1997. At Cadence, it was a real eye opener for me to the world semiconductor and EDA industry. There were many things to learn – technology, tools, business, management, customers, strategic relations, partnerships, and so on. During my life at Cadence, I have seen how we have gradually moved the level of abstraction up at several stages of design to address manufacturing issues – DFM, DFY, and so on. That’s when I realized we could do lithography awareness at the floorplanning level; that gave me a patent awarded at that time!

Today, at sub-20nm we are seeing designs becoming highly vulnerable to variability effects. The perfection at 90nm or 45nm no more works at 20nm. So, the scale of perfection in designs has to be improved further to get a working chip discounting variability. And we are seeing tools accounting for variability effects now; specialized formats have evolved to specify variability.

Semiconductor and EDA has been an interesting discipline in my life which tells me that nothing is perfect, but you can make it perfect to work within a set of parameters and that can go up to the levels of electrons and protons. That’s physics, that’s engineering! Nothing is absolute, absolutely!

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

August 19, 2015

Seeing Firsthand How the Internet has Changed Traveling

Seeing Firsthand How the Internet has Changed Traveling
by Tom Simon on 08-19-2015 at 12:00 pm
Categories: General, IoT, Mobile

We hear a lot of talk about the internet improving our lives, but most of the time this translates into time spent on FaceBook, shopping on Amazon or other distractions. However, on our just completed trip to Europe I discovered how mobile internet connectivity can transform the experience of traveling.

At home when I drive places I use Waze. It is extremely useful for getting directions and also avoiding traffic on routes you know well. If you are not familiar with Waze, it is a crowd sourced traffic app with real time route planning to avoid traffic jams. Also I occasionally use Google Maps to find shops, restaurants, etc. At home these things are nice to have. Believe me they help, but they are not what I would call essential.

Now let’s go back the early eighties when I traveled in Europe as a young backpacker. There simply was no finding a wifi hotspot and checking in on Facebook so your friends know where you are. I remember looking for the Bundespost so I could wait in line to make a phone call back to the US. I did this about once a week so my parents would know I was OK.

Even though my present day mobile carrier wanted a fortune for calls from Europe back home, I was able to use the Google Hangouts Dialer to make calls for free to the US as long as I had decent wifi. I use Google Voice for all my calls and I was able to just forward my incoming calls to Hangouts to avoid cell minutes – all on my phone.

But the big win was finding and getting to places. It used to be that if you needed to use a subway to get somewhere it was some work but totally doable, however buses and sometimes even trams were a bit of problem. Is this the right bus? Is this my stop? With GPS and Directions in Google Maps all of this became child’s play. Even parsing the Paris metro no longer requires assuming the self-identifying tourist-posture in front of the system map. This is an important tip for avoiding becoming a pick pocket victim. Everyone else is looking at their phones too – it makes it easy to “fit in.”

One of the best examples of how empowering having all the train schedules and transit info in the palm of your hand, while traveling in a country where you do not speak the language, is when the unexpected happens. Three times in our most recent trip we had trains stop mid-route because of air conditioning failures due to the extreme Summer heat.

Invariably we were told to get off in some small town, where we were left to figure out a new route. At one point we were in a crowd of about 100 people forced off a train and told to wait in 90+ degree temperatures for a bus to take us to our destination. However, it seemed no bus was coming for us. Then a local bus came by and people rushed it only to realize it was not the ‘replacement’ bus. Using Google I determined that we could use this local bus and then a train to get to Linz in time to catch our connection to Halstatt.

The best part was that I had to convince the German speaking bus driver that our plan to get to Linz would work. Our uncrowded and air conditioned bus pulled away from the milling crowd, with us safely on our way to our next destination.

Without the mobile phone, internet connection and Google Maps, we would have been left in the sweltering heat wondering if and when a bus might come, and then have to jam onto it with dozens of other stranded travelers.

This only scratches the surface of just how useful connectivity was on the trip. In a subsequent post I will talk about navigating to hotels, restaurants and water holes. One thing that is certain is that we did more, saw more and fretted less about navigation on this trip than any previous trip I have taken overseas because of the information at my finger tips.

August 19, 2015June 14, 2019

Only One Type of OEM Seems to Work in EDA

Only One Type of OEM Seems to Work in EDA
by Paul McLellan on 08-19-2015 at 7:00 am
Categories: Concept Engineering, EDA

OEM agreements don’t seem to work in EDA. Sometimes they are signed but usually they turn out to be closer to joint marketing agreements. The reason seems to be that EDA software is complex and requires high-touch support especially when getting the product first installed and introduced into a production flow. The effect of this is that if a big EDA company has an OEM agreement with a small company, then the customer knows they will get better supported by working directly with the small company who is more knowledgable about the product and more focused.

Another issue is that big EDA companies typically do large deals on a whole bundle of software for a period of time, typically three years. Nobody really knows how much revenue should really be attributed to which product, not even the customer nor the large EDA company. The methodology I’m familiar with is to use a uniform discount: take the list price for all the products, add them up and then apply a discount percentage to get to the deal size. Then use that discount number to each individual product to allocate the money to different product lines. However, doing business that way doesn’t really work with OEM products that have some sort of royalty or license fee associated with them. A few copies of an OEMed product just complicate the deal. EDA salespeople are notoriously risk-averse since they make most of their money rolling up big deals to sell companies software that they had in the previous deal. So the last thing they want is something that slows down the deal closing. In fact, it is often hard to get them to put their own new products into the deal unless the customer is begging for them because.

A further issue is at the strategic level. Let’s say a big EDA company has a hole in its offering that another company fills and signs an OEM agreement. Either the big company doesn’t sell much in which case why bother, or they sell a lot meaning the hole is really important and they should probably do an acquisition. But now they have to buy back their own revenue, or worse, another big EDA company pays even more and they are back to having a hole again.

The one type of OEM agreement that does seem to work is for components. The one I am most familiar with is Concept Engineering. Many EDA companies need a schematic viewer, that takes the netlist (or the netlist data-structure) and produces an attractive graphical representation with the cells neatly placed and the wires neatly routed. Every EDA company (except Synopsys, who I guess needed a schematic viewer to even develop Design Compiler) uses the viewer from Concept Engineering. We used it at Ambit years ago, and then continued after we were acquired by Cadence. I’ll be surprised if Cadence’s new Genus synthesis tool doesn’t use it still. Concept Engineering has been delivering this technology for 25 years now.

The reason this type of OEM deal works and product ones do not is that it is a component of the product. The customer buys the product and gets the component included. The salesperson doesn’t worry about the component slowing down their deal. The customer doesn’t worry about trying to get special support from the original creators.

Concept Engineering also sells tools in the StarVision suite based on the same underlying technology. These tools are primarily used by companies importing IP to look at the blocks and gates and transistors to understand the IP quickly to be able to use it in a design or, perhaps, make modifications. But this is a product that those design groups want to get directly from Concept Engineering and its distributors, not through a large EDA company. And so that is what happens. It is almost the perfect exception to prove the rule that OEM agreements only work for components.

August 18, 2015December 27, 2023

EVS Codec: The Next Big Thing in Mobile Voice

EVS Codec: The Next Big Thing in Mobile Voice
by Majeed Ahmad on 08-18-2015 at 4:00 pm
Categories: Ceva, Mobile

What is the next big thing in LTE-based 4G mobile networks? Apparently, it’s Voice over LTE (VoLTE) these days, especially after 3GPP has released the Enhanced Voice Services (EVS) codec that industry watchers call a breakthrough in audio and voice communications.

Long Term Evolution or LTE is the first cellular system that has been developed for data applications from grounds-up. So voice service has mostly been a dilemma for the LTE business. Initially, mobile operators began moving the voice calls to the 2G and 3G networks as a stop-gap measure. Then, in the early 2010s, mobile operators like MetroPCS and SK Telecom started launching VoLTE services that used both AMR narrowband and wideband codecs.

The 2G cellular networks, such as GSM and CDMA, mostly use adaptive multi-rate (AMR) codec that operates on narrowband 200-3400 Hz signals at variable bit rates in the range of 4.75 Kbps to 12.2 Kbps. However, the traditional voice standard—also known as AMR narrowband or AMR-NB—falls short in terms of voice clarity and noise cancellation because it sacrifices voice quality to enable lower bandwidths.

EVS is a major breakthrough for VoLTE service

The AMR wideband or AMR-WB standard improves speech quality and audio coding through a wider bandwidth of 50-7000 Hz and consumes relatively less channel capacity, from 12 kbps to nearly 24 Kbps. The AMR-WB codec—synonymous with HD voice—features enhanced audio processing, multiple microphones and speakers and improved echo cancellation to enhance voice quality and reduce background noise.

However, AMR-WB has taken too long for commercial realization, and the fact that devices on both ends are required to be HD voice-capable has led to limited availability. Then, in 2014, 3GPP finalized the EVS codec that goes well beyond AMR-WB in terms of speech quality, wider frequency range, and bandwidth utilization.

The Physics of EVS

The EVS voice codec offers HD quality voice of AMR-WB in less bandwidth than the AMR-WB codec. So, mobile operators like T-Mobile, now using 24 Kbps for HD voice, can employ super-wideband EVS and have the same audio quality with 5.95 Kbps to 7.36 Kbps. Furthermore, EVS enables innovative music and audio applications like live-to-air studio quality calls from mobile phones.

EVS uses 50 Hz to 14 KHz bandwidth that encompasses narrowband, wideband, super-wideband and full-band voice communications. It’s backward compatible with both AMR-NB and AMR-WB codec standards and can be used for even 2G and 3G networks to reduce bandwidth demands while maintaining the same voice quality. EVS has put in place error resilience mechanism for both circuit-switched 2G and 3G voice services as well as packet-switched Voice over IP (VoIP) applications.

EVS and the evolution of mobile voice
(Image credit: Qualcomm Inc.)

EVS, a robust codec that uses unique concealment techniques to minimize errors, is able to quickly recover from lost packets. Moreover, it boasts highly efficient jitter buffer management as well as channel-aware mode (CAM) for partial redundancy. Next, EVS features source-controlled variable bit-rate (VBR) adaptation for better speech quality at the same average active bit rate than fixed rate coding.

That allows mobile operators to optimize network capacity and voice call quality as desired for their service. However, the fact that EVS is able to offer unprecedented quality for speech, music and mixed content also means that it’s an intensive codec in terms of computational requirements. According to technology watchers, it’s six times more powerful than ARM-WB in terms of processing requirements.

Merits of a DSP Audio Solution

The EVS audio codec mandates a dedicated DSP solution designed specifically for voice processing. The super-wideband EVS codec, which provides excellent voice and audio quality on any mobile network, requires substantially higher signal processing power to run sophisticated multi-microphone noise reduction and echo cancellation algorithms.

CEVA, the supplier of DSP cores, is one of the firms proactively supporting the new voice codec. It has recently announced the availability of EVS voice codec for its TeakLite family of audio DSPs. CEVA provides EVS capability in the form of audio and voice software package that can run on the TeakLite DSPs.

TeakLite-4 processor is specially designed for codecs like EVS

A CPU that is not specifically designed for voice processing will simply consume too much MHz and power. Even a dedicated voice DSP like the TeakLite-4 that is specifically designed for such codecs takes quite a lot of MHz capacity. In fact, the performance of EVS and appropriate dual-microphone noise reduction can take up to 6mW when optimized for the TeakLite-4 DSP.

It’s worth noting that memory footprint of both code and data is quite large in EVS voice codec, and that mandates adequate memory mechanisms like caches. The CEVA-TeakLite-4 DSP core has all the required memory mechanisms like caches and advanced memory management.

Moreover, TeakLite-4 has a dedicated voice processing functionality and not just general DSP functionality like the M7 processor. In a nutshell, a DSP offers better performance for less area compared to the M7 microcontroller because of its dedicated voice processing ISA and memory management capabilities.

CEVA achieves first certified Bluetooth 4.2 IP

CEVA achieves first certified Bluetooth 4.2 IP
by Don Dingee on 08-18-2015 at 8:05 am
Categories: Ceva, IoT, IP

SoC designers working on chips for the IoT and wearables now have access to cutting-edge certified Bluetooth Smart technology from CEVA. At Bluetooth ASIA in Shanghai, CEVA announced the RivieraWaves Bluetooth Smart 4.2 IP Platform has achieved full certification by the Bluetooth SIG to the Bluetooth 4.2 specification using the current, most stringent testing suite.
Continue reading “CEVA achieves first certified Bluetooth 4.2 IP”

August 18, 2015

Jen-Tai Hsu Joins Kilopass and Looks to the Future of Memories

Jen-Tai Hsu Joins Kilopass and Looks to the Future of Memories
by Paul McLellan on 08-18-2015 at 7:00 am
Categories: IP, Kilopass Technology

Kilopass has a new VP of engineering, Jen-Tai Hsu. I sat down with him last week to find out where he came from and where he and Kilopass are going.

He grew up in Taiwan and went to National Taiwan University where he studied electrical engineering. Then he came to the US and went to Case Western Reserve University to get a masters degree, studying MEMS/Silicon sensors, and finally to UCLA for a PhD in EE device physics. That is enough education for anyone, so time for a real job.

He started working at National Semiconductor as a process integration engineer on flash memory for a couple of years. Then he went to Intel where he ended up staying for 12 years. He continued to work on flash memory before moving into product engineering. Intel was the first company getting two bits into a cell using 4 different voltage levels technology (Multi-Level Cell, or MLC) with project code name Voyager. After a couple of years he moved to what we would today call an IP group working on the various forms of SERDES needed for the PC business: USB, PCIe, SATA and so on.

I think that it was at VLSI Technology where the first PC chipset was developed. We had IP blocks, that we called megacells, for all the chips that made up the rest of the motherboard beyond the processor and memory. Over a weeked a group threw together a chipset and it looked feasible. This became a huge business for VLSI over the next years. Intel bundled our chipset, called Topcat, with their processor, I forget whether they stamped Intel logos on them. But we always knew that eventually it would be Intel’s business since they knew all about next generation processors ahead of anyone else, by definition. Anyway, that became true and Jen-Tai spent 9 years working on chipsets at Intel until, in 2008, he left to join GUC.

GUC (Global Unichip Corporation) is a subsidiary of TSMC that does designs for customers and then uses TSMC as a foundry to manufacture them. As the ASIC business changed from being all about gates to being about IP too, every design services company needed access to IP, preferably that they had developed in-house to give them some differentiation from all the other design services companies. Often this IP is a family of SERDES interfaces since they are needed for a huge number of designs and they are beyond the abilities of many design teams to do themselves. The way GUC was organized the job was still very technical since Jen-Tai was both the senior director of the group and also owned the top level design. GUC had been using Synopsys’s IP but once the internal development was successful they switched to their using their internally developed IP. This enabled them to win heavyweight contracts from major networking manufacturers, major telecoms companies and more. IP revenue ramped up from nothing to tens of millions.

The next step was to Pericom as VP engineering doing analog intensive design. Low cost high margin chips competing with the usual suspects: NXP, TI, Maxim, IDT. They had a number of different design centers all with their own methodology, which he unified so everything was much easier to integrate.

Finally, to where we are today, he joined Kilopass. He loves going to the fundamentals of technology and memories are the cutting edge of bringing process technology to life as products.

Kilopass are known for one-time-programmable (OTP) memories, both small registers used to hold encryption keys or capture which redundant DRAM columns should be disabled, and also larger memories to hold code. Their current architecture has a read access time of around 30-40ns, the next generation should be below 20ns and consume just 1/10 of the power. This is obviously perfect for IoT type designs that need to get power as low as possible.

Kilopass is also working on new memory technology for the SRAM/DRAM type market. So not one-time-programmable. However, they haven’t announced details yet so you’ll have to wait until the new year to unwrap that particular present.

The press release announcing Jen-Tai’s appointment is here.

August 17, 2015

My Top Ten Regrets if I were Dying?

My Top Ten Regrets if I were Dying?
by Daniel Nenni on 08-17-2015 at 4:00 pm
Categories: General

As birthday #55 rapidly approaches I say to myself: Self, if I were dying what would be my regrets? The first thing I did was ask The Google because I’m not coming up with anything really interesting myself. Also, it really isn’t a pressing problem for me as my life expectancy has increased quite a bit over the last 30 years, or so I’m told. Of course I could die from a Taiwan taxi ride this week so it is something to think about no matter what your circumstances are.

When my wife and I decided to start a family I purchased a very large life insurance policy. We both agreed that one of us should stay home and care for the children (we have two boys and two girls) so we would be single income for quite a while. I was a rising star in Silicon Valley so she stayed home. During the life insurance policy process they came up with a life expectancy for me of 68 years. At the time that sounded pretty good since my father died in his early forties and I lost a younger brother.

Fast forward to today, based on a recent study my life expectancy is now about 15- 20 years longer. Part of it is my fitness, diet, and family life, which is excellent. The other part is advancing medical science and being proactive with regular blood tests and check-ups. I had a very near death experience and that put me on this journey of health and wellness but I digress…

According to The Google here are the top ten regrets of dying people:

[LIST=1]

I should have pursued my dreams and aspirations

I worked too much and never made time for my family

I should have stayed connected with my friends

I should have said I love you more

I should have spoken my mind more

I should have resolved more conflicts

I should have had children

I should have saved more money for retirement

I should have had the courage to live truthfully

I should have let myself be happier

Okay, that was no help because I have all of those pretty much covered. I have also traveled extensively and have but one thing left on my official bucket list (run with the bulls in Spain) but my wife won’t let me. I think my greatest concern is living long enough to enjoy my grandchildren with a reasonable quality of life and that brings us to semiconductors.

Quite frequently I’m asked where semiconductor growth will come from after smartphones. IoT is an easy answer but specifically what in IoT? For me it is health and wellness. Picture this: You swallow a pill sized nanochip and the doctor uses a VR headset to see what is really going on inside your body. If he finds something, you swallow a nanobot to make the appropriate adjustments. Not too far-fetched if you watch Game of Thrones and see what kind of medical science was available back then.

Circling back to the dying regrets thing, what I would really like is a five minute warning before I die because I think my biggest regret would be dying in a Starbucks or on the toilet like Elvis. Make an app for that and it would be the next Uber sized unicorn, absolutely.