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June 25, 2015

Heard on the Street at ITF

Heard on the Street at ITF
by Paul McLellan on 06-25-2015 at 7:00 pm
Categories: Foundries

As I said yesterday, I’m at the imec Technology Forum (ITF) in Brussels. So what have I learned from all the people that I’ve interacted with.

There were two press releases announced at a press conference yesterday. The first was that imec was expanding its relationship with Toshiba and Sandisk. This covers bringing EUV into volume manufacturing and other things. You may know that imec has major partnerships with the four biggest non-memory semiconductor manufacturers (Intel, TSMC, GlobalFoundries and Samsung) and with the four main memory manufacturers (Micron, SK Hynix, Toshiba/Sandisk and Samsung again). Toshiba/Sandisk had an existing relationship with imec but only for the memory aspect of the business. This announcement expands the relationship to cover non-memory processes.

As Dan already reported about the creation of a research company based in Chinese, with majority ownership from SMIC and minority ownership from Huawei, Qualcomm China and imec themselves. I was at the press conference where we asked questions of imec. Funnily enough it had the shortest embargo I have ever come across. It is 1.35pm and they tell us it is embargoed…until 2pm when the announcement was to go out in China. There was very little information other than what was in the press release. You probably know that China has committed billions of dollars to creating a domestic semiconductor industry with a 14nm process available by 2020. Of course there is more than just money to developing a 14nm process, just ask GlobalFoundries.

See UMC and SMIC 14nm Too Little Too Late?

We asked if the process was going to be FinFET. After a little discussion they were not allowed to say, although leakage would have to be a killer if it was just a vanilla planar process. We asked if export restrictions make it impossible to transfer a process from Samsung or someone else. Nobody knew. They just knew that they were in compliance with export regulations, hardly surprising.

I disagree with Dan that this is too little too late. China has made it a strategic imperative to have a growing proportion of domestic semiconductor content. If the development succeeds in creating a 14/16nm process that yields well, then it will be heavily used by Chinese companies even if by nobody else. Not just Huawei and Qualcomm, who are in the consortium, but also Lenovo, Xiaomi and more. If you look at the top 10 smartphone companies, it is lead by Apple and Samsung. But the rest of the list, apart from LG, is made up of Chinese companies some of which you have barely heard of. And it does matter, China is the largest smartphone market in the world, much bigger than the US, so the semiconductor content is important.

There is increasing distrust between China and US. For example, US carriers are either banned or “discouraged” from using Huawei kit since maybe the Chinese have trapdoors in them. Of course this is almost hilarious now we have discovered what the NSA has been doing, intercepting Cisco routers en route to their customers and compromising them. Do you think the Chinese would trust that mask data at GlobalFoundries in New York has not been compromised in some way by the security services? I doubt that US defense suppliers will be using SMIC as their foundry for similar reasons.

I learned a lot of doubts about EUV from talking to people at last nights dinner. But I covered them in yesterday’s post on EUV. The big issues being mask contamination under the pellicle, the non-availability of defect free masks (actually silicon molybdenum Bragg mirrors), and management of heat when you have a 250KW laser generating light of which under 10% is EUV of which under 10% reaches the photoresist. That’s a lot of waste heat to dump.

3 Design Hooks of Atmel MCUs for Connected Cars

3 Design Hooks of Atmel MCUs for Connected Cars
by Majeed Ahmad on 06-25-2015 at 7:00 am
Categories: IoT

In February 2015, BMW reported that it has patched the security flaw which could allow hackers to remotely unlock the doors of more than 2 million BMW, Mini and Rolls-Royce vehicles. Earlier, researchers at ADAC, a German motorist association, had demonstrated how they could intercept communications with BMW’s ConnectedDrive telematics service and unlock the doors.

BMW uses SIM card installed in the car to connect to a smartphone app over the Internet. Here, the ADAC researchers created a fake mobile network and tricked nearby cars into taking commands by reverse engineering the BMW’s telematics software.

Security is a big concern in connected cars

The BMW hacking episode was a rude awakening for the connected car movement. The fact that prominent features like advanced driver assistance systems (ADAS) are all about safety and security is also a testament is that secure connectivity will be a prime consideration for the Internet of cars.

Built-in Security

Atmel Corp. is confident that it can create secure connections for the vehicles by merging its security expertise with performance and low-power gains of ARM Cortex-M7 microcontrollers. The San Jose, California–based chip supplier claims to have launched industry’s first auto-qualified M7-based microcontrollers with Ethernet AVB and media LB peripherals. Atmel’s high-end MCU series for in-vehicle infotainment also offers the CAN 2.0 and CAN flexible data rate controller for higher bandwidth requirements.

Nicolas Schieli, Automotive MCU Marketing Director at Atmel, acknowledges that security is something new in the automotive environment that needs to be tackled as cars become more connected. “Anything can connect to the controller area network (CAN) data links.”

Atmel offers the ability to integrate cryptos in auto embedded designs

Schieli said that Cotex-M7 has embedded enhanced security features within its architecture and scalability. On top of that, he added, Atmel is using its years of expertise in Trusted Platform Modules and crypto memories to securely connect cars to the Internet. Schieli also mentioned the on-chip SHA and AES crypto engines in SAM E70/V70/V71 microcontrollers for encryption of data streams. “These built-in security features accelerate authentication of both firmware and applications.”

He explained how the access to the Flash, SRAM, core registers and internal peripherals is blocked to enable security. It’s done either through the SW-DP/JTAG-DP interface or the Fast Flash Programming Interface. The automotive-qualified SAM V70 and V71 microcontrollers support Ethernet AVB and Media LB standards, and they are targeted for in-vehicle infotainment connectivity, audio amplifiers, telematics and head control units companion devices.

Software Support

The second major advantage that Atmel boasts in the connected car environment is software expertise and an ecosystem to support infotainment applications. For instance, a complete automotive Ethernet Audio Video Bridging (AVB) stack is being ported to the SAM V71 microcontrollers.

Software support is a key leverage in highly fragmented markets like automotive electronics. Atmel’s software package encompasses peripheral drivers, open-source middleware and real-time operating system (RTOS) features. The middleware features include USB class drivers, Ethernet stacks, storage file systems and JPEG encoder and decoder.

Next, the company offers support for several RTOS platforms like RTX, embOS, Thread-X, FreeRTOS and NuttX. Atmel also facilitates the software porting of any proprietary or commercial RTOS and middleware. Moreover, the MCU supplier from San Jose features support for specific automotive software such as AUTOSAR and Ethernet AVB stacks.

Atmel claims its customers have built designs in a few weeks

Atmel supports IDEs such as IAR or ARM MDK and Atmel Studio and it provides a full-featured board that covers all MCU series, including E70, V70 and V71 devices. And a single board can cover all Atmel microcontrollers. Moreover, the MCU supplier provides Board Support Package for Xplained evaluation kit and easy porting to customer boards through board definition file (board.h).

Atmel is also packing more functionality and software features into its M7 microcontrollers. Take SAM V71 devices, for example, which have three software-selectable low-power modes: Sleep, Wait and Backup. In Sleep mode, the processor is stopped while all other functions can be kept running. In Wait mode, all clocks and functions are stopped but some peripherals can be configured to wake up the system based on predefined conditions.

In Backup mode, RTT, RTC and wake-up logic are running. Furthermore, the microcontroller can meet the most stringent key-off requirements while retaining 1Kbyte of SRAM and wake-up on CAN.

Transition from MPU to MCU

Cortex-M7 is pushing the microcontroller performance in the realm of microprocessors. MPUs, which boast memory management unit and can run operating systems like Linux, eventually lead to higher memory costs. “Automakers and systems integrators are increasingly challenged in getting performance point breakthrough because they are running out of Flash capacity,” said Atmel’s Schieli.

On the other hand, automotive OEMs are trying to squeeze costs in order to bring the connected car riches to non-luxury vehicles, and here M7 microcontrollers can help bring down costs and improve the simplification of car connectivity.

SAM V71 MCU lowers system cost by replacing MPU

The M7 microcontrollers enable automotive embedded systems without the requirement of a Linux head and can target applications with high performance while running RTOS or bare metal implementation. In other words, M7 opens up avenues for automotive OEMs if they want to make a transition from MPU to MCU for cost benefits.

However, the MPU and MCU worlds are constantly converging and colliding, and the difference between them is not a mere on-off switch. It’s more of a sliding bar. Atmel, having worked on both sides of the fence, can help hardware developers to manage that sliding bar well. “Atmel is using M7 architecture to help bridge the gap between microprocessors and high-end MCUs,” Schieli said.

Samsung: the Journey to 14nm and 10nm

Samsung: the Journey to 14nm and 10nm
by Paul McLellan on 06-24-2015 at 7:00 pm
Categories: FinFET, Foundries, Samsung Foundry

At the Samsung theatre (cutely named the Samsung Open Collaboration (SoC) theater) I watched a presentation by KK Lin on using DFM to bring up their 14nm and 10nm processes. And yes, they are real. Here is a picture I took of a 14nm wafer and a 10nm wafer. Samsung announced that they would ramp 10n to volume production by the end of next year, 2016.

KK explained that Samsung uses DFM in two different ways (two “faucets” as the misprint on the slides has it). Design Enablement (DE) DFM is used to fix up design mask data. This is primarily optical proximity correction (OPC) and is used since 193nm light is being used with immersion lithograph (and double patterning for some layers) to print features much less than the wavelength. However, just doing that still leaves “hot” spots on the wafer where failure is more likely if the lithography and manufacturing is not absolutely perfect.

So another stage of DFM is Process Enablement (PE). Obviously a lot of process monitoring is done in a completely design independent ways using various process control monitors (PCMs). But that alone doesn’t get the yield ramp up fast enough for today’s consumer market places especially mobile. It used to be that a ramp to volume would take a couple of years, and now it is expected within a few months of final qualification. So the PE DFM is used to do design aware process monitoring and fault analysis. It is simply not possible to look at a whole wafer in any reasonable time at a resolution that can spot problems (“looking for a golf ball in California” is one way I’ve heard it described) so knowing where the hot spots and failures are most likely to be found makes it tractable.

KK’s conclusion:

Samsung Foundry provides comprehensive closed-loop DFM solutions at both design and process level
During design DFM signoff tools and flows are used to prevent failures
For process ramp, DFM is fed forward for defect monitoring, detection and estimation
Samsung Foundry 14/10nm DFM are synergized to serve customers’ collaborative yield learning. Not 100% sure what that means, maybe sounds better in Korean. But I think it means that by using DE and PE DFM they can ramp the leading customer designs to volume faster

Also on the Samsung booth was a nice demonstration of how much lower power FinFET is than planar. They had two smartphones running video. In one the application processor was 28nm HKMG, and in the other it was 14nm FinFET. If you look closely at the screens on the two phones, you can see that the one on the left has a temperature of 62°C and the one on the right 86°C.

They also had continuous displays showing the instantaneous power dissipations for the two phones. At the moment that I took the pictures, the 28nm chip was disippating almost 1.5W whereas the 14nm chip was 0.8W, close the half the amount of power.

June 24, 2015

A Closer Look at Fab Closures Around the World

A Closer Look at Fab Closures Around the World
by Pawan Fangaria on 06-24-2015 at 12:00 pm
Categories: Foundries

Electronics is unusually an evergreen industry where companies make profit, yet end-product prices go down significantly after a brief period of price skimming. A product phases out quite fast (in case of smartphones every 1.5 to 2 years), but still yields big bucks for successful companies in its value-chain. How does this happen? How long it will continue to happen?

Well, the answer to the first question is highly capital intensive fabs with large wafer capacities and intelligent brains to invent newer ways of doing things with better YoR(Yield of Results), lesser CoR (Cost of Result), and lesser ToR (Time of Results). Of course, the worldwide demand lets it happen too. However, the demand does not sustain beyond a certain price-point; IoT (Internet of Things) market is a live example today, there is a tremendous latent demand, but at low price-point. The end result is – the price reduction has to continue, perhaps with reduction in OPM (Operating Profit Margin) of the companies. So, one can guess, the semiconductor business which started as a ‘blue ocean’ in the last century started turning ‘red’ due to couple of economic recessions and slowdown in this century. Several efforts are being made to keep the water ‘blue’, but how long will it remain blue and to what extent? Let’s analyze some data from an IC Insights’ report about fabs, published last week.

Between 2009 and 2014, just after the last global economic recession which started in 2008, 83 wafer fabs were either closed or repurposed. Majority of the fabs that were closed were 200mm and below wafer fabs. Arguably, the move was towards larger wafers to produce devices at lower cost. However, the economic stress is visible with the closure of some 300mm wafer fabs too in 2013.

This shows the need of consolidation in fab business. Although large mergers have happened in the past, or happening currently, more will happen going forward. New wafer fabs, and wafers at cutting edge technology nodes are no cheaper. The only way is to cut operational cost through consolidation. To me it appears to be a case of good business opportunity for large pure-play foundries like TSMC, GLOBALFOUNDRIES, UMC, and maybe Samsung foundry as well that can supply large wafers at reasonable cost, if not lower. Semiconductor designs should stay fabless.

A region wise graph of closed wafer fabs clearly shows how economies of different countries have affected the fab businesses in those regions.

Japan has closed most of the 83 fabs followed by USA and Europe. This exactly tallies with Japan, a leader in semiconductor business in 1990s, reduced to just one semiconductor company (Toshiba) in 2015 top10 list of semiconductor companies.

How will the electronics cost go down? Wafer cost is not expected to go down further. More mergers and consolidations are going to take place, and still a few 10nm and 7nm fabs will appear. If the fabs business gets consolidated at some pure-play foundry level, then the ocean may turn blue for fabs. However, the semiconductor equipment suppliers will bear the brunt because opening of new fabs will be limited. The electronics cost may stay where it is, if it does not go down further.

One thought comes to my mind is about new fabs in the regions where there are none existing; India is a live example. Should India still go for a new fab when there are fabs closing around the world? My opinion is, even if India opens a fab, it should go for the latest, not less than 300mm, may be 450mm so that it stays cost-effective and relevant for long term to recover the CAPEX and get enough ROI.

The IC Insights’ report is HERE.
Also read: Shift-West of Semicon Power Centers

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

June 24, 2015July 18, 2025

Bijan Kiani Talks Synopsys Custom Layout and More

Bijan Kiani Talks Synopsys Custom Layout and More
by Paul McLellan on 06-24-2015 at 7:00 am
Categories: EDA, Synopsys

Last week I sat down and talked to Bijan Kiani of Synopsys. He has marketing responsibility for design implementation products at Synopsys spanning digital, custom and analog mixed signal (AMS).

He was born in Iran and after high school he moved to the UK. He got his PhD degree from University of Edinburgh. It turns out that I was doing my PhD at the same time although I don’t think we ever met. He was in EE and I was in CS and despite being literally across the road, in those days the departments had little to do with each other. He then worked for Burroughs and NEC in Scotland and joined European Silicon Structures (ES2) very early on. In another coincidence I also had a job offer from ES2 but in the end I decided to stay in the US at VLSI Technology. After ES2 didn’t really go anywhere he started his own company, InCA, doing ASIC emulation and prototyping. It was acquired by Zycad.

In 1996, so nearly 20 years ago, he joined Synopsys where he held various marketing roles. Now he has marketing responsibility for the entire digital and custom implementation products. On the custom side the heart of the portfolio is the Laker product that Synopsys acquired with SpringSoft and Custom Designer being developed organically. It turns out that Laker inside Synopsys has a different dynamic in the marketplace from when it was in SpringSoft. Before the acquisition I remember talking to SpringSoft, who bemoaned the fact that it was so hard to get foundries to create PDKs in a timely manner. But Synopsys is #1 in interface IP and foundries need that IP to be supported on their leading edge processes before fabless companies can tape out designs. This puts IP on the critical path to volume ramp in the foundries for leading edge processes. Since Synopsys uses their own custom layout solution for developing the IP, they need early collaboration with foundries to enhance custom tools and develop the PDKs before they can even start. By establishing close collaboration with leading foundries they have full support of the latest technologies.

I asked Bijan why people would switch to the Synopsys solution. He said that as people move to FinFET, productivity for physical design takes a big hit because there is more to be done and checked. The complexity of new rules, restrictions such as fin placement, higher parasitics, metal track requirements and the high impact of physical effects all impact designer productivity. Using traditional custom design, productivity is reduced substantially, causing companies to take a fresh look for alternatives. Working with both the IP design centers which are active at the latest process nodes, as well as several leading customers who are the early adopters on these nodes Synopsys have developed many unique technologies that enhance basic layout editing. So they’re integrating a lot of great technologies that they have acquired such as Galaxy custom router and Helix placer to provide an assisted automation solution. Today they have very large logos that are using the Synopsys’ custom layout for FinFET or established nodes, including 5 of the top 20 fabless semiconductor companies.

Synopsys is continuing to invest heavily to bring more automation to the market. The solution is complemented with strong tools for parasitic extraction, StarRC, and physical verification, IC Validator. Users love the integration of verification with layout so that design rule violations are flagged interactively as they work. With the complexity of design rules in modern process nodes, creating and then having to fix lots of obscure violations is part of life.

Of course Synopsys has a historically strong position in circuit simulation with the various simulators it has acquired or developed over the years: HSPICE, CustomSim and FineSim. One impressive statistic Bijan told me is that all leading Flash and DRAM memory chips are being verified with CustomSim and FineSim.

Another area of strength is that designs can be moved from custom layout into ICC and back, without losing any information (as opposed to using GDSII as the transfer format). So a block can be handled automatically in ICC, then moved for custom editing or shape-based routing for critical high-speed nets in the layout editor before being moved back into ICC for further integration. As Bijan emphasized, the strongest interest in the custom solution is in advanced processes, due to the productivity hit that customer are experiencing when moving from established nodes. But a lot of custom and AMS design is done in non-leading edge processes, 65nm or 130nm. The problems are simpler there than in the leading edge processes but Bijan emphasized that the automation technologies being developed for advanced node also can significantly help improve productivity in the established nodes. Strategically Synopsys has decided to build their beach-head in the most advanced processes where their automation, integration with ICC and their IP family all play a strong role.

June 24, 2015

Growth drivers shifting to emerging economies

Growth drivers shifting to emerging economies
by Bill Jewell on 06-24-2015 at 4:00 am
Categories: Semiconductor Intelligence, Semiconductor Services

Global real gross domestic product (GDP) growth in 2015 is expected to be 3.5%, according to the International Monetary Fund (IMF) April 2015 report. 2015 is a slight acceleration of 0.1 percentage points from 3.4% growth in 2014. The IMF projects 2016 global growth of 3.8%, an acceleration of 0.3 percentage points from 2015. The table below shows GDP growth and acceleration/deceleration for advanced economies and emerging/developing economies. Key countries are listed under each category.

The advanced economies are expected to provide the growth acceleration in 2015. The United States, the largest economy accounting for about 23% of global GDP, is the largest contributor to the 2015 acceleration with GDP growth moving from 2.4% in 2014 to 3.1% in 2015 – accelerating 0.7 points. The Euro Area countries combined are the second largest economy and the second largest contributor to the global acceleration. Japan’s recovery from a 0.1% decline in 2014 to 1.1% growth in 2015 is the third major factor in accelerating GDP growth.

The emerging/developing economies as a whole are expected to show deceleration of 0.3 points, from 4.6% in 2014 to 4.3% in 2015. However these same countries drive the acceleration of global GDP growth in 2016 with 0.4 points of acceleration. Russia is in a major recession in 2015 with a forecast GDP decline of 3.8%, but begins to recover in 2016 with a 1.1% decline. Thus Russia contributes to global GDP acceleration in 2016 by being less of a drag on the economy than in 2015. South America shows a similar effect, led by Brazil and Argentina.

China has been a major driver of global economic growth for several years. Although China’s GDP is still expected to grow at almost twice the global rate, growth is projected to slow from 7.4% in 2014 to 6.8% in 2015 and 6.3% in 2016. India’s GDP growth is forecast to accelerate from 7.2% in 2014 to 7.5% in 2015 and hold at 7.5% in 2016. Thus India will replace China as the fastest growing major economy. The ASEAN-5 countries (Indonesia, Malaysia, Philippines, Thailand and Vietnam), the Middle East & Africa and Mexico also contribute to global GDP acceleration.

The overall message from the table is the advanced economies have recovered from slow growth in 2014 to close to long term growth rates in 2015 and 2016. The emerging/developing economies are still growing faster than the advanced economies, but growth leadership is shifting from China to India and Southeast Asia.

What is the impact on the electronics and semiconductor markets of these trends? The May 2015 smartphone forecast from market research firm GfK shows near term growth will depend on emerging regions, excluding China. Global smartphone unit growth is projected to slow to 10% in 2015 from 23% in 2014. China, a major growth driver and the largest single market for smartphones, is expected to show a 3% decline in 2015. The developed economies – North America, Europe and developed Asia/Pacific (APAC) – show growth slowing from 18% to 8%. The emerging economies – Latin America, Middle East, Africa and Emerging PAC – drive 2015 growth at 26%.

[TABLE] border=”1″
|-
| colspan=”6″ style=”width: 671px; text-align: center” | Smartphone Unit Forecast (Source: GfK, May 2015)
|-
| style=”width: 347px” |
| colspan=”3″ style=”width: 203px; text-align: center” | Millions of Units
| colspan=”2″ style=”width: 121px; text-align: center” | Change
|-
| style=”width: 347px” |
| style=”width: 78px; text-align: center” | 2013
| style=”width: 66px; text-align: center” | 2014
| style=”width: 59px; text-align: center” | 2015
| style=”width: 65px; text-align: center” | 2014
| style=”width: 55px; text-align: center” | 2015
|-
| style=”width: 347px” | World
| style=”width: 78px; text-align: center” | 998
| style=”width: 66px; text-align: center” | 1227
| style=”width: 59px; text-align: center” | 1355
| style=”width: 65px; text-align: center” | 23%
| style=”width: 55px; text-align: center” | 10%
|-
| style=”width: 347px” | North America, Europe, Developed APAC
| style=”width: 78px; text-align: center” | 374
| style=”width: 66px; text-align: center” | 440
| style=”width: 59px; text-align: center” | 476
| style=”width: 65px; text-align: center” | 18%
| style=”width: 55px; text-align: center” | 8%
|-
| style=”width: 347px” | China
| style=”width: 78px; text-align: center” | 359
| style=”width: 66px; text-align: center” | 393
| style=”width: 59px; text-align: center” | 383
| style=”width: 65px; text-align: center” | 9%
| style=”width: 55px; text-align: center” | -3%
|-
| style=”width: 347px” | Latin Amer., Middle East, Africa, Emerging APAC
| style=”width: 78px; text-align: center” | 265
| style=”width: 66px; text-align: center” | 394
| style=”width: 59px; text-align: center” | 496
| style=”width: 65px; text-align: center” | 49%
| style=”width: 55px; text-align: center” | 26%
|-

The PC unit forecast from IDC in May 2015 shows a 2015 decline of 6.2%. Mature markets show a slightly bigger decline of 6.6% compared to the emerging market decline of 5.9%. The emerging market decline is dragged down by China, which had an 8% decline in 1Q 2015 PC shipments versus a year ago according to government statistics.

IDC’s forecast for tablets and 2-in-1 PCs is a 3.8% decline in 2015 following 2% growth in 2014. Tablet growth in 2013 and prior years exceeded 50%.

How will these trends affect the semiconductor market in 2015 and 2016? The slowing of key market drivers such as smartphones and tablets will limit growth for semiconductors. The first quarter of 2015 started weakly with a 4.9% decline from 4Q 2014, according to World Semiconductor Trade Statistics (WSTS). The outlook for 2Q 2015 revenue growth for key semiconductor companies is mixed, as shown below.

Several companies are guiding for 2Q 2015 growth with around 3% at the midpoint (Intel, TI, STM and NXP). The highest growth rates are from Infineon at 9% and Avago at 7%. A few companies are expecting double digit declines (Qualcomm, SanDisk and NVIDIA). Weighted average guidance is about 3%, with a high end around 5%.

Our Semiconductor Intelligence March 2015 semiconductor market forecast was 8% for 2015 and 7% for 2016. Based on the weak 1Q 2015 and moderate expectations for 2Q 2015, we have lowered our 2015 forecast to 5.5%. We are maintaining our 2016 forecast of 7% based on some improvement in the global economy and slightly better prospects for the key drivers of smartphones and tablets.

The chart below shows recent forecasts for 2015 and 2016. 2015 forecasts are in a narrow range, from WSTS’ 3.4% to our 5.5%. Forecasts for 2016 range from WSTS’ 3.4% to our 7.0%.

Overall, the outlook for the global economy, electronics and semiconductors is slow to moderate growth over the next two years. The risk is more on the downside than the upside. Factors which could lead to slower growth are more plausible than factors which could lead to higher growth. However the prospects of an economic downturn in the near future are low.

June 24, 2015

UMC and SMIC 14nm, Too Little Too Late?

UMC and SMIC 14nm, Too Little Too Late?
by Daniel Nenni on 06-24-2015 at 1:00 am
Categories: eSilicon, Semiconductor Services

Pretty much out of nowhere UMC let fly a press release about taping out a 14nm test chip with ARM and Synopsys IP which was quickly followed by an SMIC 14nm press release about a joint venture with Huawei, Qualcomm, and imec. It caught me a bit by surprise since I spent time with both UMC and SMIC at #52DAC and nothing was mentioned. Of course Samsung and TSMC are already in production at 14/16nm and were showing 10nm wafers so maybe it would have been anticlimactic. As I mentioned before, FinFETS will forever change the foundry landscape so let’s talk about that for the remaining 400 hundred words.

Currently there are three very different versions of FinFET processes available to foundry customers: Intel 14nm, Samsung 14nm, and TSMC 16FF+. If and when SMIC and UMC are FinFET capable there will be five very different versions since UMC is licensing the IBM version and SMIC will be developing their own. UMC is expected to start FinFET production in 2016 (2017 would be my bet) and SMIC in 2020. Wait, what? 2020? Hopefully that is a typo but probably not.

Never in the history of the foundry business has there been 5 very different versions of a leading edge process offered so you have to ask yourself: “Self, just what is the fabless semiconductor ecosystem to do?” Do EDA and IP companies really have the bandwidth to support all five foundries with silicon proven FinFET tools and IP? And without the full support of the design enablement community how are all five foundries going to make money?

One thing I can tell you is that this level of competition, one which we have never seen before, will make Gordon Moore proud. The FinFET transistor cost will decrease inline with Moore’s Law despite what the idiot analysts are saying. Take a hint from the TSMC 16FFC announcement last April, 16FFC is a more cost effective version of 16FF+ aimed at the consumer marketplace. Same design rules, simpler manufacturing process (less masks), and tighter process corners. Power is said to be reduced by over 50% and the PRICING is cost-competitive against OTHER processes (meaning planar and FD-SOI).

Welcome to the new foundry landscape where cost is “MOORE” important than performance and power, absolutely. And if you believe what you read about the industry staying with 28nm forever because FinFETs are too expensive good luck with that. Let me introduce a new term for companies that linger on 28nm: FinFOOLed.

The other interesting foundry announcement is SMIC supporting the new eSilicon STAR Design Virtualization Platform. eSilicon launched this internet enabled platform with TSMC last year and I was a bit surprised that SMIC is the #2 adopter. This is a slide from the eSilicon presentation in the SMIC booth at #52DAC. You can see the full presentation HERE. Take a look at the demographics of the users, it truly is a global community. eSilicon ships MILLIONS of chips every year so yes this is a very big deal and congratulations to SMIC for being #2!

June 23, 2015

EUV: the view from imec

EUV: the view from imec
by Paul McLellan on 06-23-2015 at 7:00 pm
Categories: Foundries

I’m at the 2015 imec technology forum (ITF) in Brussels the next few days. One of the presentations today was by Peter Wennink, the CEO of ASML. The thing that most interested me in his presentation is what the status of EUV is today. ASML is the only company developing EUV steppers so what they think is important. On the other hand, they are the company building the steppers so what they say has to be looked at with some skepticism. First, what Peter said.

The motivation for EUV is that without it we will need increasingly multiple patterning. He pointed out that the biggest problem is not even the number of mask steps but the number of overlay metrology steps which goes up even faster. But EUV has to work at 7nm. It is already too late for 10nm, the plans are already set at least for the introduction. And 5nm will require double patterning even with EUV.

Since this time last year, EUV has made huge progress:

Productivity requirement 1000 wafers/day
- using 80W source printed 1022 wafers in 24 hours at one customer
- 110W power demonstrated at ASML
Availability 70%
- 55% average at multiple sites
- 82% for one week achieved at one customer
- sustained source availability about 85% on track for end of 2015
System shipments in 2015: 6
- integration of multiple systems in progress at ASML
- 2 systems on order intended for production
- volume purchase agreement with one customer (presumed by everyone to be Intel) for 15 systems of which 2 ship in 2015

Next issue, the pellicle. Clean scanner remains a priority and they are on track for 10X per year reduction in front-side defects (basically contamination from the light source or other parts of the scanner getting onto the mask, which is actually a mirror).

ASML started their own pellicle program since the traditional pellicle manufacturers were not interested. They now have a full size pellicle that covers the whole mask. Transmissivity is 85% (in one direction, the light has to go through twice though: reflective mask remember). No impact on alignment.

Inspection is a problem. Pellicle is not transparent to either visible light or e-beam so it has to be removed for mask inspection, and then replaced after inspection. Pellicle is compatible with both the mask flow and the scanner.

So it all sounds great right? Here are problems that people at the conference told me about during dinnner and breaks.

So what are the next problems?

Problems are being solved linearly. Until light source is working, nobody is worrying too much about all the other problems. Everything has to work perfectly by about 2017 if it is to be on schedule for 7nm. The equipment cannot be changed after start of qualification which is about 2 years before volume is ramped fully
Pellicle inspection. With transmissive masks, the mask can be inspected, then the pellicle added and then a final inspection done through the pellicle. With EUV can’t do that. So if a particle gets trapped under the pellicle it will print and thousands of wafers may be wasted. Currently no way to inspect unless EUV light is used but no inspection equipment like that has been developed
Heat. The light source is up to 110W and desired to go to 250W. The mirrors absorb about 30% of energy so they will get really hot. The mirrors are made of silicon molybdenum alternating layers but they have different coefficients of expansion and delaminate around 150C. Also, the mask is early in the light path and absorbs a lot of energy but must not distort or it will cause printing errors
Mask blanks are not defect free. Before adding the silicon molybdenum layers the defects are too small to see with visible light, and after they are get bigger as the mirror is built up. By the time they are visible it is too late to do anything about it. Currently no good way to fix a defect on the mask blank before patterning

If all this gets fixed and EUV is commercially viable then we should get back on track for the 40% node to node reduction in cost, which is basically an increase in node to node cost per wafer of around 20% combined with a doubling of the number of transistors per area.

June 23, 2015

Sonics’ New NoC

Sonics’ New NoC
by Paul McLellan on 06-23-2015 at 7:00 am
Categories: IP, Sonics

Today Sonics announced the latest version of their network-on-chip (NoC) technology, SonicsGN-3.0. As with any new release there are lots of improvements that are of interest mainly to existing users, but the big area with increased capability is the expanded interleaved memory technology (IMT). This was first introduced in SonicsSX in 2008 and has been in wide customer use ever since.

SoCs often communicate through external DRAM memory. But bandwidth requirements tend to go up faster than DRAM performance, and so the solution to this is to use more pins and wider memories. But with modern memory technologies such as DDR3/4 the access is burst oriented and it is really only efficient to use an 8-word burst. But that might deliver 256 bytes of which only a few are useful, while the next access has to wait for its own burst. The solution is to interleave the memory, instead of having 4 banks have 2 banks of 2. But then the challenge then is to make sure that memory access is balanced so that both banks get used heavily. If access is mostly to the first bank then that will become a bottleneck and bandwidth to the second bank goes to waste.

In a PC or Mac this is fairly straightforward to arrange, memory alternates between the two banks. That’s why, if you upgrade your memory, the DIMMs come in pairs. Alternating blocks of 64 bytes are stored in first one bank and then the other. Since most data-structures that the microprocessor is manipulating are larger than this, typically activity to the two banks will statistically get balanced between the two banks. However, this doesn’t work for memories that are being used, say, by the video subsystem on an SoC.

As Drew Wingard, the CTO of Sonics, points out:SoC designers were early in the move to multi-channel memory architectures. Use of multi-channel DRAMs and memory sub-systems is now pervasive in SoC designs, for example, in mobile applications where maximizing memory throughput takes precedence over increasing memory capacity.

In SoC designs with multi-channel DRAM subsystems, the processor speed and the total number of processors has grown to the point that the memory bandwidth bottleneck is the biggest problem. The purpose of using multi-channel memory is to exploit parallel access to memory, while avoiding bandwidth loss due to wide DRAM data buses. By breaking data into smaller word sizes and interleaving the transactions across multiple channels, IMT enables designers to improve concurrency and overall throughput by up to 20 percent using the same external DRAMs.

But to be manageable, this needs to happen transparently to the software address space view of the world (just as in your laptop you didn’t need to know about the interleaving to write code). The traffic needs to be split for delivery to the correct channel. Doing it in the memory controller causes a bottleneck at the arbiter and doesn’t really scale past two channels. IMT is a full distributed architecture which scales well. Throughput is maximized since the network automatically overlaps channel access. But by using IMT to isolate the channels from the IP cores (including processors) it is transparent to software and other hardware.

Another related concurrency management problem is ordering of requests that may be simultaneously outstanding to multiple targets, including multi-channel memories. SGN’s flexible reordering buffer architecture enables single initiator agents to have transactions outstanding to an arbitrary collection of targets, including memory channels, while respecting the protocol-defined ordering.

The other area for a major upgrade are improved links with physical design. Modern SoCs are often so big and so fast that a signal cannot get across the chip in a single clock cycle requiring registers to be inserted for retiming. Obviously these registers need to be physically spread across the chip, it is no good putting all the re-timing registers right by the receiver, for example. But with multiple power and clock domains a register cannot just be dropped down at an arbitrary location. SGN 3.0 includes new, user-controlled hierarchical partitioning and re-timing stage insertion capabilities that give designers control of which domains are associated with each re-timing stage so that they can match the floorplan. Using these features, designers can better structure their SoC designs and optimize RTL netlist generation for physical layout, which results in fewer iterations in the back-end design flow.

The Sonics press release page with full details is here.

June 22, 2015

3 Projections About Nokia’s Smartphone Reboot

3 Projections About Nokia’s Smartphone Reboot
by Majeed Ahmad on 06-22-2015 at 8:00 pm
Categories: Mobile

I have written a book on Nokia’s smartphone problem. The name of the book is Nokia’s Smartphone Problem: The End of an Icon? and it chronicles the Finnish company’s journey from a mobile handset maestro to a smartphone also-ran.

Nokia’s smartphone story began with the launch of the Communicator 900—arguably the first commercial smartphone—at the CeBIT fair in 1996. And it came to a sad end in September 2013 when Microsoft announced to buy Nokia’s mobile phone business for $7.2 billion.

An account of Nokia’s past and present situations

Here are three projections based on the chronicle of Nokia’s first smartphone play that spans from 1996 to 2013.

Leaner Business Model

The fact that Nokia is back in the smartphone game is hardly a surprise. The mobile handset is in its DNA, and the Finnish firm can’t keep away from it for long. However, more important is the fact that a far more cautious Nokia will play it safe this time around and won’t drain its resources by trying to establish full-fledged smartphone operations. Instead, Nokia will return to the smartphone market in a gradual and calibrated manner.

Nokia, probably taking cues from China’s Xiaomi, the third largest smartphone maker, will try to create an innovative business model for its smartphone market reentry. The Finnish company will most likely design the handset and then license the design and Nokia brand name to its partner who will carry out the phone manufacturing, distribution, marketing and sale.

Nokia N1 tablet provides cues on the firm’s future smartphone roadmap

Nokia demonstrated this model with its N1 tablet last year. Foxconn acquired the license for the tablet’s manufacturing, distribution, sale and after-sale support. The licensing model is similar to the approach that photography pioneer Kodak has taken after the bankruptcy.

It’s pretty ironic that the book Nokia’s Smartphone Problem has found some analogies between Kodak and Nokia. Kodak’s internal teams argued for the shift toward digital photography that the top guys ignored. Similarly, back in 2000s, Nokia’s senior management didn’t heed engineers outcry for Internet-centric, touchscreen-based app phones. A leaner Nokia seems to have learned the lesson and is moving carefully in the cut-throat smartphone business.

Continued Focus on LTE Networks

The new Nokia will remain focused on its core business of wireless infrastructure for 4G networks. Inevitably, the company sees its future in the LTE-centric mobile infrastructure business. The mega acquisition Alcatel-Lucent is a testament of that shift.

The new Nokia is led by the infrastructure man Rajeev Suri

However, the Finland–based firm still boasts valuable resources and intellectual property related to the smartphone technology. So it’s not in Nokia’s larger interest to put all eggs in one basket: mobile networks. It’s worthwhile to note that Nokia seems open for selling its HERE location business at a good price.

Moreover, mobile business with both network and terminal units is still seen as a panacea in the wireless telecom world. The two businesses have a natural synergy. It’s just that consumer-focused mobile phone business will merit a lower priority for Nokia than engineering-heavy business-to-business focus of LTE-based mobile networks equipment.

Choice of Mobile Platform

It’s most likely going to be Android. The book Nokia’s Smartphone Problem narrates the story of how Nokia secretly began to work on an Android fork in 2012, and the outcome was Nokia X phone launched at the Mobile World Congress (MWC) in Barcelona in February 2013. Apparently, Nokia’s mobile OS partner Microsoft didn’t like it. In the hindsight, Nokia’s advances toward Android became a factor in Microsoft’s decision to buy Nokia’s mobile business later that year.

Nokia’s Android phones launched in 2013

The fact that Nokia has based its N1 tablet on Android mobile operating system further reinforces this premise. There are some industry watchers who point to Jolla’s Sailfish operating system, which is a MeeGo progeny. MeeGo was the mobile operating system that Nokia co-developed with Intel as an alternative to hopelessly buggy Symbian platform.

But Nokia’s liaison with Jolla’s Sailfish platform is unlikely because the new Nokia won’t take an unnecessary risk and will go with the flow. And the flow is apparently with Android.