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Predicting Lifetime of Analog ICs

Predicting Lifetime of Analog ICs
by Pawan Fangaria on 06-22-2015 at 12:30 pm
Categories: EDA, Siemens EDA

With the increase of transistors per unit area, high density interconnects and manufacturing variability at lower nodes, the electronic devices have become more vulnerable to failures. The devices that operate under extreme conditions such as automotive devices that operate at high temperatures need to be robust enough to sustain through their lifetimes. Automotive devices typically have longer lifetimes which can last for ten or more years. There can be several factors that can degrade the reliability of a device, thus affecting its lifetime. The major reliability degradation factors include NBTI (Negative Bias Thermal Instability), HCI (Host Carrier Injection), and TDDB (Time Dependent Dielectric Breakdown). How to predict the life of an IC amidst such degradation effects?

The effects such as BTI and HCI have to be modeled and simulated. For analog and RF circuits, advanced analog and mixed-signal simulators are used which need to simulate the circuit efficiently and provide accurate results including statistical aging analysis. The reliability and aging analysis must be done early in the design cycle to avoid product recall later which may incur significant loss to the company.

Mentor Graphicshas a very effective and efficient verification flow for reliability which uses their Eldo circuit simulator. It compares the behavior of a fresh circuit just out of fab against the behavior of the same circuit aged after N years of operation under arbitrary periodic conditions. The lifetime of the fresh circuit can be predicted from the comparison of results.

Eldo uses a model which computes instantaneous stress of transistors subject to a given bias and temperature. The stress for each device is computed and integrated during normal simulation. The accumulated stress after Y years is computed by linear extrapolation. Eldo uses another set of equations which model the way ‘fresh’ model parameters are modified into ‘aged’ ones by this accumulated stress. A new ‘aged’ simulation is run using these updated model parameters. This flow can be performed, either quickly in 2 steps or in N steps. The N-step flow can provide more accurate results, however it will be slower by N times.

The aging by nature is a statistical process. Two identical devices can have slightly different threshold voltages, drive currents, and leakage currents. They also can have different aging profiles. Even if the bias conditions are identical, they do not age the same way. The required measurements are complicated, lengthy and costly. Eldo UDRM (User Defined Reliability Model) extensions support Monte Carlo simulation on aging parameters; supported models include BSIM3/4SOI, PSP, HiSIM etc.

The aging sensitivity analysis provides insight about which aging device is important and has most impact on outputs. A significantly degraded device may have little impact on circuit performance whereas a little degraded device may have significant impact on output performance. The reliability analysis with Harmonic Balance Steady-State is supported for RF circuits.

Eldo UDRM flow provides a robust and flexible solution for reliability analysis of ICs. It supports customizable aging models in Spice and Verilog-A languages. The reliability simulation offers encryption mechanisms to protect intellectual property of equations and models of degradation effects. The advanced model definitions allow designers to account for these degradation effects much early in the design.

This methodology was presented in 52[SUP]nd[/SUP] DAC at Mentor booth by Ahmed Eisawy, Eldo Product Marketing Manager at Mentor. Also, there is a case study done by Vitessewhich is posted on Mentor website; Joint Design – Reliability flows and advanced models address IC reliability issues. This case study also shows how reliability issues can be debugged by visualizing instantaneous stress pulses as experienced by the device.

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

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SEMulator3D on Silicon Cloud International

SEMulator3D on Silicon Cloud International
by Paul McLellan on 06-22-2015 at 7:00 am
Categories: Coventor, EDA

Almost exactly a year ago I wrote about Silicon Cloud International (SCI). Their mission is to help smaller countries that have targeted semiconductor design as a way to move up the technology ladder from low-cost manufacturing. Last year everything was in the future but SCI now have their first two centers up and running. The first, a pilot program, was announced at the end of last year and is in UAE. The second, announced a couple of months ago is in Singapore (which is also SCI’s home).

See also National Semiconductor Education in the Cloud

In EDA the pioneer in using the cloud was probably Nimbic (now part of Mentor). If the cloud is going to work anywhere in EDA then these types of applications that require hugely scalable compute resources, don’t involve gigabyte files, and don’t contain the entire company crown jewels are likely to be the first places. I just wrote a blog last week on the IBM announcement of its library characterization tools in the cloud, with some skepticism about doing an entire design in the cloud.

See also IBM Design Tools in the Cloud: Big News or Old News?

Another area that seems a good match is virtual fabrication whereby a full 3D model of a part of a process is built up from the process recipe and a small amount of layout. This can then be verified. The process is computationally expensive and a lot of verification can be run in parallel, so the scalable nature of the cloud is idea.

At DAC on the SCI booth I watched a demo of Coventor’s SEMulator3D Virtual Fabrication platform with broad parallel computing offered by Silicon Cloud. Coventor is calling this 3D Design-Technology Checking (3D-DTC).

SEMulator3D enables process predictive virtual fabrication of any design in any process flow. I’ve blogged about this before, most recently about vertical flash memory. Using SEMulator3D’s Automation features, users can easily virtual fabricate hundreds or thousands of models representing process or design variations, and then check them in true 3D space for critical yield criteria. The broad computational resource added by Silicon Cloud allows this to be done across a huge process space in a very short time. This especially important for companies that do not have extensive compute farms available (or “private cloud” seems to be the trendy word for a compute farm these days).

See also Vertical NAND Flash


So what was the demo? Just a single design construct is analyzed: a pair of semi-isolated M2 lines, connected to dense M1 wiring with a staggered V1 configuration. This design is virtually fabricated in a 10nm-like BEOL technology, complete with Trench-First SADP (self-aligned double patterning) Mx patterning, LELE (litho-etch-litho-etch double patterning) Vx patterning and advanced metallization. By varying lithography, deposition and etch processes, it is possible to see where this design construct is subject to yield-limiting mechanisms. The demo only used a small portion of the cloud. There were lots of other demos too, all of which needed their share, but the demo was able to run 89 virtual design of experiments wafers through the full process flow and a suite of 3D-DTC rules in just over an hour. If the whole cloud had been made available it would have taken just 11 minutes. It provided some tremendously valuable information about the Design-Technology sensitivities of this structure, such as the points of Minimum Insulator failure (a key reliability metric) and Minimum Metallization failures (a key resistance and reliability metric)… despite being 2D DRC clean!

But the real comparison is to the old way of doing things. That would have required the fabrication of about 200 wafers, at a cost measured in millions dollars, and a delay measured in month. I’ll take the 11 minute option.

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GlobalFoundries IBM Deal to Close July 1st!

GlobalFoundries IBM Deal to Close July 1st!
by Daniel Nenni on 06-21-2015 at 5:00 am
Categories: Foundries, GlobalFoundries

Probably one of the most awaited semiconductor events is coming next week if the Poughkeepsie Journal is correct, which from what I’m told by my Albany friends, they are. The official announcement was made last October using the slide deck which can be found HERE. It was originally thought that the approval process would take a year so someone must have really pushed this one through.

ARMONK, N.Y., and SANTA CLARA, Calif., October 20, 2014: IBM (NYSE: IBM) and GLOBALFOUNDRIES today announced that they have signed a Definitive Agreement under which GLOBALFOUNDRIES plans to acquire IBM’s global commercial semiconductor technology business, including intellectual property, world-class technologists and technologies related to IBM Microelectronics, subject to completion of applicable regulatory reviews. GLOBALFOUNDRIES will also become IBM’s exclusive server processor semiconductor technology provider for 22 nanometer (nm), 14nm and 10nm semiconductors for the next 10 years.

Given the latest semiconductor acquisition spree this may not seem like a big deal but I think it is by far the most interesting one we will ever see. Some say this is an exit strategy with Samsung being the ultimate suitor. Others say it is a Greek tragedy in the making. Time will tell but personally I think it is a brilliant move in what will prove to be one of the more interesting chess games our industry has ever seen, absolutely.

Paul McLellan and I spent quite a bit of time on this from both the GF and IBM side of things. Here is a quick summary of the benefits we see for this acquisition:

  • The IBM ASIC business is exactly what GF needed to get into the system houses
  • The IBM IP portfolio is exactly what GF needed to differentiate in the fabless semiconductor ecosystem
  • The IBM talent (5,000+ employees) is exactly what GF needed to create an East Coast semiconductor dynasty
  • The IBM patents (10,000+) is exactly what GF needed to secure their semiconductor legacy
  • The IBM acquisition is exactly what GF needed to secure a nice investor exit (IPO)
  • Reinforces GlobalFoundries’ long-term commitment to manufacturing and technology leadership
  • Provides R&D expertise to give a path to 10nm and beyond
  • Expands segment growth in RF and ASIC
  • Becomes IBM’s sole source foundry partner
  • Gives them strategic relationships with top OEM industry suppliers

“This acquisition solidifies GLOBALFOUNDRIES’ leadership position in semiconductor technology development and manufacturing,” said Dr. Sanjay Jha, CEO, GLOBALFOUNDRIES. “We can now offer our customers a broader range of differentiated leading-edge 3D transistor and RF technologies, and we will also improve our design ecosystem to accelerate time-to-revenue for our customers. This acquisition further strengthens advanced manufacturing in the United States, and builds on established relationships in New York and Vermont.”

“The Agreement expands our longstanding collaboration, which began when GLOBALFOUNDRIES was created in 2009, and reflects our confidence in GLOBALFOUNDRIES’ capability,” said IBM Senior Vice President & Director of Research Dr. John E. Kelly III. “This acquisition enables IBM to focus on fundamental semiconductor and material science research, development capabilities and expertise in high-value systems, with GLOBALFOUNDRIES’ leadership in advanced technology manufacturing at scale and commitment to delivering future semiconductor technologies. We are grateful for the leadership and investments by the states of New York and Vermont in supporting the semiconductor industry.”

IBM, GlobalFoundries deal to close July 1; new look for tech

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Unlock the Key to Ultra-Low Power Design

Unlock the Key to Ultra-Low Power Design
by Tom Simon on 06-20-2015 at 7:00 am
Categories: EDA, Events, MunEDA

We have been hearing about low power for a long time. Fortunately, low power chip operation has come about through a large number of innovations. Key among these is clock gating, frequency and voltage scaling, managing leakage with lower threshold voltage, HKMG, and many other techniques. But we are entering the age of ultra low power and it brings with it a completely new level of expectations, and design complexity.

Ultra low power is needed to run RFID, implantable devices, remote sensing platforms, or wearable tech. It needs to run with no built in power source, as is the case for RFID, or with very limited power, such as with small lithium polymer batteries charged by solar energy. The needs of ultra low power have pushed design methodology into new areas, like sub threshold CMOS analog design. With this shift in design comes the need for new tools to solve difficult design problems.

While digital designers are looking to drive their transistors into strong inversion rapidly to quickly move through the highly resistive transition that draws power and dissipates thermal energy, analog designers are interested in weak and moderate inversion modes so they can save power and achieve high gain – gm/Id. Threshold voltages have dropped to save power across the board, and analog designers are looking to operate their circuits at sub threshold voltages for a variety of reasons.

Circuits that operate in the moderate inversion region are very conducive to analog design. In fact gain values can exceed those of BJT’s, and thermal noise can be lower because of less carrier scattering. But care needs to be given to evaluate the effects of variation and the properly optimize the circuit to ensure operation in the region that was intended.

Designers end up with a complex multi-variable, multi-objective design problem that has many dimensions and tricky sensitivities. The old days of picking gate dimensions with a spreadsheet and running a few simulations to verify and fine tune the results are long gone. In fact simulation needs to move from being a verification tool to a design tool.

This is exactly what Munich based MunEDA was showing at #52DAC recently in San Francisco. I met with Michael Pronath VP of Products and Solutions at MunEDA to see a demo and discuss their solutions for optimizing analog circuits designed for ultra-low power. He used theoir WiCKeD suite to run through the flow on a Miller OpAmp operating at 1.2V. The design targets were: Phase Margin > 70, GBW = 1MHz and of course absolute minimum power. He used WiCKeD to optimize all the transistor W,L values, set the bias current, etc.

While maintaining all the design objectives Michael showed me how the design can be optimized with their Deterministic Nominal Optimization DNO to achieve the lowest power with all the transistors operating in moderate inversion. They can even add in process and thermal variation to be sure that the circuit is well behaved for high yield and reliability.

The results were impressive and showed an improvement over the classical and gm/Id methodology. Certainly gm/Id is a good method for evaluating transistor circuits in moderate inversion, but WiCKeD’s numerical sizing approach is good at optimizing yield and reliability, which are nearly impossible with other approaches with capacity constraints. WiCKeD works comfortably with:

  • >100 specifications and constraints handled simultaneously
  • >200 design variables
  • >2000 MOS Post-layout effects and parasitics supported
  • Multiple test benches, goals, and corners are considered

The user interface also allows designers to go through the flow by combining step visually to arrive at a set of alternatives to pick the best results.


MunEDAhas quietly been collecting a large majority of the top semiconductor companies in its customer list. For me seeing the software in use helped clarify the operation and advantages of their unique approach. I can see why designers would like their approach for getting the lowest possible power out of sensitive designs.

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An Universe of Formats for IP Validation

An Universe of Formats for IP Validation
by Pawan Fangaria on 06-19-2015 at 4:30 pm
Categories: EDA, Fractal Technologies

Although I knew about Crossfire’s capabilities for signing off quality of an IP before its integration into an SoC, there was much more to learn about this tool when I visited Fractal Technologies booth during this DAC. The complexity handled by this tool to qualify any type of IP for its integration into an SoC can be imagined by the number of different formats and databases the tool supports. Crossfire’s unique common data model allows different databases and formats to be cross-checked for completeness and correctness against a golden reference format or against a previous release.

There are formats to support different levels of descriptions for a design at the chip/IP, cell, transistor, or layout levels. Also there are specialized formats to describe parasitic, power, timing, test, parameter variation, and other aspects of circuits at the cell or macro levels. As the technology progresses through lower process nodes, new physical effects come into existence and they need to be modeled in many different ways. It’s not simple for designs to migrate to newer technology nodes without provisioning for newer physical effects through newer, perhaps complex models. The result is ever increasing number of design formats including but not limited to verification and power and timing specifications. Also, there are different databases from major vendors in the semiconductor industry, e.g. OpenAccess and Milky Way. Imagine this volume and diversity of data that has to be accommodated and managed in a common system like that of Crossfire. Provision to accommodate all types of formats and databases is imperative because an SoC can have IPs from multiple vendors in multiple different formats. Crossfire has a robust process of including any new format into its data model.

Fractal Technologiescommon data model for Crossfire is extensible to easily accommodate any new format. Crossfire’s first phase is to check completeness of the format for all object types including cells, pins, nets, timing arcs, and also power domains. The Crossfire compares any item that has been parsed with the equivalent item from a reference. Once a new format is proven complete, it means that its generation is well integrated into the automated characterization flow. So, any new cell or process corner added into the IP will be correctly and automatically included into the new format as well. At the SoC level, after Completeness Checks for all formats of an IP, the IP becomes ready for integration.

In the second phase, the intrinsic quality of the format is checked where characterization data such as timing and power values are checked for their correctness according to their physical aspect. Crossfire provides a rich set of quality assurance checks to dive deeper into the models provided by different formats such as trend-checks for timing and power values across process corners. For example, it can take various process corners described in the .lib files and check whether delays will indeed increase with rising substrate temperature or decrease with increasing supply voltage. The Intrinsic Quality Checks of IPs are done for final verification of the SoC before tape-out.

Recently some very important formats were added into Crossfire –

Apache Power Library (APL): This format models all power aspects of a particular cell or IP and is an important input to ANSYS’RedHawk for IR drop and reliability verification. Besides completeness check, Crossfire also checks trends for APL such as increasing currents at increasing output loads.

Unified Power Format (UPF): This is another power format promoted by Synopsys. The purpose of UPF is to describe power domains, voltages and related pins for the entire design. The power domains have to be physically separated networks in the IP design. Crossfire verifies this requirement by cross-checking UPF against SPICE netlist.

Core Test Language (CTL): This is an IEEE standard for describing the Design for Test (DFT) interfaces of a particular IP. Crossfire checks consistent naming of pins for test-control and scan-chains and their proper functionality.

Advanced On Chip Variability (AOCVM): This is an extension to Synopsys’ Liberty and is aimed at modeling the variation of cell-delays during manufacturing at lower process nodes like 14nm and 10nm. Crossfire checks for completeness and consistency of AOCVM against the available Liberty models for timing and power. It also checks for trends such as reduced variability of delays with increasing logic depth.

The Crossfire is versatile enough to include documentation formats as well. Through a PDF reader, the end-users also can parse their own proprietary datasheets into the Crossfire common data model and check the documentation for completeness. Currently, Crossfire supports over 40 different formats and databases and is able to add a new format within a few weeks time. Crossfire also provides a flexible API for users to code their proprietary checks on their IP, and those can be added on the GUI as well.

Thus Crossfire offers a very powerful environment to check IPs before their integration into an SoC and also to verify quality before the SoC tape-out. There is also a whitepaper HERE to read for more information.

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

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IBM Design Tools in the Cloud: Big News or Old News?

IBM Design Tools in the Cloud: Big News or Old News?
by Paul McLellan on 06-19-2015 at 7:00 am
Categories: EDA

One announcement that I missed coming up to the Design Automation Conference last week was that SiCAD is hosting a portfolio of IBM’s design automation tools in the cloud. Supposedly these are priced half the cost of similar capability from Cadence, Synopsys and Mentor. So should the big three be worried? Is this an earth-shattering event?

The press release opens:IBM today announced that it is launching IBM High Performance Services for Electronic Design Automation (EDA), the electronic industry’s first enterprise-class, secure cloud service, which provides on-demand access to electronic design tools, in partnership with SiCAD, Inc., a Silicon Design Platform provider, with expertise in EDA, design flows, networking, security, platform development, and cloud technologies.

So the 50,000 foot view of what is being offered is:

  • Access to IBM-patented EDA tools
  • Bundled with Platform LSF on IBM Softlayer
  • Charged by consumption based on pay-as-you-go model
  • Offered through SiCAD’s Virtual Design Center Platform

IBM has always had some of the most advanced design tools, and they have relied correspondingly little on 3rd party tools. Their own place and route, timing engine, synthesis engine, analysis and so on. It is not quite clear exactly which tools will be available in the end, they say that this initial announcement is just a start, but certainly their library characterization tool, logic verification tool and its own SPICE simulator.

I see four big problems.

The first problem is the one that we had at Compass Design Automation, when we spun it out from VLSI Technology. Despite the fact that our tools were supposedly technology independent, the reality was that they were much more intertwined with our own libraries and with VLSI’s process technology. VLSI used external foundries too, and other customers such as LG in Korea used our whole portfolio in their own fab with a completely different process. Nonetheless, lots of things break when you see things that you have never seen before. For example, IBM does all its server design on SOI, which it manufactures in its Fishkill fab. But nobody else does high performance designs on IBM’s process. That may change one GlobalFoundries gets the fab and can make the foundry available to others.

The second problem is that companies have been very reluctant to use cloud-based solutions for semiconductor design, except in niche areas like Nimbic. There are two reasons for this. One is the perceived “putting the crown jewels on the internet” effect. If Target can lose all its customer data, and the OPM can lose all the federal employee data, including security clearance data, and Snowden can walk off with half the NSA’s secrets, then this is not seen as a trivial risk. I’m sure the Chinese military would love to have Intel’s latest processor mask data, or TSMC’s 10nm process recipes, or Qualcomm’s latest modem. That’s why you don’t find those things out in the cloud.

Another cloud issue is that IC designs are large. So moving them in and out of the cloud is time consuming, and unless all the tools required are there (they are not) then this is a necessity. For some applications, such as library characterization which can involve tens of thousands of SPICE runs, I can see the attraction of the cloud. Relatively small amounts of data, large computational load, almost unlimited parallelism, LSF to handle it all.

The third problem is that this is the second (or maybe third) time that IBM has tried to commercialize its design tools. Remember BooleDozer and Einstimer. They might even have been the best synthesis tool and the best timing engine (Ambit’s timing engine was written by the same person, and it was clearly the best engine of its era). But IBM were not successful in the market. They tried to sell through distribution, so that probably contributed to the lack of success, but was not on its own not fatal.


The fourth problem is the usage-based pricing. If the price is low enough to be attractive to large companies that means that running hundreds of copies of a tool 24-hours a day needs to be cheaper than buying permanent (or time-based) licenses. But if the price is set this low then there is almost no revenue from the small and medium sized companies that is the explicit focus of the announcement. If, on the other hand, the price is set high enough to get interesting revenue from the medium sized companies it will not be of interest to the larger ones. There are probably ways to solve this but it has been one of the problems whenever EDA companies have toyed with usage-based pricing. The EDA company is only interested if the revenue is higher, and the customer is only interested if it is lower. At least in this case, since IBM does not have existing business to protect, that dynamic might not matter.

We will have to wait and see what happens as more tools become available and whether:With the cloud service, clients no longer need to purchase EDA tool licenses, new hardware, data center infrastructure or staff to manage on-premise environments. IBM High Performance Service for EDA provides high performance tools, security and overall improved price performance offering customers of all sizes more affordable access to EDA tools and decreased cost of designs.

SiCAD’s website, including the press release is here. An “end of EDA as we know it” article worth reading is here.

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Solido Has Perfected the Emerging EDA Company Business Model!

Solido Has Perfected the Emerging EDA Company Business Model!
by Daniel Nenni on 06-18-2015 at 7:00 pm
Categories: EDA, Solido

Last year at #51DAC we gave away more than a thousand printed versions of our book “Fabless: The Transformation of the Semiconductor industry.” This year we gave away pens with a light and stylus. My friends at Solido Design gave away 600 pens in their booth and we gave away another 400 at our DAC reception on Wednesday night. Solido was actually very clever about it. They turned on the lights and just left them in the trays on the counter. People came to them like moths to a flame… Even John Cooley stopped by to investigate! NO PEN FOR YOU! 😉

Speaking of clever, Solido is one of the more interesting companies I have worked with. They have perfected the emerging EDA company business model, absolutely. Solido CEO Amit Gupta is very approachable and I always enjoy talking to him. Here is an update from Amit and thank you again to the Solido booth staff for giving away our pens. It was greatly appreciated!

Q: What does Solido do?
We are the world-leading provider of variation-aware custom IC design software. Our customers are using our product, called Solido Variation Designer, to dramatically boost SPICE simulator performance by reducing the number of simulations and increasing design coverage for PVT, 3-sigma Monte Carlo, high-sigma Monte Carlo, hierarchical Monte Carlo and variation debug.

Q: How do your customers use your product?
We have 3 segments of users: memory, standard cell and analog/RF/custom digital designers. Our memory customers are using Variation Designer for full chip memory and cell level statistical verification. Standard Cell designers use our product for statistical verification and sizing of cell libraries. And our analog/RF and custom digital customers use Variation Designer for statistical & PVT verification and debug. Overall, users are getting improved design coverage in way fewer simulations than brute force.

Q: What industry trends are you seeing that impact your business?
We are seeing 2 big trends in the custom IC design space – continued move to smaller nodes and ultra-low power design at mature nodes. The move to smaller nodes is increasing variation. 28nm, FinFET and FD-SOI devices all have an increasing amount of variation impacting designs. Also, ultra-low power design at the more mature nodes, for applications like IoT wearables, is having larger variation impact due to lower supply voltage. Both of these trends have resulted in much more variation-aware custom IC design being done in the industry.

Q: What are the benefits of your customers using your product?
You can no longer cut corners when doing your SPICE verification. Increased variation causes designers to overdesign (poor power, performance and area) due to unnecessary over-margining, or underdesign resulting in poor yield. Our customers are using Variation Designer to see the impact of variation and eliminate unnecessary over and under design, so they get much better power, performance, area and yield.

Q: How is your business doing?
Our business is growing very quickly. We had 60% revenue growth last year, and 90% revenue growth in the first half of this year with increasing profits. We now have over 25 customers, including most of the top semiconductor companies, and over 1,000 users worldwide using our software regularly. We are also hiring – we have 10 software developer and applications engineering positions to fill immediately.

Q: What’s new at DAC this year?
We are pleased to be an invited presenter at the TSMC Open Innovation Platform Theater to showcase the Solido – TSMC integrated solution for our mutual customers. We also hosted a panel where engineers from Applied Micro Circuits, Cypress Semiconductor and Microsemi discussed their experiences using Variation Designer in their design flows and how they transitioned from legacy tools over to Solido.

In our demo suites, we are previewing our next major release – Solido Variation Designer 4.0. It includes Statistical PVT which delivers unprecedented accuracy and coverage across 3-sigma statistical variation and operating conditions, Hierarchical Monte Carlo which verifies full-chip memories with perfect statistical accuracy, and a suite of brand new features for memory, standard cell and analog/RF/custom digital designers.

Q: Where can our readers find more information about Solido?
They can visit our website at www.solidodesign.com for more product details and contact information. Or visit our careers site to see our job postings: http://www.solidodesign.com/page/jobs/

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Can FD-SOI Change the Rule of Game?

Can FD-SOI Change the Rule of Game?
by Pawan Fangaria on 06-18-2015 at 12:00 pm
Categories: EDA, FD-SOI, Foundries, STMicroelectronics

It appears so. Why there is so much rush towards FD-SOI in recent days? Before talking about the game, let me reflect a bit on the FD-SOI technology first. The FD-SOI at 28nm claims to be the most power-efficient and lesser cost technology compared to any other technology available at that node. There are many other advantages from a technology standpoint which we have heard over a year or two. For example, simplicity of process, no channel doping, excellent electrostatic control of the channel, and back biasing with extremely thin box. These technology aspects translate into limited short channel effect, low DIBL (Drain Induced Barrier Lowering), minimum junction capacitance and diode leakage, lowest leakage current, and excellent voltage threshold variability. The result is – the device can operate at multiple voltages and multiple frequencies. It can be used for high-performance (at 28nm at this time) as well as ULP (Ultra-Low-Power) applications.


[Courtesy ST: FD-SOI transistor structure; SRAM SER comparison]

Okay, I’m not showing the power graphs here as they are widely known for FD-SOI technology. Just see the interesting Soft Error Rate (SER) comparison bar chart obtained at ST for SRAMs. It is the minimum in case of FD-SOI and that improves reliability of devices with FD-SOI technology. Reliability, low-power, and low-cost are the key requirements for IoT applications. Also, the technology has lot of benefits for analog and high-speed designs because of lower gate capacitance and leakage current and latch-up immunity. The device also has lower noise and higher gain because of the absence of channel doping and pocket implants.

Now, let’s see how the rule of game is changing. At 28nm, there is no FinFET to compare with. The FD-SOI technology stands tall against all others with all the advantages mentioned above. Is that the only reason for the rush towards FD-SOI at this juncture? There is something more to it; the semiconductor business scenario, the economy, and the trending segments. In next couple of years IoT is supposed to be the top growing segment. Also, IoT applications do not require 16nm, 14nm, or below technology nodes. The 28nm process node seems to be ideal for IoT applications as they need low power at low cost. The 28nm process also looks good for analog ICs which will be a key requirement for the IoT market.

This is the most opportune time for foundries (ST being in the leadership position for FD-SOI), chip and IP developers, EDA vendors, and service providers to avail the opportunity provided by FD-SOI.

During 52[SUP]nd[/SUP] DAC, CEA-Letimade a big announcement about the launch of “Silicon Impulse”, a platform aimed at broadening the use of FD-SOI technology for ultra-low-power devices that are used in IoT applications and other energy-efficient equipments. The platform will offer technical expertise for developing energy-efficient solutions along with access to FD-SOI technology and manufacturing facilities. The service will include infrastructure support such as emulator and other test services along with industrial multi-project wafer (MPW) shuttles. The platform has partners from wide spectrum of semiconductor ecosystem including academia, foundry, EDA providers and chip designers. The list of partners with CEA-Leti includes CEA-List, STMicroelectronics, Dolphin Integration, CMP, Mentor Graphics, Cortus, and Presto Engineering.

The collaboration and partnership is not limited to ‘Silicon Impulse’ platform partners. There are also other partnerships happening around the world. Sankalp Semiconductoris an Indian origin company, leading in SoC chip design services and specializing in end-to-end solutions for IOs, Analog and Mixed-Signal chip designs. It has multiple design centers in India and USA. Recently, just before DAC, Sankalp announced FD-SOI services and IP partnership with ST. Sankalp has been involved in the development of many FD-SOI analog IP and high-speed PHYs for ST. Sankalp has developed significant expertise about FD-SOI technology and its usage in various applications. With FD-SOI technology, Sankalp feels confident to serve for the emerging IoT, wearable, consumer, multi-media and automotive markets.

See the press release about Sankalp and ST partnership here.

To accelerate the global footprint for FD-SOI technology based development, CEA-Leti is also hosting a workshop on June 22-23 where an expanded representation from the semiconductor community will take place. The presenters include –

  • ST, GLOBALFOUNDRIES and Samsung on FDSOI manufacturing
  • Ciena, ST and NXP on products based on FDSOI chips
  • Cadence, Synopsys, Mentor Graphics, sureCore, eSilicon and Tiempo on their offers for FDSOI in terms of IP and EDA tools

Also, there will be prominent professors from world-class universities along with Leti who will present about their research and innovations in designs with FD-SOI.

It’s exciting to see the FD-SOI ecosystem growing so fast, definitely there is merit in this technology. One may argue about 14nm FinFET technology superiority in terms of performance. However, I hear that ST will soon bring 14nm FD-SOI up to speed. So, by the time IoT market matures with 28nm FD-SOI, 14nm FD-SOI will become available for mainstream design. Does that seem like FD-SOI game?

By the way, if anyone is interested in attending the FD-SOI workshop, it is in Grenoble, France. Registration link is here.

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

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Semiconductor Equipment: the Report and the Show

Semiconductor Equipment: the Report and the Show
by Paul McLellan on 06-18-2015 at 7:00 am
Categories: ESD Alliance, Semiconductor Services

Somebody said to me recently that SEMICON West, which takes place in San Francisco July 14-16th, isn’t that big a deal since very little manufacturing goes on in the US any more. In fact 15% of manufacturing capacity is in north america (I think that actually means the US since I don’t think there are any fabs in Canada). That is more than China, almost twice as much as Europe. Of course if you put all the Asian countries together you get to about 70% of all capacity.

Looking at just new capacity, due to the presence of leading device manufacturers, North America represents a significant portion of the new equipment market. For the last two years, North America was the second largest market for semiconductor manufacturing equipment behind only Taiwan.

Last week SEMI announced he update of its World Fab Forecast report for 2015 and 2016. The report projects that semiconductor fab equipment spending (new, used, for Front End facilities) is expected to increase 11 percent (US$38.7 billion) in 2015 and another 5 percent ($40.7 billion) in 2016. Since February 2015, SEMI has made 282 updates to its detailed World Fab Forecast report, which tracks fab spending for construction and equipment, as well as capacity changes, and technology nodes transitions and product type changes by fab. You can hear more about this on Monday July 13th, the “day before SEMICON West” by attending the the SEMI/Gartner Market Symposium an update on the semiconductor supply chain market outlook. In addition to presentations from Gartner analysts, Christian Dieseldorff of SEMI will present on Trends and Outlook for Fabs and Fab Capacity and Lara Chamness will present on Semiconductor Wafer Fab Materials Market and Year-to-Date Front-End Equipment Trends.

On Tuesday there is a keynote panel at 9am, and on Wednesday a keynote on IoT, also at 9am.

  • Tuesday: Keynote Panel – Scaling the Walls of Sub‐14nm Manufacturing
    Featuring: Qualcomm, Stanford University, imec and more.

  • Wednesday: Keynote – The Internet of Things and the Next Fifty Years of Moore’s Law
    Doug Davis, Senior Vice President and General Manager, Internet of Things Group, Intel

One the exhibit floor there are two presentation areas known as TechXPOTs. There is one in the north hall of Moscone and one in the south. The presentations are included with any pass for the exhibits. Topics that will be covered include:

  • What’s Next for MEMS?
  • Automating Semiconductor Test Productivity
  • Emerging Generation Memory Technology: Update on 3DNAND, MRAM and RRAM
  • Materials Session: Contamination Control in the Sub-20nm Era
  • Subsystem and Component Suppliers at Critical Cross Roads to Deliver on Yield and Productivity
  • Equipment and Materials Opportunities for Flexible Hybrid Electronics
  • Packaging Session: Auto Utopia — Gearing up Semiconductor to Turn Dreams to Reality
  • The Evolution of the New 200mm Fab for the Internet of Everything
  • Monetizing the IoT: Opportunities and Challenges for the Semiconductor Sector
  • CMP Technical and Market Trends
  • Factory of the (Near) Future: Using Industrial IoT in Semiconductor Manufacturing Sector
  • Update on Industry Status of 450mm

There’s more too:

  • Freescale IoT Truck
  • Fuel Cell Car
  • Innovation Village
  • Pavilions: China, Europe, Malaysia, Silicon Saxony

Details on the World Fab Forecast are here.
The website for SEMICON West, including links for registration, is here.

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The Best Conversations You Missed at #52DAC!

The Best Conversations You Missed at #52DAC!
by Daniel Nenni on 06-17-2015 at 7:00 pm
Categories: Cadence, EDA, Siemens EDA, Synopsys

The CEO Fireside Chats were my very favorite part of #52DAC. Dr. Walden Rhines, Lip-Bu Tan, and Dr. Aart de Geus are heroes of the EDA industry, absolutely. I saw all three Fireside Chats and the one word that I’m left with is INSPIRED!
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