SemiWiki – Page 724 – The Open Forum for Semiconductor Professionals

August 7, 2015

Is 7nm Coming to the TSMC OIP Ecosystem Forum?

Is 7nm Coming to the TSMC OIP Ecosystem Forum?
by Daniel Nenni on 08-07-2015 at 4:00 pm
Categories: FinFET, Foundries, TSMC

This is the 5[SUP]th[/SUP] TSMC Open Innovation Platform Ecosystem Forum and it is not to be missed. Please note that the location has moved from the San Jose Convention Center to the Santa Clara Convention Center which is literally right across the street from the new Levi’s Stadium. If you haven’t been to the new stadium you really should take a tour and stop by the SF 49ers Museum. Public tours run between 10am and 6pm and yes they have WiFi.

The new location will increase attendance significantly this year (my opinion) so you had better register now because space is limited. In addition to networking with 1,000+ semiconductor professionals you will get to hear from TSMC’s executives on what is new and improved for the different processes and surrounding ecosystem: 28nm, 16nm, 10nm, and I would bet 7nm will also be mentioned if not formally announced.

You may also get to hear from one of TSMC’s leading customers. At the TSMC Technology Symposium last April the guest speaker was Avago CEO Hock Tan. Since then Hock has engineered the acquisition of Broadcom for $37B. Previously he acquired LSI Logic for $6.6B so I would definitely like to hear a semiconductor industry update from an executive of his caliber, absolutely.

The event starts at 9am on Thursday, September 17[SUP]th[/SUP]. After the ninety minute executive presentations there are 30 technical papers divided into three tracks for EDA, IP, and Services. The paper abstracts are now up on the OIP website. And of course there will be a vendor expo with 80 vendors bearing gifts and the latest news on design enablement. Rumor has it Solido Design will be giving away the elite SemiWiki.com stylus penlights so you may want to go there first.

Click HEREfor the event overview, agenda and registration

|-
| 11:30 – 12:00
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| align=”center” valign=”top” | Exploring Custom Metal Stacks for Advanced Node IC Design Using Early StarRC Extraction
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| align=”center” valign=”top” | Synopsys
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| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| align=”center” valign=”top” | Migrating ARM Cortex-A53 designs From 28HPM to 28HPC+ – Getting Two Designs Out of a Single Implementation
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| align=”center” valign=”top” | ARM
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|-
| 12:00 – 13:00
| colspan=”3″ align=”center” valign=”top” | Lunch
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| 13:00 – 13:30
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| align=”center” valign=”top” | Thermal and Color-aware Reliability Verification for Sub-16nm FinFET Designs
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| align=”center” valign=”top” | Ansys Inc.
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| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| align=”center” valign=”top” | High-Speed SerDes Design in Advanced TSMC Process: Architecture Implementation
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| align=”center” valign=”top” | GUC
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|-
| 13:30 – 14:00
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| align=”center” valign=”top” | Custom Device Array- Place, Route, Simulate Prior to Layout
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| align=”center” valign=”top” | Cadence
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|-
| 14:00 – 14:30
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| align=”center” valign=”top” | Hierarchical Fill Methodology for Advanced Nodes
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| align=”center” valign=”top” | Mentor Graphics
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|-
| 14:30 – 15:00
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| align=”center” valign=”top” | IC Packaging centric approach to design fanout-out WLCSP (InFO) designs
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| align=”center” valign=”top” | Cadence
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| align=”center” valign=”top” | Rapid Implementation of IoT end-point sensor devices using ARM and TSMC IP
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| align=”center” valign=”top” | ARM
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|-
| 15:00 – 15:30
| colspan=”3″ align=”center” | Coffee Break
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| 15:30 – 16:00
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| align=”center” valign=”top” | 2-5X productivity improvement in converging to a DRC-clean cell design—Qualcomm’s experience with Calibre RealTime
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| align=”center” valign=”top” | Mentor Graphics
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|-
| 16:00 – 16:30
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| align=”center” valign=”top” | Synopsys’ PrimeTime POCV Improve Productivity and PPA in FinFET Designs – NVIDIA Experience

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| align=”center” valign=”top” | Synopsys
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|-
| 16:30 – 17:00
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| align=”center” valign=”top” | TSMC Advanced Node EMIR analysis
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| align=”center” valign=”top” | Cadence
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|-
| 17:00 – 17:30
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
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| align=”center” valign=”top” | IC Compiler II key in accelerating time-to-market for HiSilicon’s next-generation 10-nm advanced SoC’s
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| align=”center” valign=”top” | Synopsys
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|-
| 17:30– 18:30
| colspan=”3″ align=”center” | Social Hour
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The TSMC OIP Ecosystem Forum brings together TSMC’s design ecosystem companies and our customers to share real case solutions to today’s design challenges. Success stories that illustrate best practices in TSMC’s design ecosystem will highlight the event.

More than 90% of last year’s attendees said that “the forum helped them better understand TSMC’s Open Innovation Platform” and that “they found it effective to hear directly from TSMC OIP member companies.”

This year’s event will prove equally valuable as you hear directly from TSMC OIP companies about how to apply their technologies to address your design challenges!

This year, the forum is a day-long conference kicking-off withtrend-setting addresses and announcements from TSMC and premier IC design company executives.

The technical sessions are dedicated to 30 selected technical papers from TSMC’s EDA, IP, Design Center Alliance and Value Chain Aggregator member companies, and an Ecosystem Pavilion feature up to 80 member companies showcasing their products and services.

Click HERE for the event overview, agenda and registration

August 7, 2015March 22, 2022

ClioSoft SOS v7.0: Faster, Smarter and Stronger

ClioSoft SOS v7.0: Faster, Smarter and Stronger
by Majeed Ahmad on 08-07-2015 at 12:00 pm
Categories: Cliosoft, EDA

System-on-chips (SoCs) are now everywhere, whether they are processors, microcontrollers or FPGAs, and what matters more these days is how quickly these large and complex chips adapt to the specific needs of the OEM application or the “system.” So time-to-market window is shrinking, and conversely, the use of IP tools is increasing in order to efficiently manage the rising complexity and time-to-market requirements of SoC designs.

One of these IP tools is ClioSoft Inc.’s SOS, a design data management solution for analog, RF, digital and mixed-signal designs. The ClioSoft SOS design collaboration platform—which has an 18-year history of being tightly integrated with traditional EDA flows—allows chip engineers to use tools from different vendors to design digital, analog and RF design modules.

Now ClioSoft has released version 7 of its SOS design collaboration tool, which it claims is faster, smarter and stronger. The SOS v7.0 is upward compatible with earlier SOS versions and provides SoC designers with all the features of previous versions of the design data management tool.

In SOS v7.0, ClioSoft has added the bandwidth spice to its multi-site architecture. That’s a significant improvement because managing progress at each design site is crucial in getting the chip to the market in time. The speed factor enhances the ability of SOS data management tool to manage design data from concept through GDSII and mitigate the possibility of design re-spins because of incorrect configurations.

SOS7 tool uses HSDT technology for bandwidth boost

ClioSoft has over 150 customers—ranging from large foundries to small design shops—that use the SOS configurable IP platform. So how does SOS v7.0 differ from previous versions? Below is the recap of the three salient features of the SOS v7.0 design data and enterprise IP management platform.

Faster Data Management

ClioSoft claims that SOS7 is up to 30 times faster than previous versions of its SoC design collaboration platform. The data management tool supplier is using hyper streaming data transport (HSDT) technology to enable faster queries and caching operations.

The use of HSDT technology allows SOS7 to ensure data compactness and thus create smaller repositories. Moreover, remote design centers can efficiently keep synch with each other and to the central repository by making use of the faster and more efficient communications links.

SOS7 provides faster access to design data at multiple sites

Smarter Data Management

Remote design centers are becoming a mainstay in the SoC design environment because design tasks are now divided among several subsets of a large design team. That allows several tasks to be completed simultaneously and thus reduce the time it takes to transition into the physical design stage and tapeout.

So the new version of SOS accommodates more remote sites through greater scalability and thus supports more users and data traffic. ClioSoft has managed to enhance the scalability by allowing SoC design teams to create work areas more quickly. Moreover, SOS7 boasts a better reporting infrastructure to streamline design workflow.

ClioSoft’s distributed architecture is inherently more suitable for multi-site SoC design

More Reliable Data Management

As mentioned earlier, the SoC designs are increasingly becoming complex, so they require appropriate levels of error resilience and security. ClioSoft’s SOS7 version further improves reliability with new features such as repository hot backup and balancing of the load to accommodate more users.

That’s on top of the existing SOS featureslike release and derivative management, integrated revision control, and issue tracking interfaces to commonly-used bug tracking systems. ClioSoft claims that SOS is the only design management platform that supports all types of designs: digital, analog, RF and mixed-signal.

Also read:

Starvision and SOS, a Perfect Match

Why Design Data Management: A View from CERN

ClioSoft Celebrates 2014 with 30% Revenue Growth!

August 7, 2015

Just One Month to SEMICON Taiwan

Just One Month to SEMICON Taiwan
by Paul McLellan on 08-07-2015 at 7:00 am
Categories: ESD Alliance, Semiconductor Services

SEMICON Taiwan is the first week of September in the Taipei Nangang Exhibition Center. To be precise it is September 2nd to 4th. Last year there over 26,000 people attended. This year it is the 20th anniversary show. SEMICON Taiwan attracts the world’s leading technology companies who design, develop, manufacture, and supply the technologies to manufacture the microelectronics that drive today’s most sophisticated consumer and commercial electronic products. So if you attend, you can connect with the companies, people, products and information shaping the future of design and manufacturing for semiconductors, nanoelectronics, MEMS, Photovoltaics and related advanced electronics.

For equipment manufacturers, there is no more important market than Taiwan. With new manufacturing technologies such as 450mm and EUV in development and with the continued growth of emerging and adjacent microelectronics markets (including high-brightness LEDs, MEMS, 3D IC, and plastic electronics), 2015 is already shaping up to be an important year for the global microelectronics supply chain. Taiwan is expected to invest over US$10 billion in 2015, which make Taiwan the single largest semiconductor equipment market in the world, ahead of the US and Korea.

Here are some of the things that will be taking place this year:

Opening Ceremony: 9/2 from 9.30 to 10.30 including ribbon cutting, awards, and VIP tour
Gala Dinner: an annual festival of Taiwan’s Hi-tech/Semiconductor/LED community with more than 400 industry leaders from around the world
Technology programs
- Day 1: Semiconductor materials forum, sustainable manufacturing forum, advanced packaging technology symposium, plus (all day), MEMS forum and (all day) TechXPOT on the main stage in the exhibit hall
- Day 2: (all or half day events running in parallel) High-tech facility international forum, eMDC forum, SIP global summit: 3DIC , IoT, TechXPOT
- Day 3: (all or half day events running in parallel) SIP global summit: wafer level packaging, CMP forum, IoT, automotive design, TechXPOT
Business programs
- Day 1 (1pm to 5pm) Executive summit
- Day 2 (8am-12pm) Market trends forum, (1pm to 5pm) CFO summit
- Day 3 (10am-5pm) Memory summit
National pavilions for Japan, Korea, Holland, Belgium, Germany, Russia and Cross-strait (I guess that is a tactful way of saying China)
Smart manufacturing pavilion, AOI (Automated Optical Inspection) pavilion, materials pavilion, precision machinery pavilion, hi-tech pavilion, secondary market pavilion, CMP pavilion, MIRDC (Metal Industries Research & Development Centre) pavilion, SICA (Silicon Carbide) pavilion
Job fair

If you are thinking of exhibiting, SEMICON Taiwan attracts a highly influential audience from every segment and sector of the European microelectronics industries, including semiconductors, solar/PV, LEDs, MEMS, printed/organic/flexible, and other adjacent markets. Above is the breakdown of visitors from 2014.

So join Jing-Jing, SEMCON Taiwan’s mascot, in September. Who is he? A baby born in a semiconductor plant, knows the movement of world’s semiconductor industry. With the radar on his head, Jing-Jing can forecast the market trends and connect the industry supply chain. He even has a Facebook page here.

Full details are here(English) and here(中文). Registration is here.

August 6, 2015June 14, 2019

Foolproof Your IP before it Stumbles in Higher-up Design

Foolproof Your IP before it Stumbles in Higher-up Design
by Pawan Fangaria on 08-06-2015 at 4:00 pm
Categories: EDA, Fractal Technologies

SoC designs are increasingly becoming assemblies of a large number of IP blocks. A well integrated assembly can lead to a successful PPA (Power, Performance and Area) optimized design. However, it is equally important that each IP block is optimized, robust, and integrable in the design. The complexity of an IP and its integration can be so high that any kind of re-work can prove to be very costly. This issue has been recognized by the SoC design industry; otherwise we wouldn’t have seen the emergence of IP cataloging for choosing the best IP for a particular function in an SoC. A semiconductor services company, eSilicon has gone much beyond cataloging by providing “Try IP Before You Buy” kind of services where you can check whether your chosen IP fits well in your SoC environment or not.

The point is, in the current IP and SoC market one cannot afford to lose on design time and miss occasionally available, small time-to-market window. Before using an IP for integration, a quick check on its quality and suitability for integration can save a substantial amount of rework down the SoC integration and verification flow. This can also enable you to better predict your SoC design and verification schedule. This is explained very well in a graph provided by Fractal Technologies which depicts how repair time during SoC integration after IP shipment starts increasing exponentially, thus destabilizing overall design schedule.

Fractal’s Crossfire has more than 200 checks to assess the quality and suitability of an IP for integration into an SoC. It has automated and integrated viewing, debugging, and reporting capability. Also, it provides user-induced waiving for particular rules to prevent unwanted checks, thus accelerating the consistency validation of an IP. The Crossfire also provides APIs for users to create their own custom checks for particular IPs.

Checking IPs is not as simple as it appears to be. A typical problem faced by designers is to maintain consistency among various formats encompassing different IPs and their integration into an SoC. The complexity of SoCs, IPs in various forms from third party suppliers across the world, and different levels of design abstractions and validations have led to significant increase in the number of formats to be supported at each level in the design flow. It’s essential that the consistency between these formats is maintained to avoid unnecessary iterations in the design flows. Consider the diagram below which represents several aspects of an IP, each represented in multiple formats and databases.

TheCrossfire supports each of these formats and checks for consistency between different aspects of an IP to ensure its integrity at all levels. The sheer number of views including functional representation, netlist, timing, power, reliability, layout, and test makes it really a difficult task to check the consistency at each level. It needs automated tool like Crossfire. The deep sub-micron processes have introduced another level of complexity to manage manufacturing variability at the design level, adding a few more formats to represent variability in the design flow.

The Crossfire ensures that the information represented across these views is consistent and does not contain any anomaly. In case of any mismatches or even modeling errors, Crossfire promptly reports it. A timely correction of such errors saves a lot of debugging and rework later during SoC integration. The Crossfire has a very easy-to-use GUI with graphical debugging, filtering, viewing and several other features for quick investigation into a design. There is automatic setup for batch runs as well. The existing customer scripts can be easily integrated into Crossfire environment. Also, there are APIs for creating database independent checks.

As it is evident, in today’s SoC and IP environment new formats keep evolving. The Crossfire has a robust methodology for adding new format support in its IP validation scheme. The detail about this methodology is given in a whitepaper at Fractal website. In the first half of this year, Fractal had added support for several new formats including APL, UPF, CTL, and AOCVM into Crossfire for IP validation. Most recently, it has added support for Spice v2lvs variant.

Along with the new format addition, Crossfire keeps adding a number of new rule checks with respect to the new format as well as existing formats as the checks are discovered internally at Fractal or during various IP checks at customer sites.

A tool like Crossfire can be relied upon for checking the quality and consistency of an IP before its integration into an SoC, thus shortening the overall SoC design schedule. Also, by using this tool the SoC integration schedule can be made more predictable.

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

August 6, 2015

How to prevent execution surprises for Cortex-M7 MCU?

How to prevent execution surprises for Cortex-M7 MCU?
by Eric Esteve on 08-06-2015 at 11:00 am
Categories: Arm, Foundries, IP

ARM Cortex-A series processor core (A57, A53) are well known in the high performance market segments, like Application Processor for smartphone, Set-Top-Box or networking. If you look at the electronic market you realize that multiple applications are cost sensitive and doesn’t need such high performance processor core. We may call it the embedded market, even if this definition is vague. The ARM Cortex-M family has been developed to address these numerous market segments, starting with the Cortex-M0 for lowest cost, the Cortex-M3 for best power/performance balance, and the Cortex-M4 for applications requiring digital signal processing (DSP) capabilities.

For the audio, voice control, object recognition, and complex sensor fusion of automotive and higher-end Internet of Things (IoT) sensing, where complex algorithms for audio and video are needed for rich audio and visual capabilities, Cortex-M7 is required. ARM Ltd. offers the processor core as well as the Tightly Coupled Memory (TCM) architecture, but ARM licensee like Atmel has to implement memories in such a way that the user can take full benefit from the M-7 core to meet system performance and latency goals.

In a 65nm embedded Flash process device, the Cortex-M7 can achieve a 1500 CoreMark score while running at 300 MHz, offering top class DSP performance: double-precision floating-point unit and a double-issue instruction pipeline. But algorithms like FIR, FFT or Biquad need to run as deterministically as possible for real-time response or seamless audio and video performance. How to best select and implement the memories needed to support such performance? If you select Flash, this will require caching (as Flash is too slow) leading to cache miss risk. SRAM technology is a better choice as it can be easily embedded on-chip and permit random access at the speed of processor.

Peripheral data buffers implemented in general-purpose system SRAM are typically loaded by DMA transfers from system peripherals.

The ability to load from a number of possible sources, however, raises the possibility of unnecessary delays and conflicts by multiple DMAs trying to access the memory at the same time. In a typical example, we might have three different entities vying for DMA access to the SRAM: the processor (64-bit access, requesting 128 bits for this example) and two separate peripheral DMA requests (DMA0 and DMA1, 32-bit access each). Atmel has get round this issue by organizing the SRAM into several banks as described in this picture:

For chip maker designing microcontroller, licensing ARM Cortex-M processor core provides numerous advantages. The very first is ubiquity of ARM core architecture, being adopted in multiple market segments to support variety of applications. If this chip maker wants to design-in a new customer, the probability that such OEM has already used ARM based microcontroller is very high, and it’s very important for this OEM to be able to reuse existing code (we know the heavy weight linked with software development, in the 60% to 70% of the overall project cost). But this ubiquity generates a challenge: how to differentiate from the competition when competitors can license exactly the same processor core?

Selecting a more aggressive technology node, providing better performance at lower cost is one option, but we understand that this advantage can disappear as soon as the competition also move to this node. Integrating larger amount of Flash is another option, very efficient if the product is designed on a technology allowing to keep the pricing low enough.

If the chip maker has designed on an aggressive technology node, allowing providing higher performance and offering larger amount of Flash than the competition, it may be enough differentiation. Completing with the design of a smarter memory architecture unencumbered by cache misses, interrupts, context swaps, and other execution surprises that work against deterministic timing allow bringing strong differentiation.

If you want to more completely understand how Atmel has designed this SMART memory architecture for the Cortex-M7, I encourage you to read this white paper from Jacko Wilbrink and Lionel Perdigon “Run Blazingly Fast Algorithms with Cortex-M7 Tightly Coupled Memories”. (You will have to register).

This paper describe MCUs integrating an SRAM organized into four banks that can be used as general SRAM and for TCM, showing one example of a Cortex-M7 MCU being implemented in the Atmel® | SMART SAM S70, SAM E70, and SAM V70/1 families.

By Eric Esteve from IPNEST

More products and design kit on Atmel Sales portal:

http://www.atmel.com/products/microcontrollers/arm/sam-v-mcus.aspx (SAM V)
http://www.atmel.com/products/microcontrollers/arm/sam-s.aspx (SAM S)
http://www.atmel.com/products/microcontrollers/arm/sam-e.aspx (SAM E)
http://www.atmel.com/tools/atsamv71-xult.aspx?tab=devices (device evaluation kit)

August 6, 2015June 14, 2019

Ultra-low Voltage: Is Your Slack Really Positive? Are You Sure?

Ultra-low Voltage: Is Your Slack Really Positive? Are You Sure?
by Paul McLellan on 08-06-2015 at 7:00 am
Categories: CLK Design Automation, EDA

During synthesis and static timing the main figure of merit is “slack”. If a signal arrives with time to spare before it is needed (often measured against the setup time before a clock changes at a register) then the slack is positive. Positive slack is generally a good thing, although it can indicate over-design if it is large. If a signal arrives late then the slack is negative. Obviously, the goal for signoff is to have all slack positive or zero.

Signal timing is actually measured against timing constraints. These come from two sources. One is the user who can specify things like the clock frequency or timing limits at output pins. These basically let the user express the desired behavior of the design. The other source is the cell library where the characterization data is captured. Particularly important are the setup and hold times for flipflops and latches. A further complication is that these checks need to be performed at several process “corners”, traditional ones such as FF and SS but for a modern process, at many other temperature, voltage and process conditions too.

Measuring slack for ultra-low voltage operation—below 0.7V—brings additional challenges, especially process variance. Paths that appear to pass timing within a corner may fail when process variance is included. Even at older process nodes such as 55nm or 65nm, process variance within a PVT corner can show up when the threshold voltage is severely reduced.

The set-up and hold timing checks that are pre-characterized for flip-flops, latches and registers in a cell library are especially vulnerable to variation. Process variance has as much impact on the timing constraints as it does on delay variation. In fact, the corner timing constraints for lower voltages may be extremely optimistic and hide timing violations. They are overstating the timing slack in the design.

During the medieval ages of chip design the solution was always to trade off any lack of accuracy with pessimism. How bad can it be? Use that number. But in a modern process, that doesn’t work. Often it will prove impossible to close timing with “that number” because there isn’t enough timing headroom to waste a lot of it on pessimism. Plus “that number” varies depending on corner, temperature, load, slew-rate and so on. Lack of accuracy has to be fixed by increasing accuracy.

The Liberty Variation Format (LVF) supports an approach known as constraint uncertainty. This adjusts the timing constraints to reflect the impact of process variation on a very granular basis: each slew/slew constraint condition gets a unique value. Constraint uncertainty makes sure that margin gets added in exactly the right places, and with the level of conservatism the user specifies to protect against critical set-up and hold violations. By combining constraint uncertainty with arc/load/slew specific delay variance (also supported by LVF) engineers can close timing with much higher confidence and precision. There are other approaches, such as adding values direct to the .lib timing library, but they suffer from various limitations.

Timing constraints, like the delay tables for the libraries, have traditionally been characterized at the process corners: SS and FF. They do not use the global corners SSG/FFG and then add in local on-die variance. However, process variation can affect the transistors inside of a flip-flop or latch just as much as they do the gates along a data or clock path. Engineers are often shocked to see that delay can swing by as much as 2X or more on a cell because of process variation.

For example, the diagram above shows the setup constraint for a 20nm flipflop measured at 1V (in green). It also shows the constraint measured at the SS corner (one of the places where cells are normally characterized) versus SSG+3σ (the red vertical dashed lines). There is considerable pushout, the constraint is optimistic. Turning to the 0.65V characterization (in blue) there is an even larger pushout (to the red dotted line). The constraint is very optimistic and so will overstate slack. What looks like a reassuring positive slack may well be negative slack, a recipe for a chip that doesn’t work.

There are two approaches to generating constraint uncertainty values: Monte Carlo (MC) SPICE or CLKDA’s Variance FX. All of the MC SPICE based approaches depend on sampling. Simulating a flip-flop is time consuming at best; simulating it 100’s of times or 1000’s of times for accuracy at low voltage, can be prohibitively slow. Variance FX, the industry leading solution for variation characterization can be hundreds of times faster than MC SPICE. The FX model and simulator solve for variance without any sampling and are typically within ± 2% of MC SPICE for nominal ± 3σ. Variance FX supports the classic approaches for constraint uncertainty, and has multiple options for characterizing constraints efficiently.

The bottom line: traditional corner based constraints are very optimistic, and will overstate timing slack. Paths that appear to be passing may be failing, and by a lot. Positive slack may be negative. Working chips may…not.

The CLKDA white paper The Impact of Process Variance on Timing Constraints and Slack at Ultra Low Voltage is here.

August 5, 2015December 27, 2023

CEVA in More than 6 Billion Chips!

CEVA in More than 6 Billion Chips!
by Daniel Nenni on 08-05-2015 at 8:00 pm
Categories: Ceva, IP

One of the IP companies that I track is CEVA, the largest licensor of DSP cores. CEVA is the fifth largest IP company behind ARM, Synopsys, Imagination Technologies, and Cadence (Lattice acquired Silicon Image). CEVA is actually a combination of companies which started with the DSP Group and Parthus Technologies in 2002 and RiveriasWaves (WiFi and Bluetooth) in 2014. Today CEVA has signed 375+ license agreements that have resulted in more than 6 billion chips shipped around the world serving the mobile, consumer, automotive, and IoT markets. CEVA has been with SemiWiki since 2012 with 60 blogs published to date and viewed 231,626 times so we know them quite well.

First let’s take a quick look at the Q2 financials:

Total revenue was $13.4 million (45% YoY Increase)
Licensing and related revenue was $7.7 million (76% YoY increase)
Royalty revenue was $5.7 million (17% YoY Increase)

And the most interesting comment during the investor call to me was:

“From CEVA perspective, the smartphone market opportunity is under-exploited. IDC estimates that over 8.5 billion smartphone will be sold from 2015 through 2019. According to GSMA intelligence, 2G technology still accounts for 58% of the world’s 7 billion mobile connections. This large installed base is a prime candidate for upgrade to 3G and LTE smartphone.”

To this I agree wholeheartedly and to highlight that, three key CEVA customers were also discussed: Samsung, Xiaomi, and Intel. With the advent of chip teardowns (chipworks and iFixit) the building blocks of SoCs are no longer secret. Xiaomi, the largest smartphone vendor in China, is using CEVA for LTE as is Samsung, the largest smartphone vendor in the world. Even Intel, the largest semiconductor company in the world, uses CEVA for LTE in their SoFia SoCs and XMM7360 modems.

The other part of CEVA’s business is the newly acquired RivieraWaves Bluetooth and Wi-Fi which you may have seen advertised on SemiWiki. According to CEVA RivieraWaves provides the industry’s lowest power Bluetooth IP compatible with any MCU/CPU and RF available on the market today. RivieraWaves Wi-Fi on the other hand offers a comprehensive suite of platforms for embedding Wi-Fi 802.11a/b/g/n/ac into SoCs and ASSPs. Optimized implementations are available targeting a broad range of connected devices, including smartphones, wearables, consumer electronics, smart home, industrial, automotive applications, etc…

For a more detailed look at RivieraWaves Wi-Fi read: Apple Watch Design Revisit with a Wi-Fi Twist. SemiWiki blogger Majeed Ahmad did a really nice job on this one, absolutely.

About CEVA, Inc.
CEVA is the leading licensor of cellular, multimedia and connectivity technologies to semiconductor companies and OEMs serving the mobile, consumer, automotive and IoT markets. Our DSP IP portfolio includes comprehensive platforms for multimode 2G/3G/LTE/LTE-A baseband processing in terminals and infrastructure, computer vision and computational photography for any camera-enabled device, audio/voice/speech and ultra-low power always-on/sensing applications for multiple IoT markets. For connectivity, we offer the industry’s most widely adopted IPs for Bluetooth (Smart and Smart Ready), Wi-Fi (802.11 b/g/n/ac up to 4×4) and serial storage (SATA and SAS). One in every three phones sold worldwide is powered by CEVA, from many of the world’s leading OEMs including Samsung, Huawei, Xiaomi, Lenovo, HTC, LG, Coolpad, ZTE, Micromax and Meizu. Visit us at www.ceva-dsp.com and follow us on Twitter, YouTube and LinkedIn.

August 5, 2015

An Open Letter to Qualcomm CEO

An Open Letter to Qualcomm CEO
by Pawan Fangaria on 08-05-2015 at 12:00 pm
Categories: EDA, IoT, Mobile

Dear Steve,

Let me first clarify about myself that I am a humble blogger at Semiwiki and admire your company as the #1 Semiconductor Fabless Company and #4 in terms of overall semiconductor sales of the top10 semiconductor companies in the world as per 2014 data. Also, I must mention another point of admiration that your company is #2 in terms of R&D expenditure. I neither own a single Qualcomm stock, nor recommend anyone to buy or sell. However, observing the turmoil your company is going through this year, I would hate to see it getting out of the top10 list or even falling into lower ranks in that list. So, I thought of writing this sincere, open letter to you in the spirit of what best Qualcomm could do to stay relevant and even win the war in near future. Of course, there is a substantial struggle going forward, but even a single wrong step can lead the company into further trouble. Think it from a complete neutral perspective; keep the pressure from various sides aside for a while.

It takes years of effort, energy, resources, and what not to build a scale of business like Qualcomm has. It must not be destroyed. Remember the BCG matrix? In a large organization, it generally has all kinds of businesses – Stars, Cash Cows, Dogs, and Question Marks. In Qualcomm, as I see it, it has a great Cash Cow and a Star which has moved into Question. Fortunately, I do not see Dogs there. So, situation is not that bad as it is being projected. Truly speaking these integrated elements of an organization cannot be separated. The Cash Cow has to feed others and get fed in return; there needs to be an unquestionable integrity into that. Yes, there is pressure from investors to split the cow and the star in question. The investors care about short-term returns on their investments. If they can be pacified by other means, that’s it; in the long run they would realize that ‘not splitting’ was a blessing in disguise. Also, a split can be in the form of actually ‘not a split’. Here are the strategies which can be adopted for a win-win from all sides –

Form a Holding Company – Constitute a new Qualcomm Holding Company (QHC). Provide autonomy to QCT and QTL to run as stand-alone businesses with their separate BOD and equity capital. QHC will own both QCT and QTL and it will have participation in the board from QCT and QTL, as well as institutional investors. JANA Partners already has two of their representatives in the Qualcomm board. They can very well represent in QHC. By doing this Qualcomm doesn’t have to actually sell any of its unit and at the same time it can bring more returns to investors. QTL and QCT should keep complementing each other as they have been doing; earnings will be different because of the types of business models in them, but then investors will be compensated according to their holdings in them.

RIF is already on the horizon – You have already announced about RIF. That can provide a breather on cost cutting and pacify investors. However, my sincere opinion would be to cut where the fat is. Often large organizations do a mistake cutting at wrong places. You have to take the pain of identifying the fatty regions in your organization before cutting. If you do that it would be right to cut and would provide short as well as long term benefits as well.

Partner instead of straight M&A – I understand, you want to diversify to bring higher returns to your investors. This can be done in more creative ways than acquiring a company. There are rumours about Qualcomm acquiring AMDto get into server business. This is a good strategy as it augments well with your IoT plan which is gaining strength on Gateway side and the server business can let you enter into the Cloud. However in my view, acquiring AMD and wielding it against Intel to win in the server business could be a long haul.

Similarly, there are other companies being talked about to be the acquisition targets of Qualcomm. Also, QCT is being talked about as the acquisition target of Intel. I would not go into those details here. My simple suggestion to you would be on the following lines –

Identify your immediate battle ground, it’s not server business, it’s China region which is key to mobile processor business today. The mobile business is QCT’s backbone. So, protect that. What’s the key issue there? It’s price war. Who are the main players? They are you, Intel, Spreadtrumand MediaTek. You know your main rival there. Now identify a player among the others who is strong and may need your help. There you go.

Intel too wants to cut the pie in the mobile market. They are aggressively following the China market, rightly. However, they are losing substantial dollars in the mobile business. Given a favourable deal, in my opinion, they should be willing to pursue. Qualcomm has the mobile technology, but you need to cut cost. You have a chance to share mobile technology with Intel and get into manufacturing pact with Intel to cut cost. Both companies can make it a win-win here in the mobile business. Eventually, you will have an answer for your high-end turf in the mobile business too. Today, the route for mobile business starts from China!

Coming to IoT, you stand a great chance to win with your powerful connectivity solution from Atheros acquisition. QCA401x is an ideal, power and cost optimized chip for IoT applications with right amount of memory for holding data and interfacing with several devices. It also has security and various communication protocols including WiFi, IPv6, and http. Similarly, QCA4531 is low-cost solution leveraging Linux environment, good for hub in IoT systems. Also, with your next generation 4G LTE and secure Bluetooth and GPS technology from CSR acquisition, you can bring new dimensions in the IoT connectivity, short as well as long distance. You are good at Gateway solution. To enter the cloud, again get into some kind of agreement with Intel for servers at this point of time. You can expand later. PC business is a no-no, it will not provide growth. For IoT edge devices, just wait for a while. The market will be flooded with edge devices in a few years from now. You can get a better value at low price for edge-device solution at that point of time.

I am leaving it open for the audience to share their views. Their unbiased views can definitely come a long way in rebuilding of the pioneer, innovator, and trend-setter in the fabless world.

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

August 5, 2015June 14, 2019

Acoustic Resonators for RF: MEMS with No Moving Parts

Acoustic Resonators for RF: MEMS with No Moving Parts
by Paul McLellan on 08-05-2015 at 7:00 am
Categories: Coventor, EDA

There is an annual conference known officially as the Sensors and Actuators Workshopand informally as Hilton Head since it is held on Hilton Head island in South Carolina. Coventor talked to some of the top researchers last year about RF filters and decided to develop a simulation solution that would better serve both the researchers and commercial designers. Recently they delivered with the recent CoventorWare 10 release which includes a new (and unique in the industry) fast analysis capability for acoustic resonators.

Market pressure for RF filters to be compact and inexpensive, yet meet the higher performance requirements of the 4G standards, has spurred great interest in novel filter design concepts that further miniaturize the transmit/receive chain of RF frontends The first successful filters were surface acoustic wave (SAW) filters, but in the past few years the number of bulk acoustic wave (BAW or FBAR) filters within a handset has grown rapidly to fill the market demand above 1 GHz where SAW device performance degrades. Most recently, bulk mode resonators that vibrate in plane to allow multi-frequency filters on one substrate have garnered significant interest within the research community. These in-plane bulk-mode resonators come by various names such as contour-mode resonators (CMR) and laterally-vibrating resonators (LVR).

These acoustic resonators have become more popular as the number of filters in a typical mobile device has increased to around 30 per phone. The best known success story in the space has been Avago’s FBAR which proved the higher performance of bulk-mode devices compared to conventional SAW filters.

Acoustic resonators are designed using MEMS techniques even though they do not have any moving parts. It is one thing to be able to design them but there has been a major missing piece to the jigsaw, computationally efficient algorithms to perform frequency sweep simulations in a reasonable time. Current solutions take days (literally) and that is a 2D simulation, which is not good enough. 3D takes so long as to be impractical. This obviously limits both the amount of exploration that can be done and the accuracy with which the performance can be predicted.

Matt Kamon of Coventor told Professor Songbin Gong at the University of Illinois about the proprietary fast frequency-sweep algorithms specifically for MEMS piezoelectric resonators. He claimed Coventor could simulate his 3D designs in minutes where his current tool took hours, and do in hours what previously took days. Since the Hilton Head 2014 conference, Professor Gong and his group have worked with Coventor to polish this offering specifically for rapid design of cutting-edge acoustic resonators.

Coventor have named the offering “FastPZE” and it is part of CoventorWare 10. The diagram above shows the accuracy. The red line shows conventional simulation (actually the red circles are the only points simulated and then the points were just joined up). The black line, which shows a lot more detail, is the result of the FastPZE algorithm. Both simulations took the same amount of time.

Another point to emphasize is that designs are not necessarily constructed with Manhattan geometries. A design may consist of arbitrary polygons or curves. In some simulation tools, this would require a mesh made of tetrahedrons. Unfortunately, since these are thin-film devices, this can lead to an extremely large number of mesh elements and consequently very long simulation times. CoventorWare, in contrast, provides very efficient meshing for thin-film devices of non-Manhattan shape with straight or curved edges as shown in the above diagram.

Download Matt’s white paper Fast Acoustic Resonator Analysis for the Rapidly Growing Premium RF Filter Market here.

August 4, 2015September 1, 2024

China (and Cupertino) Are Killing Korea in Mobile

China (and Cupertino) Are Killing Korea in Mobile
by Paul McLellan on 08-04-2015 at 7:00 am
Categories: Foundries, Mobile, Samsung Foundry

Samsung, #1 in the mobile phones based on unit shipments, has two big problems in mobile. Apple’s iPhone; and China in general and Huawei in particular in the Android world where they live. They have just announced their fifth quarter of decline. Revenue was down 8% year on year but operating profit declined 38%. They sold 89M handsets (which includes about 20% of non smartphones, so maybe 72M smartphones). Their big problem market is China where they used to be the market leader but now are behind Apple, Huawei and Xiaomi (and maybe Lenovo/Motorola).

One problem is that the Galaxy 6 is not selling as well as expected. I’ve read that a problem with Galaxy 6 is that Samsung pretty much cloned an iPhone. Since iPhone doesn’t have a replaceable battery, or a memory card slot, and is not waterproof, those things don’t matter, right? The problem is that the Galaxy 5 had all of those things and probably some of its success was due to people who cared about them picking Galaxy over iPhone. After all, if you want an iPhone then why not just buy one; Apple will be happy to sell you one. But if you really want something different from iPhone, then how about the curved screen. Buy the “edge” version. The problem is that you can’t since, according to Bloomberg anyway, they failed to produce enough curved screens to satisfy demand. They said that they will increase their capacity for curved screens early next year (horses and stable doors spring to mind).

Or if you want a replaceable battery, waterproofing, memory slot then you have lots of choices and Huawei seems to be one of the beneficiaries. Analysts were expecting them to sell 50M smartphones in the first half but they also just announced that they sold 10M phones in each of May and June, which is clearly a higher run-rate. They must be close to 30M smartphones for the quarter. And, yes, they are profitable. They look to be #3 with 7% market share, ahead of Xiaomi who are now trying to sell in markets other than China and Singapore (such as India) where they don’t have existing distribution channels.

Samsung have said that they will further reduce prices on the Galaxy 6 to drive growth, but as Yoo Eui Hyung, an analyst with Dongbu Securities in Seoul, says:Poor sales of S6 only proved that it can’t beat Apple in brand loyalty among users and just ended up being one of the many Androids. The price cuts may increase sales, but I highly doubt it could promise bigger profit growth.

But there are two Korean cell-phone manufacturers. If Samsung is struggling then surely LG should be a beneficiary. But they only sold 14M phones in Q2, down 8% from Q1, and are basically breakeven. Their flagship phone, the G4, has the features that Samsung dropped from the Galaxy 6 so it is weird that they haven’t picked up share. Since they are only breakeven they have already executed what Samsung plans, namely selling the phones at a low price. That can drive volume but not profit. LG’s profits fell 45% mainly due to smartphone sales being down.

One area where Samsung is doing well is semiconductor. The switch from Qualcomm’s Snapdragon to internally developed Exynos was widely reported, not least in veiled remarks on Qualcomm’s earnings calls. Between the application processor business, and their memory business (plus some other smaller businesses) their profits in semiconductor are up 83%. But Samsung semiconductor needs Samsung mobile to be successful. Every Galaxy 6 sale lost to Huawei is an Exynos chip not sold. That dynamic may change a little going forward since Apple’s 6S application processor is known (or at the very least strongly rumored) to be fabricated by Samsung Foundry. So Samsung Semiconductor would love Galaxy 6 to be wildly successful, but when they lose a sale then they want them to lose to Apple not Huawei or Xiaomi.

The Bloomberg piece is here.