New Tool Suite to Accelerate SoC Integration

New Tool Suite to Accelerate SoC Integration
by Pawan Fangaria on 06-16-2015 at 12:30 pm

Today, an SoC is seen in the context of an optimized assembly of IPs; it’s no more a single monolithic chip design. It’s very common to see an ARM processor IP along with an interconnect IP, a memory IP, and couple of buses and interfaces IP in an SoC. Although the SoC seems to be an integrated collection of IPs, it can be very complex and the number of IPs can grow to any extent. From a manufacturing point of view, the power, performance and area (PPA) are the parameters to worry about at the IP level. For an SoC, there can be large catalogs of optimized IPs in every category from where the best IPs can be picked up and assembled in the SoC. Of course, the problem gets enlarged at the SoC level because one has to choose the right IPs and then integrate them in the most optimized manner to achieve best PPA, latency, and minimum congestion. The overall system throughput must be at the maximum within the given power and area constraints.

The problem is even wider in economic sense, because an SoC is a complete system that needs to be targeted to a particular market segment within specified cost parameters. The target segment, cost, and IP integration architecture are the key criteria for an SoC which appear much before the PPA for its success in the market place. There was a whitepaper written by me a couple of weeks ago (link to the whitepaper is at the end of this article) which provides details about the key criteria for SoCs in modern context. Today, I’m extremely happy to see the automated tools that address these top criteria for SoC integration.

During 52[SUP]nd[/SUP] DAClast week, it was a very pleasant occasion when I met Andy Nightingale, VP of System IP Marketing at ARM; Norman Walsh, Director of IP Tooling at ARM; and Simon Rance, Senior Product Manager of System and Software Group at ARM who demonstrated an innovative IP Tooling Suite developed at ARM for very fast and optimized SoC integration. That’s when I remembered about my whitepaper because it exactly touches upon some of the key criteria for SoCs mentioned there. Let’s see how this suite of tools helps in SoC integration.

ARM Socrates DE provides an advanced design environment where desired IPs can be chosen from an IP catalog, and then instantiated and configured as per designers’ need. The design environment is common to ARM’s existing environment that takes advantage of the already built-in protocols. It also supports third party IPs to be integrated into the sub-system or SoC. The IP-XACT format is used to maintain the IP interfaces at the industry level standard. If any third party IP does not have an IP-XACT description than the environment has utility to automatically generate IP-XACT from the RTL and point out mismatches, if any. The interesting part about Socrates DE is that it allows designers to customize IPs into different configurations to differentiate from others and instantly provides BOM (Bill of Material) for the overall sub-system or SoC. By using this tool, a designer can do several trials to configure IPs and optimize the overall sub-system or SoC for a target application within the given budget. The configuration and optimization of the SoC can be done in a day’s time or even hours as against several months to evaluate between various options without this tool.

After the initial architecture determination within the Socrates DE, there is ARM CoreSight Creator which provides an excellent Debug & Trace System seamlessly integrated with the Socrates DE. The CoreSight Creator is used to fine-tune the micro-architecture for better configuration efficiencies. It uses all built-in design rules provided in the ARM environment.

Another vital component in the tool suite is ARM CoreLink Creator which optimizes the Interconnect System for congestion free operation. ARM’s new CoreLink NIC-450 Network Interconnect offers a tool-driven automation flow that employs algorithms for tasks such as ensuring deadlock-free operation and partitioning across multiple power/voltage domains.

The overall suite of tools provides the most optimized and correct-by-construction configuration for an SoC or a sub-system along with its associated testbench. This approach reduces the SoC turn-around time and the risk of re-spin by a large extent because of improved predictability and QoR.

The ARM platforms including a large IP portfolio and suite of tools for IP configuration and integration provide an ideal platform for SoC integration. ARM’s partners can gain most value out of this system in today’s SoC environment. I am told that already there are more than 50 System IP tooling partners with ARM. It’s natural because finding right BOM with an optimized configuration and architecture for IP integration into the SoC is a burning need today.

ARM press release is here.
Here is my whitepaper “SoCs in New Context – Look beyond PPA”.
Also read “Even More Integration and Automation for ARM-based Designs

Pawan Kumar Fangaria
Founder & President at