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August 3, 2015

Why Modern SoC need cache-coherent NoC?

Why Modern SoC need cache-coherent NoC?
by Eric Esteve on 08-03-2015 at 4:00 pm
Categories: IP, NetSpeed Systems

Launching high technology product on the semiconductor market after your competitors is not necessarily a weakness. NetSpeed has developed NocStudio, a front end optimization design tool helping architects to create SoC architecture bridging the gap with the back end, floor planning and place and route. Created about 20 years after Sonics and 8 years after Arteris, NetSpeed has capitalized on the positive (Sonics and even more Arteris have evangelized the semiconductor industry about how important NoC integration could be for design optimization and to avoid routing congestion) and learn from competitor’s weaknesses, the most crucial being the need for a NoC to support cache-coherency in modern multi-core designs.

Approaching design teams involved into System-on-Chip (SoC) like Application Processors for smartphones and the numerous SoC developed to support Multimedia, Network Processing, Servers, Computing and so on, NetSpeed has realized that their main competitor is internal design team! NetSpeed evaluates that about 80% of the SoC integrates internally developed solutions like proprietary buses, crossbars, and fabrics.

NocStudio is a graphical tool helping automate an SoC design and generating Gemini NoC, for chips that have cache coherent processor cores (CPUs, GPUs, or DSPs), or Orion NoC for chips that don’t need cache coherence. Gemini supports up to 64 processor clusters and up to 200 other components that may be I/O coherent. Gemini enables a massively parallel chip design with up to 256 CPUs.

Figure 1. NetSpeed’s Gemini network-on-chip.

NocStudio final output includes performance statistics, the RTL files required to synthesize the NoC, a C++ functional model, and verification test benches. By speeding the design process and reducing risks, NetSpeed’s tool helps cutting costs and shortening the time to market. With NetSpeed’s On-Chip Network IP topology that connects all the IP blocks in a preliminary floor plan that optimizes the design for performance, power efficiency, die area, low latency, and deterministic quality of service (QoS).

In addition, NocStudio is a correct-by-construction design tool that prevents fatal errors such as protocol- and network-level deadlocks (To learn more about why this front-end design tool is “correct by construction” and how the tool has been designed, just read this post). NocStudio provides a software layer helping SoC architect providing configurability in a coherent system at no risk. In fact, customer who desires to configure a complex system requires that they either know all of the details needed to configure it correctly, or that there is some method of ensuring that whatever they do specify will behave correctly.

Figure 2. Designing a NoC with NocStudio.

Architects can drag and drop all the desired IP blocks into NocStudio’s main window. With each addition or modification, NocStudio automatically displays a script in the lower window that defines the IP blocks for the synthesis compiler. The other approach is to manually write or edit the script that defines the IP blocks by using the command-line interface in the lower window.

To optimize traffic among IP blocks that may have different latency, bandwidth, or protocol requirements, NocStudio can vary the data-path widths from 8 to 1,024 bits and create up to 8 heterogeneous physical networks and 32 virtual networks. (Virtual networks appear as separate NoCs but use the same wires.) Because Orion and Gemini are intended mainly for ARM-based SoCs, they connect directly to IP blocks that support AMBA 4 (an AMBA 5 version is in development) and AXI protocols. NocStudio’s final output includes performance, power, and area statistics; the RTL files required to synthesize the NoC; a C++ functional model; and verification test benches

Figure 3. Optimizing Orion.

On the figure 3 we can see the chip optimization on a real life example, step by step, placement, layers, routing and channels optimization allows generating a SoC dissipating 60% less power than with AMBA AXI interconnects.

NocStudio is a front end optimization design tool and we think that such tools will become unavoidable for today’s SoC designs, like was software compiler and RTL synthesis before: the Time-To-Market pressure linked with the incredible race for always higher complexity (100’s of million gates, dozens of CPU/GPU/DSP cores) offered by the latest technology node are now pushing to change design methodology. It’s no more acceptable to discover deadlocks at Tape Out (and if you are even more unlucky, afterTO), as new iteration generated by this architecture issue is not only costly, but may jeopardize the SoC success and lead to miserable ROI, just because the TTM window has been missed.

Sooner or later, the industry will embrace front-end design tools that inevitably will look very much like NocStudio. Architects who need a scalable, high-performance, correct-by-construction SoC interconnect should evaluate NetSpeed’s technology, especially if the design requires cache coherence.

I encourage you to read the white paper “Automating Front-End SoC Design With NetSpeed’s On-Chip Network IP” By Tom R. Halfhill from the Linley Group.

From Eric Esteve from IPNEST

August 3, 2015July 18, 2025

More FPGA-based prototype myths quashed

More FPGA-based prototype myths quashed
by Don Dingee on 08-03-2015 at 12:00 pm
Categories: EDA, FPGA, Synopsys

Speaking of having the right tools, FPGA-based prototyping has become as much if not more about the synthesis software than it is about the FPGA hardware. This is a follow-up to my post earlier this month on FPGA-based prototyping, but with a different perspective from another vendor. Instead of thinking about what else can be done beyond just prototyping, Synopsys has taken on three big myths surrounding the concept in a new white paper.

A very interesting point to me is the first one taken on by product manager Troy Scott: FPGA-based prototype capacity is often perceived as limited to less than 100 million ASIC gates. If we believe other sources, the magic numbers in this equation are 5 million gates or less, and 80 million gates or more. Stunningly, the 2014 Wilson Research Verification Study shows that people are actually less successful on the smaller designs. The overall first and second spin success rate, according to that study, is lower for designs at 5M gates than it is for designs at 80M gates.

That may be because people are spending more time and effort in verification and validation of larger designs. For that job, they are using better tools such as emulation and FPGA-based prototyping platforms – which are about even in terms of industry adoption, both around 33-35%.

However, prevailing wisdom says that as designs get larger, the reluctance to use FPGA-based prototyping seems to increase and the adoption rate drops. We’ve all seen news that the raw capacity of platforms like HAPS-70 have increased substantially with introduction of Xilinx UltraScale VU440 parts – Synopsys is now shipping these platforms to early adopters.

So, what’s the hold up? Myth #1 is the 100M gate barrier. There is no doubt one can now get 100M gates poured into an FPGA-based platform. The first concern is can one build and rebuild a design on that platform for 100M gates in a reasonable amount of time? Troy goes through an analysis using Synopsys ProtoCompiler, which leverages parallelism up to four concurrent processes of synthesis. The result is a 10 hour turnaround – 4 hours in synthesis and partitioning, 6 hours in place & route.

In a more advanced situation, ProtoCompiler supports any number of compile points, even allowing nesting. This facilitates incremental builds, where only part of the design is rebuilt. The four current processes can be applied to four compile points, so rebuilds of changed areas can go faster than the entire build. Multiple licenses can also be ganged to increase parallelism.

Myth #2 is the partitioning effort. Troy shares some data from the R&D team at Synopsys – recall they are also in the IP business, and they eat their own dog food so to speak – showing benchmarks on partitioning time across 13 programs. (They aren’t triskaidekaphobic, apparently.) These benchmarks include the use of high-speed interconnect TDM schemes, automatically generated by ProtoCompiler. The results may be surprising, showing a realistic view of days, not months, to get to a working design.

Myth #3 is debug. That does get tricky on multi-FPGA prototypes. Troy explains how ProtoCompiler handles instrumentation, coordinates with the deep trace debug capability in HAPS, and deals with external DDR3 memory for debug resources. One critical point Troy makes is that hundreds of signals can be captured for full seconds of clock time. Or, things can be stretched to grab more signals for shorter periods.

The full paper is here (registration required):

Busting the 3 Big Common Myths About Physical Prototyping

The upshot of all this is we’re not just talking about gate capacity any more. Maybe we should be talking more about the low end, which is why Synopsys introduced HAPS-DX for smaller environments. Being able to synthesize designs faster, while inserting effective partitioning and debug, is what makes an FPGA-based prototyping platform really useful. In both the small and large cases, it is the ProtoCompiler technology where Synopsys is making progress.

August 3, 2015July 18, 2025

John Koeter: How To Be #1 in Interface IP

John Koeter: How To Be #1 in Interface IP
by Paul McLellan on 08-03-2015 at 7:00 am
Categories: EDA, IP, Synopsys

John Koeter is in charge of marketing Synopsys’ IP and prototyping solutions. I talked to him last week.

He grew up in upstate New York, son of a Scottish mother and a Dutch father who immigrated to the US, so he is first generation American, unlike everyone else I’ve interviewed so far for this series who were born overseas. He stayed in upstate New York for college and got a BSEE from Cornell.

After graduating, he joined TI in Dallas and did various jobs in TI ASIC, at one point moving to California for a couple of years to run a couple of design centers. One of his primary competitors was VLSI Technology where I was working at the time. We were always frustrated that TI had Nokia, which was the cell-phone market leader, locked up and we never had any success there. After 11 years at TI he decided he preferred Austin to Dallas and joined AMD in the embedded processor division, which was in the process of switching from the 29K bitslice approach to low end x86. But after a couple of years there was the usual semiconductor downturn.

He moved on and in 1998 joined Synopsys where he has been for 17 years now. He started as a program manager and then moved into business development for services doing production turnkey designs (this was the Tality Design Services era). After doing that for a time he went into sales for IP and services as a sort of east-coast overlay. When the position of VP marketing for the IP and prototyping opened up he took it. He has done that job for about 7 years now, covering IP, prototyping and FPGA synthesis. He also runs the pre-sales AE organization for those businesses.

We started by talking about IP. This is a business that Synopsys has been in for 25 years, starting with DesignWare which was basically datapath, UART, i[SUP]2[/SUP]C, timers and other basic building blocks of that era. The big transition came when they purchased inSilicon and got into USB and PCI Express on the digital side. A year later Synopsys acquired Accelerant and was in the SERDES business. They grew the business, partially organically and partially through other acquisitions such as Cascade. They really got heavily into analog when they acquired the analog business of MIPS (aka Chipidea).

One big change was that they started to package up a complete solution for interface IP. There was a digital controller, an analog PHY and verification IP (VIP). Over time this completely changed the market and all their competitors needed to do the same or get out of the business. Customers wanted to buy the complete solution. More recently they upped the ante again by launching their IP Accelerated initiative and adding software development kits, and prototyping kits and interface IP subsystems. It turns out that having SoC experts from the customer company along with IP experts from Synopsys is a powerful mixture. Although the IP may be standard, each chip is different in terms of power domains, power management, clcoks, which options of the IP are not required and so on.

In 2010 Synopsys bought Virage Logic bringing them standard cell libraries, memories (with test and repair) and the ARC microprocessor. This meant that they could, as Emeril used to say, kick it up a notch to IP subsystems, pre-integrated suites of IP including software, microprocessor, interfaces and more. The first was an audio subsystem. Then a complete sensor and control IP subsystem. At DAC this year they announced they were working with TSMC on a 40nm IoT platform. They also announced that they were pushing their IP portfolio up to automotive grade, with features to address functional safety, reliability and quality management. To qualify for automotive it requires a lot more than just slapping an “automotive” label on existing IP. At the same time they are optimizing IP for IoT applications in 45ULP and 55nm but very low voltage.

They are not done acquiring. In just the last couple of weeks they announced the acquisition of Bluetooth IP (for wireless interface) and security IP with Elliptic Technology.

The combination of interfaces, Bluetooth, security, the ARC microprocessor, memories, data converters and more gives them the broadest set of IP for IoT of anyone in the market.

There is clearly a major transition from making IP internally to buying it. It is getting so much more difficult to make, for a start. USB 2.0 to USB 3.0 has a verification requirement that is 20 times bigger. Standards turn fast, every couple of years. USB 3 to USB 3.1. DDR to LPDDR4. PCIe 3.0 to PCIe 4.0. And so on. Not many companies can keep up. They often don’t have the knowledge even if they would be willing to spend the time and the money.

Going back to 2010, when Virage was acquired, Synopsys made a couple of other key acquisitions in the system design space: VaST (where I used to be VP marketing) and CoWare. They had previously acquired Virtio. This gave them a lot of virtual platform technology. As I discovered when I had worked at VaST (and subsequently Virtutech) there is a big problem with modeling: it takes too long, costs too much and is hard to keep synchronized with the RTL. But Synopsys has three weapons that we never had: they have a lot of their own IP so they can provide TLM models, they have an emulator family ZeBu, and they have an HAPS FPGA-based prototyping system. This gives them the capability to do all sorts of hybrid solutions with processors and perhaps interfaces running as virtual models, combined with RTL running in HAPS or ZeBu. This makes it possible to look at functionality and performance, but especially these days power. Plus they have PlatformArchitect (ex CoWare) which allows for analyzing and optimizing architecture very early using TLMs, processor subsystems, DDR interfaces and more. Synopsys also now provide virtualizer design kits (VDKs) especially for some automotive MCUs and for ARM subsystems. By prepackaging everything it makes it easy for the software engineers to use the solutions immediately at low cost.

HAPS has also been very successful and leads the market. The HAPS FPGA-based prototyping solution allows high speed prototyping of SoC designs for software development, hardware/software integration and system validation. They have an optimized FPGA synthesis solution for HAPS (ProtoCompiler) that understands all the partitioning giving the highest performance for a design along with fast prototyping bringup.

At Synopsys, the prototyping business has started to be quite successful—both virtual and FPGA-based. The market for FPGA and virtual prototyping seems to be about $450M but only 1/3 is in the commercial marketplace, and 2/3 is internally developed. This means there is a big $300M potential market available if people switch from make to buy, the same problem as IP used to have a decade ago.

IP is already close to 20% of Synopsys’ business and the prototyping segment is a big opportunity. The future’s so bright you’ve got to wear shades.

August 3, 2015

Good Morning Vietnam

Good Morning Vietnam
by Paul McLellan on 08-03-2015 at 7:00 am
Categories: eSilicon, General, Semiconductor Services

This morning I went to a presentation in Palo Alto about outsourcing in Vietnam. You have probably heard that Vietnam is the new China for manufacturing, as wages have increased in the Shenzhen area then companies like Foxconn have opened plants in Vietnam. But this meeting was mostly about services, software and design. In this area, perhaps Vietnam is the new India. The meeting was organized by VNITO the Vietnam Information Technology Outsourcing Organization.

The main presentation was by Hung Ngyen of LogiGear who do software testing, especially for the videogame industry. Somewhat confusingly there was a second Hung Ngyen from Microchip. Everyone seemed to have been at high school with Tom Quan of TSMC! The numbers for Vietnam are impressive: it is often ranked #1 emerging market location based on business conditions, risk and cost. Ho Chi Minh City (HCMC, the old Saigon) and Hanoi are in the top 20 outsourcing cities. It is not even on the radar yet for these types of studies, but Da Nang is an up and coming hub investing billions in infrastructure. For engineering graduates, Vietnam is in the top 10 countries. Perhaps more to the point, the talent pool is likely to continue to outstrip demand for years meaning that companies that move there now can pick from the top 10-20% of graduates. The deep pool also means that outsourcing organizations are very scalable, start small and grow.

It is a young country. LogiGear’s local manager is about 30, and the team of around 800 people is split roughly 50:50 male and female. It seems that intracompany marriage is pretty common and, unlike in the US, is even encouraged. The speakers all figures that they were building the first layer of a middle class in the country. It is not insignificant. There are 100K software engineers in Vietnam and about 50K other digital content providers (web designers, graphic designers for video games etc).

The three big worries people have about outsourcing to Asia are:

cultural fit
language
IP protection

Cultural fit turns out to be surprisingly good. Presenting companies pointed out that it is a proud culture which means that people there are prepared to push back when, for example, a product is not ready for release. EA’s experience in Canada and Argentina was less successful than in Vietnam, where engineers will follow processes but not completely blindly. American companies seem to have no problem working closely with their Vietnam teams.

English is similar to China. Hung tried to claim that English was as good in Vietnam as India since they talk too fast with too strong an accent there. But the educated classes in India speak English since not everyone speaks any other language, they are all to some extent local. Plus their studies were all in English too.

As to IP protection, the risk is objectively much lower since there is no market for stolen IP in Vietnam in the same was as there is in China. Nobody seemed to have had any problems. They also don’t have a culture of pirating the software that they use.

In the semiconductor world, Intel is there. Samsung has just recently picked Vietnam. Renasas has operations there. But one company I knew about was eSilicon. I talked to Deepak Sabharwai, the VP Engineering for IP which is mostly in Vietnam. In fact most of eSilicon is in Vietnam. Out of 500 people in the company, 300 are there at two sites, HCMC and Da Nang.

eSilicon got into Vietnam when they acquired Silicon Design Systems. They focus on memory design since they want to have a good selection of differentiated IP, to separate them from their competition, but not so much that they are competing with their customers. Since memory is regularly half the real-estate on a chip it makes sense to specialize in that to have both standard IP and deep knowledge to create custom memories too. They also do custom ASIC design work there. They have around 250 people working on design.

They also do all their software Q/A there, with another 50 people. The team has done a great job of creating and automating the tests for both the customer-facing STAR suite and the enterprise software that they use internally to run the company. Software engineers can be hired from school but for memory design they hire smart graduates and train them internally. And they train them to a high standard, doing 14/16nm FinFET memories for example.

Deepak confirmed what the breakfast meeting had said. Cultural fit was good, the senior people speak good English but not everyone speaks so well. And they have all their IP development over there so don’t consider IP theft a major risk. Deepak, who worked for Cadence in india, said he felt Vietnam is now where India was 15+ years ago.

If you are seriously interested in considering operations in Vietnam, then there is a 3 day conference Vietnam, an Emerging Destination for IT Outsourcing from 14th to 17th October. There will be IT outsourcing companies, multinationals, technical universities and more. The conference will be held in The Reverie Saigon at Times Square in HCMC Vietnam. Details are here.

August 2, 2015

Semiconductor Mergers – Innovation or Consolidation?

Semiconductor Mergers – Innovation or Consolidation?
by Pawan Fangaria on 08-02-2015 at 8:00 pm
Categories: EDA, Foundries, General, IoT, IP

About 3 years ago, I had written an article about consolidation in the semiconductor landscape where I had articulated 4 main reasons of consolidation – Macroeconomics, Business Leadership, Technology Leadership, and IP leadership. Back then, based on the state of affairs in the semiconductor industry, I had also mentioned about my perceived notion that more mergers & acquisitions would be happening in near future. Today, we are s Continue reading “Semiconductor Mergers – Innovation or Consolidation?”

August 2, 2015March 24, 2022

Talking Directly to EDA R&D

Talking Directly to EDA R&D
by Daniel Payne on 08-02-2015 at 12:00 pm
Categories: Dassault Systemes, EDA

Many EDA companies keep their R&D engineers focused on product development and bug fixing, shielding them from any and all direct contact with end-users, mostly for fear of what might be revealed if such direct dialog were allowed. Customer support people are allowed to talk directly with customers, then pass along enhancement requests or file bug reports to R&D. Another way is for product marketing and technical marketing folks to talk with EDA users and uncover new product requirements, then report to R&D what they’ve heard about possible roadmap features. Direct conversations between EDA tool users and EDA R&D engineers is kind of rare, however it can be quite beneficial to both parties as there is no intermediate filtering of ideas, design challenges, likes and dislikes.

I was actually kind of surprised to learn that Dassault Systemes is having a two day user meeting in September and October where the second day is fully dedicated to EDA users talking directly with EDA R&D engineers to actually share their user experience, have roundtable discussions, discuss product roadmaps, describe how they actually use the tools, and explain what they really want to see in the next release of software. This kind of direct interaction between users and developers is a wonderful approach that keeps a company like Dassault in tune with what’s really happening, and able to plan and respond accordingly.

As a quick recap, Dassault has introduced the Silicon Thinking Experience which offers four solution areas for SoC design teams that provide a business platform allowing Design, Product and Manufacturing engineering to work together:

Design Collaboration using DesignSync and Pinpoint
Requirements driven verification
Enterprise-level IP management
Manufacturing Collaboration

DesignSync has been used since 1998 to help SoC teams manage both the hardware and software content in their electronic products. Designers can share their hierarchical design to all team members, even across the globe during their collaboration of design and verification.

The Pinpoint tool came from Tuscany Design Automation, and was acquired by Dassault in late 2012, it provides a dashboard with info for both the front-end and back-end IC design flows, helping you to reach design closure quicker.

Knowing if your system design implementation actually meets the original requirements is important for success, so having a methodology that supports requirements driven verification is essential. Ad-hoc verification just isn’t sufficient for a complex electronic product today.

How you manage the hundreds of IP blocks on a single SoC can be a critical success factor, so using a proven system will help reduce risks, enable IP reuse, eliminate duplication of IP and track issues and defects through multiple projects.

Also Read

A Systems Company Update from #52DAC

Design Collaboration, Requirements and IP Management at #52DAC

Managing Semiconductor IP

August 2, 2015June 14, 2019

Addressing Moore’s Law with the First Law of Real Estate: Location, location, location

Addressing Moore’s Law with the First Law of Real Estate: Location, location, location
by Beth Martin on 08-02-2015 at 7:00 am
Categories: EDA, Siemens EDA

Design sizes and complexities have grown exponentially (it’s a Law!), and consequentially the task of silicon test has become proportionally more expensive. The cost of testing a device is proportional to the amount of test data that is applied, and therefore the time it takes, which in turn is proportional to both design size and the number of defect types that need to be covered.

ATPG (automatic test pattern generation) had to become much more efficient in order for test costs to remain economical. It became painfully clear by the year 2000 that within a decade, it would cost more to test each transistor than to manufacture it. Figure 1 shows the cost/transistor trend of manufacturing and test.

This powerful need for more economical test drove the development of ATPG compression technology. While the amount of compression has improved over the years, new factors like more complex design structures and the need to cover more advanced fault types like Cell-Aware faults are driving the need for compression levels beyond what is typically achievable even with the most advanced compression solutions.

I talked to Steve Pateras, product marketing director for Mentor Graphics Silicon Test Solutions, about an extremely promising new approach to reducing ATPG pattern volume using a novel type of test point technology. Pateras said that the reduction in ATPG pattern volume when these EDT (embedded deterministic test) test points are inserted into the design depends on the number of test points used and the design characteristics, but empirical results have shown significant reductions, typically in the 2X to 4X range. Combining the use of these test points with ATPG compression can therefore improve overall compression levels from a typical 100X to as much 400X or more. This level of test pattern reduction results in real time and cost savings, and is a compelling value proposition.

About ATPG Compression

But first, some background. With ATPG compression, on-chip circuitry is added to intercept and decompress test patterns before streaming into the device’s scan chains. Only the compressed test data is stored on the external tester and applied to chip pins (Figure 2).

On-chip logic is also added on the output of the scan chains to compact the test responses before unloading back to the tester. ATPG compression reduces both test data volume and test application time. You want to reduce data volume to limit ATE memory requirements and related costs. In particular, you want to ensure that all test patterns can fit into the tester’s existing memory, since it’s expensive to reload the tester with additional patterns at each device insertion. Reducing test time is important too because test time is directly correlated to test cost per device. Leading edge ATPG compression technology can generally achieve 100X compression.

Despite these drastic ATPG improvements over the years, test pattern volumes continue to increase along with the increasing design sizes. The challenge is to reduce test pattern volumes without losing test quality. This is where EDT test points come in.

About EDT Test Points
Here is how Pateras explained test points to me: Test points consist of local modifications to the netlist designed to increase the controllability or observability of a given net. Test points have been used for years in conjunction with logic BIST to reduce the number of random patterns needed to achieve an acceptable level of fault coverage. The test points were inserted in locations that would maximize the random pattern testability of the circuit under test.

EDT Test Points consist of the same local modifications, but the similarity with logic BIST test points ends there. Just like in real estate, Pateras said, location is absolutely everything. The test geniuses at Mentor developed an innovative selection algorithm to choose the location of test points that would maximize deterministic pattern reduction.

ATPG software models a fault in the logic, then traces a path back to the input to control the data to simulate the fault, then propagates the effects of the fault to an output. By adding test points at strategic locations, the pattern generation becomes more efficient, runs faster and creates fewer patterns. To insert test points, Mentor’s software (Tessent ScanPro) analyzes the netlist, either before or after scan insertion, and determines the optimum number and locations for test point insertion. The rest of the ATPG flow, shown in Figure 3, remains unchanged.

I asked Pateras what effect the insertion of test points has on timing and power. It is generally limited, he said, because physical synthesis should optimize away any timing impacts. However, to mitigate any impact on timing closure, he said critical paths extracted from static timing analysis can be excluded from test point insertion. The number of control points added to a single path can also be limited. The overall number of control versus observe points can also be controlled to favor the more timing-neutral observe points if necessary.

Empirical Results
The EDT Test Point technology has been used in many designs so Mentor has a large amount of empirical data. The amount of pattern reduction you get is, in general, proportional to the number of EDT Test Points added to the design. This trade-off is illustrated in Table 1. Even a small number of EDT Test Points, say only 0.15% area overhead, will typically provide an almost 2X pattern reduction.

You can read more about EDT Test Points in this Mentor whitepaper.

July 31, 2015

SSD Storage Chips: Basic Interconnect Considerations

SSD Storage Chips: Basic Interconnect Considerations
by Majeed Ahmad on 07-31-2015 at 4:00 pm
Categories: Arteris, EDA

The joint development of 3D XPoint memory technology from Intel and Micron has once more brought the spotlight on data centers and chips for solid-state drives (SSDs). The two semiconductor industry giants claim that 3D XPoint memory is1,000 times faster than NAND Flash: the underlying memory content for SSDs. Such developments underscore the tectonic shift in the IT industry from HDDs to SSDs.

There is an inevitable switch from rotary storage to solid-state storage, and here, controller chips for SSDs are far more complex to develop than controller chips for HDDs. Then, there are design intricacies related to Flash memory that add to the complexity of an SSD controller chip. According Kurt Shuler, Vice President of Marketing at Arteris Inc., Flash is like a helicopter. It destroys itself as it is operating.

That’s especially true in the case of an enterprise SSD controller chip in which the “mother” controller talks to multiple “daughter” controllers, which are attached to specific banks of Flash. Unlike a consumer SSD, which maxes out at 1 TB, the controller chip-based enterprise storage devices scale to 10 TB and beyond.

SSD marks an inflection point as data centers move away from HDD storage

The SSD controller chips use a cascading slices approach to accommodate more storage because enterprise SSD solutions need to be highly scalable. That leads to the use of more IP block functions than the most complicated application processor designs. Not surprisingly, therefore, the huge chip size and design complexity are a major consideration for chipmakers offering the SSD controller system-on-chip (SoC) solutions.

SSD Design Challenges

Arteris’ Shuler says that data protection is the number one design goal for storage chips. Data protection ensures that there is no data loss by detecting errors and correcting them. It’s extremely important because the enterprise SSD companies know that they have to offer the same reliability as HDD even though they are using an inherently self-eating technology like Flash.

“Data protection can add data bits and logic for error-correcting code (ECC) and hardware duplication,” Shuler said. “In fact, the ECC engine is often the largest IP block on the die.” But it’s these interconnect reliability features that help make Flash a possibility in a market that so far has been ruled by HDD.

The high-level design of an enterprise SSD chip

Second, storage chips also boast extremely complex power management and dynamic voltage frequency scaling (DVFS). Power consumption is the biggest concern in data centers where low-power functioning is required for both compute and air conditioning operations. Around 33 percent of data center power is used for cooling.

Third, there are different quality-of-service (QoS) requirements for storage chips. The SSD chips are of huge size, and they require more bandwidth-balancing QoS schemes than the DRAM-centric end-to-end QoS schemes that are used in mobile application processors. Moreover, there are a number of clock domain crossing and clock propagation and balancing issues.

Interconnect Spaghetti in Storage Chips

Enterprise SSD chip architectures are even more complex power-wise than, for instance, the TI CC26xx IoT chip design that the Dallas, Texas–based semiconductor supplier has recently announced. There are more independent engines on an enterprise SSD controller than there are in a smartphone application processor, and the connections between them can overwhelm the layout team with a tangled mess of metal line spaghetti.

Here, a specialized interconnect technology like FlexNoC enables fewer wires and less logic as well as distributed interconnect design. That helps chip designers avoid routing congestion and the resulting timing closure problems the enterprise SSD industry struggles with while using older interconnect technologies like ARM’s NIC-400.

Let’s take the core design issue of data protection as an example of how the effective use of interconnect technology can drastically enhance the scalability of enterprise SSD system requirements. The storage chips are so big, and the interconnects are so complex that they have to be protected. An SoC interconnect implements ECC, parity and hardware duplication to protect data paths in a storage chip.

Shuler claims that Arteris’ FlexNoC Resilience Package creates more physical awareness earlier in the chip design process and facilitates data protection in tasks such as ECC, parity, hardware duplication and BIST. “The FlexNoC interconnect IP automatically ensures data safety when dealing with asynchronous clock domains and power domains.”

Clock tree power and unit-level clock gating in a storage SoC interconnect

Next up, let’s see how the low-latency requirement is balanced with extremely high bandwidth in data centers as an example to highlight the critical importance of interconnect in large and powerful storage chips. The ultra-low latency factor is especially crucial because of the communication to and from ARM Cortex-R5 low latency peripheral port (LLPP).

There are a lot of challenges in implementing this communication in the ARM world because of the ARM AMBA AXI 4 KB restriction per transaction. On the other hand, enterprise SSD chips require huge block transfers in their logical block addressing (LBA) schemes. “The FlexNoC interconnect IP bridges the gap between ARM architecture and enterprise SSD controller architecture,” Shuler said.

I want to use USB Type C (and I want it now)

I want to use USB Type C (and I want it now)
by Eric Esteve on 07-31-2015 at 12:00 pm
Categories: IP, Synopsys

USB is certainly the most ubiquitous of the Interface protocols, used in our day to day life to connect multiple systems, as well as in professional segments like industrial or even high performance servers (yes, these systems integrates USB 3 connections). But USB is also one of the protocols able to generate frustration every day. I am not talking about strong frustration, just one of the small issues we are facing several time a day when plugging USB connector the wrong way! Then we think that it shouldn’t be rocket science to define a reversible connector, that you can plug it either way…but we will see that it requires high level engineering skills.

This magic connector has been finally defined by USB-IF, it’s the Type-C connector and I was told by Synopsys that the Type-C specification is the fastest adopted USB specification of all time: it took only 7 months between the spec and the product release. If you consider that we have waited 20 years to benefit from a reversible connector, fulminating against this #%&@ connector, this fast adoption make sense.

IPnest delivering the “Interface IP Survey” every year since 2009, I know that Synopsys is the undisputed leader on the USB IP segment, but I didn’t knew about the cumulated number of USB IP projects won by Synopsys: almost 3,500 since 1995. As the clear leader on this USB IP segment, Synopsys had to position as quickly as possible to support USB-C IP.

USB-C connector has to be reversible. Which is easy to use and to understand has a pretty strong impact on the USB IP itself, as the USB PHY is concerned. If you are familiar with interface IP, you know that it can be split into a pure digital block, the controller, and a mixed-signal part, the PHY. Because the PHY is mixed-signal, it’s 100% process dependent. In other words, it’s almost impossible to support all foundries and all process nodes and the multiple variations for a process node (LP, HPM, etc.) immediately. Synopsys has started by the most challenging, the USB-C 3.1 PHY running at 10 Gbps designed on 14/16 nm FinFET technology node, targeting the high end market (Application Processor for Mobile, Tablets or Laptop), as well as the mainstream with USB-C PHY IP supporting 3.0 and 2.0 designed on 14/16 nm FinFET and 28 nm Bulk technology nodes. That’s why you can see two different USB-C PHY IP on the picture below. Redesigning these PHY IP has been the opportunity for Synopsys to optimize it for area, so it counts up to 40% less pin, leading to a smaller footprint.

As I have previously mentioned, the Type-C connector impact the USB PHY. If you want to implement USB-C, you will have to implement the controller too. Thus you will expect Synopsys to have validated the interoperability of the USB 3.1 controller (supporting also 2.0 and 1.1 for backward compatibility) with these new PHY IP. Such work being done internally, the next step for the company was to validate the interoperability of the complete USB-C solution during the USB-IF plug-fest (compliance program) in July 2015, were you can verify that your solution is compliant and interoperable.

It’s crucial for a Synopsys customer that the USB-C IP has passed the compliance test, but it may also be very important to benefit from USB 3.1 Verification IP (to validate the proper integration of the IP into the SoC) and comprehensive Prototyping Kit (below) to allow as early as possible software development, in parallel with the SoC integration. Important to mention, Synopsys customers can use their existing USB 3.0 drivers to support the new USB 3.1 controller IP, this controller has been built on the existing USB 3.0 controller.

Synopsys is launching the first USB Type-C IP solutions supporting USB 3.1, 3.0 and 2.0 specifications, built on USB PHY IP proven in literally 100’s of customer designs. Last point, but not least: USB Type-C has been specified to deliver power up to 100 Watts!! Clearly USB Type-C PHY IP design has to be robust, on top of running at 10 Gbps.

From Eric Esteve from IPNEST

July 31, 2015April 10, 2025

Silvaco 30 Years Ago

Silvaco 30 Years Ago
by admin on 07-31-2015 at 7:00 am
Categories: EDA

It’s Silvaco’s 30 year anniversary. You may already know the dry official story of the early days:

Founded in 1984 by Dr Ivan Pesic
In 1984 the initial product, Utmost, quickly became the industry standard for parameter extraction, device characterization and modeling.
In 1985 Silvaco entered the SPICE circuit simulation market with SmartSpice.
In 1987 Silvaco entered into the Technology Computer Aided Design (TCAD) market. By 1992 Silvaco became the dominant TCAD supplier with the Athena process simulator and Atlas device simulator.

I decided to get a bit more color so I sat down with Misha Temkin to find out how he joined Silvaco and what it was like in the early days nearly 30 years ago. He is an atomic physicist and did his PhD in Russia (actually still USSR) on ion implantation, modeling and atomic interaction. He published his work in a book in Russian and in 1986 it was translated into English which got him noticed.

Misha moved to the US in 1988 as a Jewish regugee and set about trying to find a job. Then in one of those alignment of the planets he saw an ad in the San Jose Mercury wanting an engineer knowledgeable in process simulation and SUPREM. It didn’t say who the company was. He sent his resume but heard nothing for 6 weeks until one morning, at 6am, he gets a call. It was Ivan, the founder of Silvaco. “I want you to work for me,” he said. He started work that Monday without even having negotiated a salary. He only found out what he was being paid when he got his first paycheck. He was the first TCAD person at Silvaco. The whole company was Ivan and about 8 or 9 engineers.

Silvaco actually started by doing parameter extraction for SPICE with Utmost (still sold today). Ivan’s previous employer had been HP who sold parameter extraction along with their equipment. But the other equipment companies had nothing similar and smaller companies could not afford HP. Ivan sold the product himself, flying all over the world. But he realized it was too small a market on its own and decided that TCAD would be a good complement.

In those days DARPA and Intel and some other industrial partners were funding TCAD work at Stanford that ended up being SUPREM and being licensed by TMA (who were acquired by Avant! and now form the heart of Synopsys’ TCAD offering). Ivan wanted to license it. But Stanford wouldn’t license it unless Silvaco had true expertise. After all, it was student code with inadequate documentation, only batch mode, no graphics. That was why Ivan hired Misha. “Here’s a guy, he did it all before but in Russia.” Eventually they got a license and started selling. In 1989, the first year, they sold 5 or 6 copies and Misha’s group grew to 5 or 6 people.

Ivan had a good nose for smart people. He could not compete with much larger richer companies to hire people from Stanford but he found people in Russia, Bulgaria, Brits, French, Asians. For 30 years the company has been more or less profitable. The only investment was from the family. As Ivan told Misha one day “we had to sell a couple of houses.” Now the family owns most of the park where Silvaco is based although they only occupy 6 of the 26 buildings.

Ivan liked to sell direct. By 1989 they already had an employee in Japan. They have been direct for a long time in both Korea and Singapore and are likely to soon go direct in China. It has been a wild ride. Silvaco was 8 people when Misha started and is now 180 people. TCAD is mostly here in Santa Clara with the mesh stuff done in the UK.

One memorable event was the SPICE billboard controversy on 101, about the only type of marketing that Ivan liked to undertake. Even CNN came by the office to, basically, complain. But it all helped to put Silvaco on the map.

You probably know the dry version of the sad recent history:

In October 2012, after an extensive battle, Dr Pesic succumbed to cancer.

But Silvaco lives on with a new management team. Ownership of Silvaco remains in the Pesic family, with Dr. Pesic’s son, Iliya Pesic as Executive Chairman of the Board, and Dave Dutton as CEO. Misha is still here 26 years later.

30 year anniversary video (2 minutes):