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TSMC Shows 10nm Wafer!

TSMC Shows 10nm Wafer!
by Daniel Nenni on 06-08-2015 at 4:00 pm

If you really want to know why I write about TSMC it is all about ego, my massive ego, absolutely. Blogs about TSMC and the foundries have always driven the most traffic and they most likely always will. Semiconductor IP is second, Semiconductor Design is third, and I don’t think that is going to change anytime soon:

SemiWiki BI: Daniel Nenni: TSMC: All
Total Blogs: 137
Total Views: 878600
Average: 6413

SemiWiki BI: Semiconductor IP: All
Total Blogs: 431
Total Views: 1641911
Average: 3810

SemiWiki BI: Semiconductor Design: All
Total Blogs: 1367
Total Views: 4157039
Average: 3041


TSMC came to the Design Automation Conference 16 years ago ushering in a new level of collaboration amongst the fabless semiconductor ecosystem. Other foundries have followed and one could argue that they are the center of the DAC universe. In that time TSMC has completed 15 reference flows (the latest being 10nm) with 7,500+ tech files, 200+ PDKS, and more than 8,600 silicon proven IP titles from .35u to 10nm.

Today, the first day of #52DAC, my prediction of a big crowd has come true. This year the big foundry buzz is around 10nm. TSMC is showing a 10nm wafer for the first time and everybody is wondering if in fact 10nm will arrive in 2016 like promised. I certainly believe it will and so does the majority of the fabless semiconductor ecosystem.

Let’s take a quick look at the TSMC process node revenue start history just for fun:

[LIST=1]

  • .35u 1996
  • .25u 1998
  • .18u 2000
  • .13u 2002
  • 90nm 2005
  • 65nm 2007
  • 40nm 2009
  • 28nm 2011
  • 20nm 2014
  • 16nm 2015
  • 10nm 2016
  • 7nm 2017

    Seriously, we are doing four new process nodes in four years? The fabless semiconductor ecosystem is truly an amazing thing. In regards to process ramp challenges, I remember .13u being very difficult because of the new copper interconnect. 40nm was certainly not easy. 40nm was the last node where TSMC gave you the option of using recommended (yield centric) design rules. Which one of these nodes was the most challenging? You tell me. If you have a design horror story please share it in the comments section and I will give you a free Kindle version of “Fabless: The Transformation of the Semiconductor Industry“.

    TSMC has the Open Innovation Platform Theater again this year in booth #1933. You can see the schedule HERE.The other TSMC related #52DAC activities are HERE:

    TSMC’s booth is jam packed, probably because they are giving away iWatches and other cool stuff. TSMC also had some interesting IoT press today, one even mentioning 10nm:

    Imagination and TSMC collaborate on advanced IoT IP platforms
    Imagination Technologies (IMG.L) and TSMC announce a collaboration to develop a series of advanced IP subsystems for the Internet of Things (IoT) to accelerate time to market and simplify the design process for mutual customers. These IP platforms, complemented by highly optimized reference design flows, bring together the breadth of Imagination’s IP with TSMC’s advanced process technologies from 55nm down to 10nm…

    Cadence Announces Collaboration with TSMC on IoT IP Subsystem
    Cadence Design Systems, Inc. (NASDAQ: CDNS), today announced that it is collaborating with TSMC on the development of an Internet of Things (IoT) intellectual property (IP) subsystem demonstration platform for TSMC’s ultra-low power (ULP) process. Targeting wearable, home automation, always-on and industrial control applications, this IP subsystem, with the support of the Cadence suite of digital and custom/analog tools, provides the opportunity to simplify IoT designs and accelerate the time to market for mutual customers…

    Synopsys and TSMC Collaborate to Develop Integrated IoT Platform for TSMC 40-nm Ultra-Low-Power Process
    Synopsys, Inc. (Nasdaq:SNPS) today announced a collaboration with TSMC to develop an integrated Internet of Things (IoT) platform on TSMC’s 40-nm ultra-low-power (ULP) process technology. The IoT platform incorporates a broad range of DesignWare® IP, including an integrated sensor and control IP subsystem with the ultra-low-power ARC® EM5D processor core, power-and area-optimized logic libraries, memory compilers, NVM, MIPI and USB interfaces as well as an analog-to-digital converter (ADC). The high-performance, low-power IoT platform provides designers with a pre-validated solution that enables them to deliver the energy-efficient, always-on processing required for applications such as sensor fusion and voice recognition…


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