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DAC Keynote: Moore’s Law Isn’t Dead

DAC Keynote: Moore’s Law Isn’t Dead
by Paul McLellan on 06-10-2015 at 5:00 am

 There were two keynotes at DAC this morning. I think the official designation of the first one was a “visionary talk” and the main difference was that it was only 15 minutes long. Vivek Singh, an Intel fellow, talked about Moore’s Law at 50: No End in Sight.

He started with a graph showing transistor speed versus leakage which is as good a measure as any of how good a transistor is. When it is on we want it to switch fast and have good drive, when it is off we want it to consume no power at all.

For now things are on-track. Haswell is 960M transistors in 22nm, but Broadwell is in 14nm and 1.3B transistors, an increase of 35%. From 22nm to 14nm the metal pitch decreased from 80nm to 52nm, a reduction of 0.65x which is slightly ahead of Moore’s Law.

The end of Moore’s Law has been predicted for years. Vivek had a few of the comments that have been made over the years (decades even):

  • optical lithography will reach its limits in the range of 0.75um
  • minimum geometries will saturate around 0.5um
  • X-ray lithography will be needed below 1um
  • minimum gate-oxide thickness is limited to about 2nm
  • copper interconnect will never work
  • scaling will end in about 10 years

As he pointed out, things look no different in 2015 (although the precise details of what people worry about have changed, obviously).


For me the big question has always been whether the cost per transistor reduces. After all, Moore’s Law was always an economic law, namely that the cost per transistor is minimized in a given process technology at a certain number of transistors, and that number seemed to increase by a factor of 2 every 2 years (or 18 months depending on which version of Moore’s Law you look at). Intel have always claimed that their cost per transistor continues to decrease in a way that they feel is not happening for their competitors.

Cynics might point out that since Intel manufactures at such high margins, it has never been under pressure to have a competitive wafer price and so it can keep transistor counts decreasing in a way that is not available (or less available) to foundries that have to manufacture chips that are competitive at much lower margins for the mobile industry in particular. As if Rolls-Royce pointed out that they could make cheaper cars if they had to in a way that Ford, say, would find hard.


Vivek’s speciality is in lithography. A simplified view of a stepper has a light source, a mask, some focusing, and a wafer. You probably know that we have not been able to get a light source with a smaller wavelength that 193nm. EUV is the big hope but it is always a few more years out. So we have had to use increasingly complicated optical proximity correction (OPC) to ensure that what we put on the mask produces what we want on the wafer, adding little corners to stop rounding, adding extra bars to stop necking, and so on. But even that has reached its limit and going forward we need to use inverse lithography.

Inverse lithography means starting from the geometry that we want to print and working out what patterns we need on the mask and what light source we need, to get it. This is computationally very expensive but Intel, handily, is in the business of decreasing the cost of computation (I believe Moore’s Law might apply here!).

So for now the innovation continues. 14nm is in full production, 10nm is on track, and 7nm is in research. Vivek is confident Moore’s Law will continue. For the most leading edge designs for the foreseeable future, I’m sure he is right. Whether the cost of computation will continue to fall fast remains to be seen. After all, twice is many cores is roughly twice as many transistors and if the cost per transistor remains flat(tish) then the cost doesn’t come down as you add cores every couple of years.


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