SemiWiki – Page 719 – The Open Forum for Semiconductor Professionals

August 30, 2015July 18, 2025

Simulating to a fault in automotive and more

Simulating to a fault in automotive and more
by Don Dingee on 08-30-2015 at 12:00 pm
Categories: Automotive, EDA, Synopsys

We’re putting the finishing touches on Chapter 9 of our upcoming book on ARM processors in mobile, this chapter looking at the evolution of Qualcomm. One of the things that made Qualcomm go was their innovative use of digital simulation. First, simulation proved out the Viterbi decoder (which Viterbi wasn’t convinced had a lot of practical value at first) prior to the principals forming Linkabit, then it proved out enhancements to CDMA technology (which was working in satellite programs) before Qualcomm launched into mobile. Continue reading “Simulating to a fault in automotive and more”

August 30, 2015

4 Design Tips for AVB in Car Infotainment

4 Design Tips for AVB in Car Infotainment
by Majeed Ahmad on 08-30-2015 at 7:00 am
Categories: EDA, IoT

Audio Video Bridging (AVB) is a well-established standard for in-car infotainment, and there is a significant amount of activity for specifying and developing AVB solutions in vehicles. The primary use case for AVB is interconnecting all devices in a vehicle’s infotainment system. That includes the head unit, rear-seat entertainment systems, telematics unit, amplifier, central audio processor, and rear-, side- and front-view cameras.

The fact that these units are all interconnected with a common, standards-based technology that is certified by an independent market group—AVnu—is a brand new step for the automotive OEMs. The AVnu Alliance facilitates a certified networking ecosystem for AVB products built into the Ethernet networking standard.

AVB is an established technology for in-car infotainment

According to Gordon Bechtel, CTO, Media Systems, Harman Connected Services, AVB is clearly the choice of several automotive OEMs. His group at Harman develops core AVB stacks that can be ported into car infotainment products. Bechtel says that AVB is a big area of focus for Harman.

AVB Design Considerations

Harman uses Atmel’s SAM V71 microcontrollers as communications co-processors to work on the same circuit board with larger Linux-based application processors. The design firm writes codes for customized reference platforms that automotive OEMs need to go beyond the common reference platforms.

Based on his experience of automotive infotainment systems, Bechtel has outlined the following AVB design do’s and don’t’s for the automotive products:

1) Sub-microsecond accuracy: Every AVB element on the network is hooked to the same accurate clock. The Ethernet hardware should feature a time stand to ensure packet arrival in the right order. Here, Bechtel mentioned Atmel’s SAM V71 microcontroller that boasts screen registers to ensure advanced hardware filtering of inbound packets for routing to correct receive-end queues.

2) Low latency: There is a lot of data involved in AVB, both in terms of bit rate and packet rate. AVB allows low latency through reservations for traffic, which in turn, facilitate faster packet transfer for higher priority data. Design engineers should carefully shape the data to avoid packet bottlenecks as well as data overflow.

Bechtel once more pointed to Atmel’s SAM V71 microcontrollers that provide two priority queues with credit-based shaper (CBS) support that allows the hardware-based traffic shaping compliant with 802.1Qav (FQTSS) specifications for AVB.

Gordon Bechtel: V71 MCU has a number of capabilities that directly aid in efficient AVB support

3) 1588 Timestamp unit: It’s a protocol for correct and accurate 802.1 AS (gPTP) support as required by AVB for precision clock synchronization. The IEEE 802.1 AS carries out time synchronization and is synonymous with generalized Precision Time Protocol or gPTP.

Timestamp compare unit and a large number of precision timer counters are key for the synchronization needed in AVB for listener presentations times and talker transmissions rates as well as for media clock recovery.

4) Tightly coupled memory (TCM): It’s a configurable high-performance memory access system to allow zero-wait CPU access to data and instruction memory blocks. A careful use of TCM enables much more efficient data transfer, which is especially important for AVB class A streams.

It’s worth noting that MCUs based on ARM Cortex-M7 architecture have added the TCM capability for fast and deterministic code execution. TCM is a key enabler in running audio and video streams in a controlled and timely manner.

AVB and Cortex-M7 MCUs

The Cortex-M7 is a high-performance core with almost double the power efficiency of the older Cortex-M4. It features a 6-stage superscalar pipeline with branch prediction—while the M4 has a 3-stage pipeline. Bechtel of Harman acknowledged that M7 features equate to more highly optimized code execution, which is important for Class A audio implementations with lower power consumption.

Again, Bechtel referred to Atmel’s SAM V71 microcontrollers—which are based on the Cortex-M7 architecture—as particularly well suited for the smaller ECUs. ” Rear-view cameras and power amplifiers are good examples where the V71 microcontroller would be a good fit,” he said. “Moreover, the V71 MCUs can meet the quick startup requirements needed by automotive OEMs.”

Atmel’s V71 is an M7 chip for Ethernet AVB networking and audio processing

The infotainment connectivity is based on Ethernet, and most of the time, the main processor does not integrate Ethernet AVB. So the M7 microcontrollers like V71 bring this feature to the main processor. For the head unit, it drives the face plate, and for the telematics control, it contains the modem to make calls, so echo cancellation is a must, for whom DSP capability is required.

For instance, take audio amplifier, which receives a specific audio format that has to be converted, filtered, modulated to match the requirement for each specific speaker in the car. So, infotainment system designers will need both Ethernet and DSP capability at the same time, which Cortex-M7 based chips like V71 provide at low power and low cost.

IoT and OTP are Like Peanut Butter and Jelly!

IoT and OTP are Like Peanut Butter and Jelly!
by Daniel Nenni on 08-29-2015 at 7:00 am
Categories: IP, Sidense

Have you ever had a peanut butter and bacon sandwich? Everything goes better with bacon! Which brings me to one of my favorite sayings: “(insert two complimentary things) go together like peanut butter and jelly”. How about this: “low power and IoT”, “IoT and OTP”, and “Low Power OTP and Sidense go together like peanut butter and jelly!”

Programmable memory started with PROMs in the 1950s and moved to antifuse one time programmable memory in the late 1960s. Texas Instruments brought OTP to MOS technology in the 1970s, Kilopass brought OTP to CMOS in 2001, and in 2005 Sidense introduced a low power split channel antifuse device. A Split Channel bit cell combines the thick and thin gate oxide devices into one transistor (1T) with a common polysilicon gate. That little history lesson was more for me than you by the way since I have not worked with non-volatile memory (NVM) since the Virage Logic days.

During my recent worldly travels FinFETs were all the rage but it was repeatedly mentioned that 14nm and more importantly 10nm is “challenging” for both EDA tools and semiconductor IP. This time it was not just “will our design yield?” which is always a concern, but it was also “will our IP work?” Getting the answers to those and other modern semiconductor design questions is of course the whole point behind the TSMC Open Innovation Platform Ecosystem Forumto be held this year on September 17[SUP]th[/SUP] at the Santa Clara Convention Center. Remember, TSMC has completed 15 reference flows with 7,500+ tech files, 200+ PDKS, and more than 8,600 silicon proven IP titles from .35u to 10nm. If you have EDA or IP questions this is the place to be, absolutely.

Back to OTP, one of the first TSMC IOP partner presentations is by Sidense R&D Director, Betina Hold, and is titled:

Ultra Low Power OTP Design for Smart Connected Universe Applications

Betina has spent the majority of her 25+ year career at ARM so she knows low power. Here is the abstract:

Sidense innovative low-voltage Non-Volatile Memory (NVM) designs targeting TSMC Ultra Low Power (ULP) and FinFET process nodes enable a wide range of Smart Connected ICs, spanning several key market segments including IoT, mobile computing, wearable technology, automotive, industrial and medical.

Smart Connected applications need embedded NVM to meet stringent power and reliability requirements. These requirements often include operation from low-voltage battery sources, extended battery life, and operation in safety-critical and/or harsh environmental conditions, and high reliability and extended temperature range are necessary attributes.

This presentation will discuss how the latest OTP IP developments from Sidense address these demands with innovative designs and a 3D 1T-OTP bit cell developed for the most advanced TSMC process nodes.

Along with the low-power properties of Sidense’s patented antifuse-based 1T-OTP bit cell, Betina will also discuss how the right macro design can result in low read voltages along with low power, critical attributes for many Smart Connected applications. She will also cover double-fin FinFET design which has shown significantly lower leakage current, higher programmed cell current, and very high read margin compared to 28nm/20nm bulk CMOS.

I hope to see you there!

August 28, 2015June 14, 2019

Why You Really Need Chip-Package Co-analysis

Why You Really Need Chip-Package Co-analysis
by Daniel Payne on 08-28-2015 at 12:00 pm
Categories: Ansys, Inc., EDA

There’s only one software company that I know of that covers four major disciplines: Fluids, Structures, Electronics and Systems. That company is ANSYS and when they acquired Apache Design Automation back in 2011 they filled out their products for electronics design, and more specifically in the area of integrated chip-package co-analysis. I just reviewed a presentation from ANSYS given at DAC back in June titled, Achieving Faster Power Design Closure with Integrated Chip-Package Co-analysis. The historic approach in EDA was to have separate tools for the IC designer, package designer and PCB designer, leading to silos of data that didn’t easily talk to each other, let alone do any co-analysis. Apache saw the opportunity and basically created a new category of EDA tool to support integrated chip-package co-analysis.

The actual co-analysis is for the Power Delivery Network (PDN) and thermal across the IC and Package domains combined. The premise is that at the IC level you cannot simplify and assume an ideal package for PDN and thermal, because you would be missing the interactions between IC and package, leading to under-design and failed silicon. Having to re-spin silicon is simply too expensive today, so having a co-analysis for PDN and thermal across IC and Package during the design phase helps ensure first silicon success.

At ANSYS the software tool used for power closure is called RedHawk and it provides quite a wide range of checks for power noise and reliability:

With the ANSYS approach you create both a chip model and a package model for PDN and thermal co-analysis. This then allows a designer to do a package-aware chip simulation, plus a chip-aware package optimization:

The benefits of this co-analysis are many:

Measuring the package impact on IC
Knowing the IC impact on package
The IC and package can be co-designed, instead of separately design, in less time
System level transient analysis
System AC impedance
System resonance is known
System decap requirements can be validated and optimized

If you ran a transient analysis on your IC and didn’t include package modeling, then the simulated results would look much better than what silicon reported. Here’s a quick comparison of transient analysis for an IC without package models and with package models:

The hot-spots shown on the right where the package models are included while doing transient analysis on the IC clearly show that you must do co-analysis including both IC and package models to get accurate results. When you run IC and Package co-analysis it provides:

Support for IR drop, DvD (Dynamic Voltage Drop) and Power-up analysis
DC-IR static analysis of the package
AC-hotspot analysis of the package

Likewise, by adding package modeling during SoC analysis you get:

3D full-wave accuracy
Chip/Package connection is automatically specified
Modeling of the power and ground supplies independently
Per-bump resolution granularity

Consider what happens if you assume that all your power or ground package bumps are lumped together versus modeled as independent, per-bump. With a lumped approach the bump voltage is only 13.8mV, however with the per-bump model you get a more accurate worst-case of 19.2mV.

Summary

Divide and conquer is an approach that no longer works with IC and Package design, so today you should consider using a co-analysis approach to get the most accurate results. ANSYS has been around the longest time in our industry, engineering software tools like RedHawk that support a chip-package co-analysis flow.

August 28, 2015

Strategic Materials

Strategic Materials
by Paul McLellan on 08-28-2015 at 7:00 am
Categories: ESD Alliance, Semiconductor Services

Here on SemiWiki we spend a certain amount of time discussing semiconductor equipment, especially the big sea-change items like EUV and 450mm, where everyone wants to know when (and if) they will happen. But there is another aspect to next generation processes other than equipment and that is materials. When the received wisdom is that Hafnium is important for transistors going forward, there need to be people whose reaction is not “Hafnium, great name for a heavy metal band” but how do we get it, how do we make it pure, how do we deliver it to fabs on multiple continents. If it is something that is required in large quantities, such as many gases, then the supply chain is even more complicated. In fact, the reality is that process advances depend on material innovation as well as equipment innovation.

On September 22nd-23rd at the Computer History Museum it is the annual SEMI Strategic Materials Conference (SMC). This year’s theme, Materials for a Smart and Interconnected World, will take a broad look at what is driving the demand for new materials, how material suppliers are being impacted by the value chain they serve and how this affects the smart and interconnected world we live in.

The opening keynote on Tuesday morning is by Garry Patton. He was the head of R&D at IBM Semiconductor but he decided to come over with the acquisition and is now the CTO and head of R&D for GlobalFoundries. His topic is The Importance of Accelerating Material Innovation. I always enjoy Gary’s keynotes since he has a deep technical knowledge but an ability to talk about technology in ways that are accessible to more than the deep specialists.

Gary is followed by Mark Thirsk of Lynx Consulting.

The rest of the morning is taken up with the Economics/Material Trends session.Market forces that drive demand for semiconductor process materials not only involves the influence / demand from chip fabricators, but also involves end use applications, largely influenced by consumer demand, locally and globally. The semiconductor business environment will be presented from various vantage points – from the materials perspective through chip fabricator, to the global economic view point. Information on materials and business trends for a broad range of semiconductor device technologies, and the driving forces behind these trends, will be presented.

In the afternoon it is a session on Material Enabling Silicon Everywhere. That’s material speak for IoT!Critical to the IoT vision is the interconnection of tens or hundreds of billions of systems that will supply information for analysis and action. These devices will combine existing and novel capabilities such as new types of sensors, low-power operation, energy harvesting, and interconnectivity to mobile or fixed wire communications. Many of these devices will build off well-known technologies, but “More than Moore” integration will likely be necessary to fulfill the vision. This session of SMC 2015 will review the process material requirements and device manufacturing implications of distributing IC-based devices to all aspects of our lives.

From 5-7pm there will be a reception.

The next day, 23rd, has 3 major sessions:

New Emerging Materials Technology and Opportunities at the Edge
Sustainable Manufacturing: Sustainability Considerations of Advanced Materials
Advanced Interconnect Technologies

Finally, A View from the Fabs: Executive Panel Session. This consists of three short executive presentations followed by a panel session moderated by Kurt Carlsen of Air Liquide Electronics. The three executives are:

Vin Menon of Texas Instruments
Hans Stork of ON Semiconductor
Gary Patten (our keynoter from the day before) of GlobalFoundries

The conference wraps up at 5pm.

Full details of SMC are on the SEMI website here. Registration is discounted until September 11th.

August 27, 2015

Moore’s law observations and the analysis for year 2019.

Moore’s law observations and the analysis for year 2019.
by Vaibbhav Taraate on 08-27-2015 at 4:00 pm
Categories: EDA, Foundries

As semiconductor professionals we all are familiar with Moore’s law. Respected Gordon Moore during year 1965-1975 observed and stated that, number of transistors in dense Integrated Circuit has doubled for approximately two years. In the present scenario, if we consider the complexity of Integrated Circuit and if we use the mathematical analysis with the fundamentals of Physics and relativity theory then for the shrinking process node, the law can be stated as ” Below 14 nm, the number of transistors in dense Integrated Circuit has to be doubled for approximately 32 months.” May be true till year 2019, the reasons are many, the exponential logic depth and computational efficiency, low power issues and need, on chip variation issues, latency, constraints at system level, parallelism, noise margins, crosstalk etc.

It is my observation and analysis in the past couple of years that at lower process nodes the real limitation is due to material properties, atomic spacing and the transfer of data due to the fabrication related issues. The technology shift can happen with the evolution of the process flow in the design of Integrated Circuits due to the issues related with the shrinking process node and the requirements of the analytical, mathematical and numerical modeling at the system, architecture and even at the design levels. .

At the engineering level the real bottleneck is the specification complexity, implementation and validation of the design at the system level. Even the practical limitation for the shrinking is the CAP theorem. According to CAP theorem, ” It is impossible for any computer system to simultaneously provide the consistency, partition tolerance and availability. “So there is limitation for the computing efficiency of the SOCs at the system architecture levels.

But the real limitation for shrinkage and computing performance is due to the space , energy, time issues. If we try to perceive the relativity theory of Einstein; then there is the limitation of the traveling particle with the speed of light. The carrier mobility due to the issues of the dielectric constants, conductivity of the material is the real limitation for the information transfer between the carriers. Another important limitation at the shrinking process node is the physical integration, synchronization to achieve the parallelism with high computational efficiency.

Another important limitations at device level are : aging, leakage, interfaces and contacts size and delay variations. So the real challenging phase for the semiconductor professionals is below 10nm process node.The real era of miniaturization can face challenges at 8 nm process node and there may be the evolution of design and process flow.

Probably during year 2019 one can expect the modified Moore’s law observation with the technological shift and changes in the design and manufacturing processes, where the number of transistors in dense integrated has to be doubled for approximately 36 to 38 months and may continue for almost one decade after 2019.

Although there are limitations, still we all are intelligent to design, innovate the complex SOCs. Let us hope for the great era of miniaturization!

August 27, 2015

Last line of defense for IoT security

Last line of defense for IoT security
by Don Dingee on 08-27-2015 at 12:00 pm
Categories: IoT, IP, Security, Sonics

If I grab 10 technologists and ask what are the most important issues surrounding the Internet of Things today, one of the popular answers will be “security.” If I then ask them what IoT security means, I probably get 10 different answers. Encryption. Transport protocols. Authentication. Keying. Firewalls. Secure boot. Over-the-air updates. Rogue apps. Data archival. Penetration testing. All the above. Continue reading “Last line of defense for IoT security”

August 27, 2015

Synopsys Did 90% of Business From Backlog with A Deal Length of 2.5 Years. Err…What Does That Mean?

Synopsys Did 90% of Business From Backlog with A Deal Length of 2.5 Years. Err…What Does That Mean?
by Paul McLellan on 08-27-2015 at 7:00 am
Categories: General

Here is Trac Pham, Synopsys CFO, from last weeks earnings call:Greater than 90% of Q3 revenue came from beginning of quarter backlog…the weighted average duration of our renewable customer license commitments was about 2.5 years, and we expect duration for the full year to be about 2.7 years.

What does that mean? Why does anyone care that much? Is that good or bad?

Renewable license means that the license is sold for a given period, usually 2 or 3 years, and then it needs to be renewed. Accounting principles (so called GAAP) force this to be recognized quarterly over the period. The whole order is entered into bookings and then every quarter, one twelfth of it (or whatever is appropriate for the term) is moved from bookings to revenue. From the EDA company’s point of view, this makes for a very predictable business. They enter each quarter with eleven twelfths of the term business already on the books waiting to be recognized, so a good or a bad quarter has much less of a yo-yo effect on the bottom line. Which Wall Street likes, since they don’t like surprises.

Perpetual licenses, on the other hand, are the old hardware business model from the days when EDA companies sold not just the software but the hardware on which to run it. The software is sold in perpetuity and a maintenance fee is paid annually or quarterly. Accounting principles force this revenue to be recognized immediately. Ship a $1M perpetual license on the last day of the quarter and that is $1M of revenue that quarter. There are actually other forms of non-renewable license, such as with a given period, but it is complicated enough already.

I think you can see the temptation. If you can switch a $10M license from a renewable license to a perpetual license then you can recognize it immediately. The customer gets a better deal for the same payment terms. It turns out that under those GAAP rules, whether a license is deemed to be recurring or not can swing on just a few words in the license agreement. That is why Wall Street analysts care about the ratios of license types and and why CFOs tell them every quarter. As long as renewable license percentages are not falling, it is good. Deals are not being switched quietly to non-renewable.

The other thing to watch out for is how long the contract lives are. If a company does a $100M deal for a 3 year renewable license, that is a lot less attractive than the same booking for a 4 year period, since in the first case it will drop to revenue at one twelfth per quarter, and in the second at one sixteenth. You can already hear the salesperson: “will you close today if I give you 4 years for the price of 3”.

It is not just Synopsys. Here’s Geoff Ribar, Cadence’s CFO, from last month’s call:We expect weighted average contract life in the range of 2.4 years to 2.6 years, and we expect at least 90% of the revenue for the year to be recurring in nature.

So both Cadence and Synopsys have a contract life of 10-11 quarters. Let’s say 10. If it was all recurring business then 90% should come from backlog with the remaining 10% or so coming from business booked that quarter. Except there are two wrinkles. Revenue recognition is actually done monthly, and in EDA a lot of business is booked in the last month of the quarter. So with a term of 30 months or so, then perhaps only 1/30 of new business will be recognized in the quarter being reported. If all the business were recurring and all new business was booked in the last month, then 29/30s of revenue should come from backlog, or nearly 97%. So there is actually room for a little non-recurring business in there and still clear the 90% threshold.

So the two things that the Wall Street analysts watch out for is recurring license percentage dropping, and the contract lives stretching out. Even if the company is meeting or even exceeding its bookings and revenue numbers, in reality the business is softening and it will show up in future quarters.

Here is the temptation. If a company was going to miss its number by, say, $10M, then they can take one of their $10M orders and make it perpetual. In fact, since perpetual licenses are worth more, the customer might pay even more than $10M, the numbers are even better. Or they can offer to give a customer who was going to place a very large order for a 3 year recurring license a deal for 4 years at only $10M more. In the first case the amount of revenue coming from backlog will decline (in the future), in the second case the contract life will lengthen.

When there was real indiscipline in the industry there were even more games played whereby companies that were already 2 years into a 3 year deal would get an offer to cancel the remaining 2 years and sign up for a new 3 year deal. Or 5. Or 6. At a huge discount, of course, and at the cost of creating a huge hole a few years out. If you sell a company what is essentially software to be used in 2 years’ time, then they won’t be buying any more in 2 years. The company is eating its seed corn. No hunger now, not so good next fall.

A company that does these sort of things to make their numbers is like someone who keeps opening new credit cards to pay the interest on the old ones. It works for a time. but eventually the wheels come off. There is a huge reset, management gets fired, the new management comes in, takes a huge writeoff, and promises never to do such a thing again and hopefully they never do. But when they have a weak quarter, the temptation is always there. Except these days Wall Street understands the model a lot better and so they insist on being told the data every quarter to make sure.

BTW I am not trying to imply that Synopsys, Cadence or anyone else would be playing these games but for the vigilance of Wall Street. I thought it was more interesting to take the actual comments from the most recent conference calls rather than just invent some dry numbers.

August 26, 2015June 14, 2019

Secret Sauce of SmartDV and its CEO’s Vision

Secret Sauce of SmartDV and its CEO’s Vision
by Pawan Fangaria on 08-26-2015 at 4:00 pm
Categories: IP, SmartDV

SmartDV started as a small setup in Bangalore in 2008 and by now is one of the most respectable VIP (Verification IP) companies in the world. Having a portfolio of 83 VIPs in its kitty and growing, it has a large customer base, including the top semiconductor companies around the world. The company has grown significantly and is raring to grow further. I had an opportunity to talk to Deepak Kumar Tala, Chairman of SmartDV Group of Companies and CEO atSmartDV. This provided further learning about the company’s strengths and philosophies that have played well in pushing the company to newer heights. Deepak also talked about VIP’s future and SmartDV’s vision in future. Here is our conversation –

Q: Deepak, post 2005, the concept of using standard VIPs for SoC verification was picking up. What made you envision the future in this area and become one of the early starters in 2008?

A: The SOCs are becoming complex with every passing month and the time spent on verification is increasing. With rapidly emerging new protocols, companies are finding it difficult to develop new protocol from scratch. Developing a new protocol requires building expertise in a new area. Looking at all these factors, it was clear to me that Verification IPs are going to be used in a big way, and if we could do it right with good quality and right price, we will be successful.

Q: From 2008 until now what were the key factors in transforming the semiconductor industry for such massive usage of VIPs in design verification? What were your company’s stakes and contributions in this transformation?

A: The consumer electronics is changing very fast, so do other sectors. More and more functionalities are being packed in every electronic gadget, creating the need for new protocols’ integration into these products. All companies do not have expertise in all protocols, hence the need for Verification IPs. We have been developing Verification IPs for all emerging technologies and have helped big companies in bringing up newer products in the market, faster. If you look at our portfolio of VIPs, we have covered almost all the protocols.

Q: Your internal language and compiler technology for developing VIPs is very effective and performance optimized. Was it a conscious choice to develop it first before VIP development or you learnt it while developing VIPs? Can you provide some specifics about it? Going forward, do you plan to add more optimizations in this technology?

A: We built the compiler technology as soon as we started our company; it took a few iterations before we stabilized the compiler. After stabilizing the compiler, we started building Verification IPs. With every major revision of the compile technology, we improved performance and also moved higher to reduce the amount of code to be written manually. From the very beginning we knew that developing a Verification IP manually can be an uphill task. So having compiler technology to automate the writing of VIPs was the key for aligning with our business strategy and gaining competitive advantage.

We have made a few major changes in our LRM and compiler so that we can move code from a VIP to an Emulator. Also with some little modifications, we can move the same code base for post silicon validation using FPGAs. These are some of the major enhancements happening in our compiler, right now.

Q: One of the key differentiating factors in your VIP offering is the delivery of a smart testbench with a comprehensive test suite with each VIP. Can you provide some specifics about how this provides higher efficiency and productivity in the customer environment?

A: Traditionally Verification IPs use BFM for generating traffic and checking protocols. The users have to write all testcases and functional coverage models. This was fine in good old days when sufficiently long time-to-market was available. But now the time-to-market window is very short, the requirement has shifted significantly; the users need to jump start their verification. The only way to enable the user to jump start the verification is by supplying a complete test solution along with each VIP. With our VIPs, we provide complete testsuite for each and every protocol, functional coverage models, testbench examples to allow testing of each and every feature, and very high quality documentation.

Q: How about the automated development of verification environment and testcases which incurs minimum cost in VIP development? Can you provide some details about this automation?

A: We have developed a language which is suited for writing verification environment and Verification IPs. BY using this language, we can write the code with higher level of abstraction and reuse. Due to this we are able to write the verification environment and testcases very fast.

Q: What enables you deliver a VIP for a new protocol in the shortest time after its release?

A: We can complete about 85% of a new protocol in a very short time due to our compiler technology and strong processes in place. As soon as we get a new specification in hand, we have a team of engineers who extract the features from the specification and create a testplan, the functional coverage requirements, and then finally break down the specification into blocks for which the code has to be developed. By using our compiler technology, we automate the development of code for each block. In a short duration of about a few days to a week, we normally can create a framework of a VIP up and running.

Q: In which direction do you see the VIP market heading in the near future? How would be the segmentation between commodity and premium?

A: As the complexities of SOCs increase, there is going to be more and more demand for complete VIPs. Also, engineering help from VIP companies for deployment of these VIPs will be needed. In such a scenario, a commodity type of model will be of no help to customers. A premium model where a VIP is delivered as a complete solution along with the engineering resources to help deployment and coverage closure will be desirable.

Q: How has been the business after opening of SmartDV’s new office in San Diego last year? What are the plans for expanding in other regions?

A: We have been maintaining a low profile, as we have been focusing in building quality VIPs and improving our compiler technology. Last year we felt the need of expanding our customer reach, so we started our new office in USA. With the new office in operation and close proximity with customers, we have been able to expand our reach within our existing customers and also find new customers. It was a key strategic decision to create awareness about SmartDV products & services, not only in North America but also in the worldwide semiconductor market. We have been able to communicate to our customers about our seriousness in VIP business and long term relationships with them. We will be further expanding our operations in Japan, Russia, South Korea, and Taiwan.

Q: What is your future vision about SmartDV into VIPs? Do you see another level of transformation in this area; for example customization against standardization?

A: We have been doing custom protocols for some time now; we also customize our existing VIPs to meet the needs of our specific customers. Due to our compiler technology, we can generate code which is specific to a specific customer. Most of the big companies have customization to standard protocols to get better performance or to suite their product needs.

Q: Do you envision any other area of focus in VIP or IP as such for your company?

A: We are getting into Simulation Acceleration, which is going to be the next level for simulation VIP. We are committed to deliver all our VIPs in SimXL platforms.

This was a very enriching conversation with Deepak. I see that the company has created a solid foundation in VIPs and is continuously improving to cover the verification space including emulation and post silicon validation through its innovative compiler technology. The company’s continued focus on providing complete VIP solutions, efficiently and faster, will go a long way in its future success.

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

August 26, 2015

GaN Technology — Contributing to Medicine in No Small Way

GaN Technology — Contributing to Medicine in No Small Way
by Alex Lidow on 08-26-2015 at 12:00 pm
Categories: EDA

In past posts, the disruptive nature of gallium nitride (#GaN) semiconductor technology, especially eGaN® FETs, was discussed…now with significantly higher performance at an equivalent cost, the inevitability of GaN displacing the aging power MOSFET is becoming clearer.

This post highlights a specific end-use application that affects all of us – the contribution that #GaN technology is making in medical applications with enhanced patient mobility using wirelessly powered devices and improved diagnostics with higher resolution equipment.

Medical Applications: Introduction and Overview
Being untethered to the power cord not only makes life easier for patients and health workers, but also increases safety and allows health care to be administered faster and more efficiently. Imagine medical teams never having to plug in a power cart while rushing to save a life in an emergency room or having to worry about the tangle of wires that can interfere with the delivery of IV fluids.

From a patient’s point of view, think about eliminating the need to have infection-prone wires extending from the body to recharge the batteries for a heart pump. And, in the world of diagnostic procedures, just think about the impact of significantly increasing the resolution of scanning equipment such as sonograms and MRI, or the ability to swallow a miniaturized X-Ray machine embedded in a pill to perform a colonoscopy.

These improvements to the world of medicine are being enabled by gallium nitride technology. Let’s take a closer look.

At the Hospital – Untethered Emergency Carts, Unplugged Bedside Monitoring Instruments, and Untethered Patients
We are all familiar with the chaotic environment in which emergency medical personnel navigate at life-saving speed and can thus appreciate the advantage of having the equipment readily available without the need to “find power outlets” .

Even at a patient’s bedside, not having power cords will be welcomed – for ease of moving instruments, avoiding accidental unplugging of critical equipment, reducing the risk of electrical shock, and reducing the potential to breed bacteria. The emerging availability of wireless power transfer is making wireless medical carts and bedside stands a reality.

The advancement of wireless power transfer is an electronics industry-wide movement. Industry leaders including Hewlett Packard, Intel, Texas Instruments, Samsung, and Witricity have established a consortium (A4WP) for consumer and computing equipment. This technology is applicable to hospital environments, which is using frequencies at both 6.78 and 13.56 MHz. In addition to the convenience, wireless power will increase safety and reduce price by removing cable clutter around the patient.

On the Patient – Heart Pumps, Pacemakers, Muscle and Nerve Stimulators, and Electric Wheelchair Recharging
In addition to untethering the instrument carts in the emergency room, having #wirelesspower available enables patients to be more comfortable while bedridden and increases their freedom of movement when ambulatory.Likewise, if a patient is bound to an electric wheelchair, the need to recharge batteries can be accomplished with a “drive over” mat that will charge the battery without the need to plug in. As with electric vehicles, electric wheelchairs can recharge simply by rolling over a wirelessly coupled mat. This vehicle recharging technology is in operation today with drive-over chargers for electric cars and buses.

There are also numerous direct patient applications for wireless power transfer enabled by GaN technology. The figure at the top of this post illustrates some of the high-impact applications under development and in clinical trials. These applications involve heart pumps and nerve stimulators that do not require wires – wires that are prone to infection – protrude from the body in order to “plug in” for power. Wireless charging is not only more convenient, it is safer for the patient.

Diagnostics – MRI, Colonoscopy
Resolution is a critical attribute of all medical scanning devices, such as sonograms, CAT scans, and MRI imaging. Equipment manufacturers are very excited about using eGaN® FETs to increase the speed and precision with which they can conduct scanning measurements. In the case of MRI systems, eGaN® FETs are used in the transmit functions, which require extremely high RF power for both the power supply and power amplifier being constrained by heat. The small size and efficiency of eGaN® FETs allow the transmit function to be placed closer to the patient allowing effective higher power capability for faster imaging. This faster imaging can be taken as either more image slices in the same time for higher resolution, or shorter scan time for more efficient equipment usage.

The receive coils are placed in direct contact with the patient and are limited by heat. Replacing silicon-based components with eGaN® FETs to detune these coils for the transmit phase and tune them for the receive phase yields a drastic reduction in power dissipation, allowing a higher density receive matrix. This provides more information in the same space for higher resolution images. Thus, medical professionals will have more accurate images and a patient’s care will benefit with improved diagnosis.

Perhaps the most innovative medical application enabled by the extremely small size of the eGaN® FETs is the “colonoscopy pill”. This pill contains a miniature X-ray machine that, after ingestion (no pre-purging needed!), creates a 3-D image of the intestinal track as it passes through the patient’s digestive system.

The scanned images are transmitted wirelessly to a receiving unit placed on the patient. Once the pill has passed through the patient’s system, physicians can analyze the digital information stored on the receiving unit. Imagine, no more discomforting overnight preparation for the traditional colonoscopy! This “pill” and procedure is the result of EPC’s customer Check Cap, and is currently undergoing European agency trials and is on track for final evaluation by 2016.
In no small way, eGaN® FETs are contributing to changing the cost curve of medicine.

Summary: GaN Technology for Medical Applications
The world of semiconductors is undergoing a technological disruption and medical applications that take advantage of high performance eGaN® power transistors and integrated circuits are emerging rapidly. In this post, applications improving the quality of medical care were presented:

Untethering the all-important “medical cart” containing emergency instruments to make movement of the cart less of a contributor to bacterial infestations, as well as faster and easier to address patients.
Removal of the necessity to have infection-prone “wires” protruding from a patient’s body because they are needed to power heart pumps, or nerve stimulators.
Increase in the resolution of body scanning devices, such as MRI equipment, giving more accurate information about the condition of patients at a lower cost.
Introduction of new diagnostic procedures, such as the “colonoscopy pill,” giving doctors more precise critical information, while easing medical procedures for the patient and reducing costs.

#GaN technology is contributing to significant improvements in medicine. Taking an even broader view, gallium nitride is displacing silicon as the fundamental material used for power conversion with the promise to displace silicon not just in power transistors, but in analog and digital integrated circuits as well. EPC is pursuing this $350B semiconductor market, and the reason is simple, #GaN technology is faster, smaller and, now, price competitive with MOSFETs…

Why wouldn’t this huge market be worth attacking with this disruptive technology?

Also read:

GaN Technology for the Connected Car

Four Things a New Semiconductor Technology Must Have to be Disruptive