Japan has had an incredible run in technology, but the past decade has seen a reversal of fortune. Consumer electronics powerhouses such as Pioneer, Panasonic, Sharp and many others have been humbled by the commoditization of their hardware and a shift in market share to Asian competitors.
Continue reading “Japan Inc. on the Brink”
I was driving recently on highway 87 (San Jose) and wanted to merge left. I checked my side-mirror, checked the blind-spot detector, saw no problems and started to move over – and quickly swerved back when a car shot by on my left. What went wrong? My blind-spot detection, a primary feature in ADAS (advanced driver assistance systems, the advance guard for autonomy), told me all was good.
Then I remembered. My fairly new (3-year old) car actually told me the previous day that blind-spot detection was shutting down, which it does from time to time (more frequently now, it seems). The system eventually recovers but I have to re-enable the feature manually, a trial-and-error process since there is no corresponding message that it is again good to go. In the intervening period, I forgot the feature was disabled. Meantime, my subconscious mind slips into default mode and assumes that safety features are working. Silly subconscious.
This hair-raising incident reminded me of a recent Consumer Reports survey on auto reliability, in which owners of first year models flagged twice the level complaints on in-car electronics as owners of models with no major changes. This isn’t a temporary glitch, nor is it sustainable. A few years ago, my boss (at that time), a fan of high-end luxury cars, switched from his 7-series BMW lease to a Mercedes because his BMW had so many problems, again in the high-end electronics. Not good news for brand loyalty (I should add that this is not just a BMW problem). At less lofty heights, all that fancy electronics comes in expensive option packages. I paid $5,000 for the package which provided blind-spot detection. I’ll think harder about doing that on my next car, especially since those features are typically warrantied for only 2 years.
Scale this up for an autonomous car, critically depending on the correct operation of considerably more electronics. I am sure that, excepting a lemon or two, when these roll off the assembly line, they will live up to advertised capabilities. But one, two, three years later? That outlook is not so promising. The sad fact is that the long-term reliability we should expect for auto electronics doesn’t just naturally and painlessly emerge under market pressure. It takes special focus in design and testing and particularly it takes long proving times.
Before we became fascinated with advanced auto electronics, we already had very capable but largely invisible electronics in our cars, managing anti-lock braking, fuel injection and other features. This was built around micro-controllers, sensors and networks, which you might view as the entry-level smarts in earlier models. However, it famously took 5 years or more for a new device to be qualified to enter such a system because the auto-makers wanted to minimize liability and recall risks. I don’t remember us having a lot of problems with auto electronics back then.
Now we have ADAS, infotainment, self-parking and ultimately autonomy, we seem to have thrown caution to the winds, at least in our expectations. I understand the battle for mindshare among automakers (and others), but looming reliability problems mean we really aren’t ready for autonomous car releases in 2020. What happens when a problem pops up in such a car? Worst case, it crashes. Better, it pulls over and stops, but how excited are you going to be when your few-year-old self-driving car does this on the way to an important meeting, or a critical doctor appointment or to pick up a child from school (and should we expect to see rows of disabled autonomous cars along the side of highways)? Better still, every year a car has a costly service (possibly under a costly warranty) to diagnose and replace suspect components. None of these options is appealing.
The danger is that what has started out as a very promising direction – for us consumers, the automakers and the builders of systems of ADAS and autonomy-support systems – may unravel in disillusion over unreliability, to the point where we and investors begin to walk away. Do we really want all of this promise to turn into a bubble?
It doesn’t have to be this way. We know how to build reliable electronics for those invisible systems in the car, for spacecraft beyond the reach of repair and for many other applications. We need to dial up our expectations on reliability and lifetime testing and dial down our consumer thirst for regular mind-blowing advances. When it comes to safety, we can’t have both (and sorry but ISO 26262, at least today, doesn’t address this problem).
You might want to check out ANSYS. They have a big focus on analyzing reliability in electronic design and an especially interesting focus on analyzing the effects of aging on reliability. Pretty relevant to this topic.
I say finally because it was a long time coming… almost ten years to be exact. I started doing business development work for both Solido and Berkeley Design Automation about ten years ago and have been trying to put them together ever since. The synergy was obvious, like peanut butter and jelly. In fact, this is my third time being acquired by Mentor (Tanner EDA, Berkeley Design Automation, and now Solido) and I think there are more to come and I will tell you why.
(My alltime favorite Solido graphic)
The significance of this acquisition is twofold: Clearly Siemens continues to invest in EDA and Solido gives Mentor an inside advantage in the AMS fight against Cadence and Synopsys.
When Siemens bought Mentor in 2016 there were some doubters, including myself, that were not convinced Siemens had good intentions when it came to the IC design part of Mentor. A chat with Chuck Grindstaff (Executive Chairman of Siemens PLM Software) at DAC convinced me otherwise but other doubters still linger. Well linger no more, Mentor (a Siemens Business) is clearly in EDA to win EDA, absolutely.
Solido CEO Amit Gupta will report to Ravi Subramanian, vice president and general manager of Mentor’s IC Verification Solutions Division. Ravi was the CEO of Berkeley Design Automation and has been steadily rising through the ranks of Mentor. Having traveled with both Amit and Ravi I can tell you that they were very involved CEO’s with more customer experience than any other EDA CEO I have worked with. Solido will stay intact in Saskatoon, in fact I would be surprised if Mentor didn’t expand there since the cost of operations is much lower than Silicon Valley or even Wilsonville.
Solido has become an invaluable partner helping our customers address the impact of variability to improve IC performance, power, area, and yield,” said Amit Gupta, founder, president and CEO of Solido Design Automation.” Combining our technology portfolio with Mentor’s outstanding IC capabilities and market reach will allow us to provide world-class solutions to the semiconductor industry on an even larger scale. We are also excited to contribute to Siemen’s broader digitalization strategy with our applied machine learning for engineering technology portfolio and expertise.”
“The combination of Solido and Mentor’s leading analog-mixed-signal circuit verification products creates the industry’s most powerful portfolio of solutions for addressing today’s IC circuit verification challenges”, said Ravi Subramanian, vice president and general manager of Mentor’s IC verification solutions division. “Solido joins Mentor at an exciting time. Having a power house like Siemens entering EDA is proving to be a true game changer for us.”
And before you ask how much Mentor paid for Solido please remember that I am under Solido NDA so my lips are uncharacteristically sealed. I can tell you this, however, Mentor wasn’t the only one interested in Solido but clearly Mentor (a Siemens Business) is now bigger than all of the other EDA vendors combined so EDA acquisitions is a whole different ball game, and yes there will be more so stay tuned to SemiWiki because we actually know stuff.
Why is this bad news for Synopsys and Cadence? Having spent ten years in the trenches with Solido I can tell you that the Variation Designer software is a critical part of the foundation IP verification flow and that will open many doors for Mentor. If you look at the Solido customer base you will see not only the top semiconductor companies (including he who must not be named) but also the foundries, which I can tell you from personal experience is where electronics REALLY begins. The same goes for Solido, they now have the Siemens worldwide reach.
Another interesting note, Solido has always been SPICE simulator agnostic and I’m sure they will continue to be but there will definitely be a Mentor SPICE bias and some secret simulator sauce is sure to be baked in there sometime soon, my opinion.
Bottom line: One of my favorite acquisition catchphrases is a “1+1=3” valuation. In this case it is more like 1+1=5.
Production of electronic equipment is continuing healthy growth. China, the world’s largest producer of electronics, had a three-month-average increase of 14% in October 2017 versus a year ago. Year-to-date through October, China’s electronic production has gained 13.8% compared to 10.0% for the year 2016, putting China on track for the highest annual growth in six years. U.S. three-month-average electronics production in September 2017 increased 4.1% from a year ago. Year-to-date, U.S. electronics production is up 5%, the strongest growth in 11 years. The European Union (EU) does not release electronics production numbers, but overall EU three-month-average industrial production was up 4.2% in September versus a year ago, the highest rate in over six years.
The significance of China, the U.S. and the EU in global electronics is shown by electronics exports and imports. Year 2016 data from the United Nations Comtrade database pegs China’s electronic exports at $544 billion in 2016, accounting for 32% of global electronics exports. The EU accounted for 23% and the U.S. was 8%. The EU was the largest importer of electronics in 2016, accounting for 23%. The EU was followed by China at 20% and the U.S. at 17%. Other Asia in the trade data below consists of Singapore, South Korea, Taiwan, Japan and Malaysia. These countries accounted for 26% of electronics exports and equaled the U.S. with 17% of imports.
China leads all major Asian nations in electronics production gains with September year-to-date growth of 13.9%, up from 10% for year 2016. Thailand has bounced back strongly, with a September year-to-date electronic export increase of 13% compared to a 3% decline in 2016. Vietnam continues to be a significant emerging electronics producer, with September year-to-date up 12%, slowing from a robust 16% in 2016. India’s electronics production was up 9% year-to-date, an improvement from 2% in 2016. Long-time electronics producing countries in Asia are lagging the growth rate of the emerging countries. Year-to-date South Korea was up 3%, Malaysia was up 2.5% and Japan was up 1.8%. Japan electronics production in 2017 is headed toward is first annual positive change since 2006, eleven years ago. Taiwan is continuing declining electronics production, down 5.6% year-to-date.
The global semiconductor market is headed for 2017 growth close to 20%. Our Semiconductor Intelligence September forecast was 18.5%. Although much of the increase is due to rising memory prices, it is a good sign that solid gains in electronics production are also supporting the semiconductor market surge.
One of the more exciting design start market segments that we track is Artificial Intelligence related ASICs. With NVIDIA making billions upon billions of dollars repurposing GPUs as AI engines in the cloud, the Application Specific Integrated Circuit business was sure to follow. Google now has its Tensor Processing Unit, Intel has its Nervana chip (they acquired Nervana), and a new start-up Groq (former Google TPU people) will have a chip out early next year. The billion dollar question is: Who is really behind the implementations of these AI chips? If you look at the LinkedIn profiles you will know for sure who it isn’t.
The answer of course is the ASIC business model and TSMC.
Case in point: eSilicon Tapes Out Deep Learning ASIC
The press release is really about FinFETs, custom IP, and advanced 2.5D packaging but the big mystery here is: Who is the chip for? Notice the quotes are all about packaging and IP because TSMC and eSilicon cannot reveal customers:
“This design pushed the technology envelope and contains many firsts for eSilicon,” said Ajay Lalwani, vice president, global manufacturing operations at eSilicon. “It is one of the industry’s largest chips and 2.5D packages, and eSilicon’s first production device utilizing TSMC’s 2.5D CoWoS packaging technology.”
“TSMC’s CoWoS packaging technology is targeted for the kind of demanding deep learning applications addressed by this design,” said Dr. BJ Woo, TSMC Vice President of Business Development. “This advanced packaging solution enables the high-performance and integration needed to achieve eSilicon’s design goals.”
From what I understand, all of the chips mentioned above were taped-out by ASIC companies and manufactured at TSMC. It will be interesting to see what happens to the Nervana silicon now that they are owned by Intel. As we all now know, moving silicon from TSMC to Intel is much easier said than done.
The CEO of Nervana is Naveen Rao, a very high visibility semiconductor executive. Naveen started his career as a design and verification engineer before switching to a PhD in Neuroscience and co-founding Nervana in 2014. Intel purchased Nervana two years later for $400M and Naveen now leads AI products at Intel and has published some very interesting blogs on being acquired and what the future holds for Nervana.
You should also check out the LA Times article on Naveen:
Intel wiped out in mobile. Can this guy help it catch the AI wave?
Rao sees a way to surpass Nvidia with chips designed not for computer games, but specifically for neural networks. He’ll have to integrate them into the rest of Intel’s business. Artificial intelligence chips won’t work on their own. For a time, they’ll be tied into Intel’s CPUs at cloud data centers around the world, where Intel CPUs still dominate — often in concert with Nvidia chips…
Groq is even more interesting since 8 of the first 10 members of the Google TPU team are founders, which is the ultimate chip “do over” scenario, unless of course Google lawyers come after you. If you don’t know what Groq means check the Urban Dictionary. I already know because I was referred to as Groq after starting SemiWiki, but not in a good way.
If you check the Groq website you will get this stealthy screenshot:
But if you Google Groq + Semiconductor you will get quite a bit of information so stealthy they are not. The big ASIC tip-off here is that while at Google they taped out their first TPU in just over a year and the Groq chip will be out in less than two years with only $10M in funding.
So please, let’s all give a round of applause to the ASIC business model and give credit where credit is due, absolutely.
Also Read:
One of the biggest misconceptions is thinking cybersecurity is only about technology. When in fact, people and their behaviors, play a prominent role in almost every aspect of protecting digital assets. Without proper consideration for the human element, security strategies are destined to fail miserably.
In this Week’s Video Blog I cover some of the aspects, history, and recommendations for better perspectives to improve security planning by embracing the human factors.
Cybersecurity cannot be achieved with just technical controls. Technology and people are two sides of the same coin and must be handled together. A strong anti-malware suite is meaningless if the end-user disables it so they can install a new piece of desired software. The best network firewall is ineffective if the user bypasses it by bringing in a USB drive to directly connect to systems. The strongest password is pointless if users fall for phishing scams and give it to attackers. The best software code eventually becomes exploitable if it is not engineered by the designers to be patched when new vulnerabilities are discovered.
Then there are the attackers. Behind every network intrusion, spam email, ransomware campaign, and denial-of-service attack is a real person. It may be technology that executes the acts, but it is a human who is initiating and coordinating it. Attackers are driven by motivations that manifest into objectives. These are then pursued by whatever methods are at the attackers’ disposal.
A cyber-criminal is typically motivated by personal financial gain. Therefore, they seek to obtain monetary assets through theft, fraud, extortion, or other means. They target, like the famed bank robber Willie Sutton, ‘where the money is” and will follow the path-of-least-resistance to obtain their objectives. These factors determine targets and drive behaviors which may result in phishing, ransomware, network breaches, fraudulent sites, malware, or many other technical possibilities. If one fails, they move on to another. If a method is successful, they refine it and press further for more gain.
Predominant View
I have found most people in cybersecurity are narrowly focused only on the technical aspects and largely ignore the behavioral side of the equation. This is a grievous mistake. Perhaps they are not comfortable with understanding the behavioral perspectives or believe that by simply closing all the vulnerabilities, security will magically be fixed. Regardless, most initially feel that technology can overcome people’s bad decisions, poor behaviors, and malicious intent. They are wrong.
Those who are not security savvy, fail to see that technology is just a tool. Those tools are wielded by people, for their purposes and sometimes in unexpected or mistaken ways. Therefore, there will always be significant gaps in security if both technology and behaviors are not addressed simultaneously.
Weak Security Strategy
Cybersecurity plans that only focus on system patching, firewall rules, access control lists, and passwords are immature for today’s challenges. It is no longer enough. Training of users, developers, operations, and even customers is very important. We must not rely on uneven perimeter defenses. Security must be woven throughout the system to be truly effective, both from a cost and risk perspective.
Advice
Embrace both sides of the equation, both technical and behavioral. Don’t be blindsided by only looking at cybersecurity through a technology lens. Although tech is hugely important, so is comprehending the behavioral aspects of people, from attacker to victim, involved in the ecosystem.Understanding both technology and behavioral controls will help close significant gaps in risk mitigation efforts.
More Cybersecurity Misconceptions videos can be found at the Information Security Strategy YouTube channel.
Interested in more? Follow me on LinkedIn, Twitter (@Matt_Rosenquist), YouTube, Information Security Strategy, and Steemit to hear insights and what is going on in cybersecurity.
We are fortunate to be living in one of the most amazing and exciting times in the history of our planet. The developments seen in my life time alone have been astounding and we are now on the cusp of yet another inflection point. The world wide web has morphed into the internet of things (IoT), some even call it the internet-of-everything and it has the potential to touch every aspect of our lives. Companies like Arm have written about the march to One Trillion IoT devices and lest we think that’s crazy, we already reached the point where there are more connected devices on the planet than people, and that happened almost 10 year ago!
With that in mind, Dan Nenni and I set out to write an e-book about the IoT phenomenon, and more specifically its disruptive nature and how system companies are using IoT opportunities along with the ASIC business model to get into the chip business. The book is entitled, “Custom SoCs for IoT: Simplified” and it is an attempt to give the reader a high-altitude fly over of how the IoT market and opportunities are evolving and how it impacts chip designers hoping to cash in on the opportunities that abound.
The book is a quick read covering a large breadth of material including IoT markets and applications and the associated IoT system architectures that map to those markets. IoT security and how it translates into hardware solutions is addressed along with discussions on trade-offs between discreet IC implementations and solutions that seek to integrate system functions onto a single chip. Other covered topics include power optimization at different levels of the IoT system architecture as well as different communications protocols and standards used by IoT devices based on the amounts of data to be transferred and the distance to be traversed.
Covered in more detail is a case study of a highly successful approach to custom SoC design for an IoT gateway SoC using Open-Silicon’s Spec2Chip turnkey solutions. The case study covers platform-based design methodologies now being employed to mitigate designer risks and accelerate design cycles needed for rapidly changing IoT markets. The case study dives into state-of-the-art design flows and methodologies including sophisticated high-level architectural synthesis, hardware / software co-design with FPGA-based prototype boards, RTL synthesis, placement & routing of digital logic, design-for-test, design-for-manufacturing, SoC packaging including systems-in-a-package (SiPs), and hardware verification boards used to bring-up chips once they have come back from manufacturing.
As said earlier, we are fortunate to be living in one of the most amazing and exciting times in the history of our planet and the good news is that we are just at the beginning. The IoT is being merged with an explosion of progress in the fields of artificial intelligence and virtual reality, which should in fact enable many of the autonomous systems-of-systems described in the book. This too, will be a stepping stone to even more aggressive technologies that are already being developed in research labs. As an example, silicon photonics is at the cusp of becoming a mainstream technology that will enable much of the 5G cellular network that will truly make the IoT ubiquitous.
The lessons learned, and the platform-based methodologies used by companies like Open-Silicon will be key to enabling companies both large and small to manage the complexities of IoT designs and to move the state-of-the-art forward. Give the book a read. It’s a free download and can be found here:
http://www.open-silicon.com/custom-socs-for-iot-simplified/.
Happy reading….
Mitch Heins
Cadence has recently announced two key design-in for their Vision DSP IP family: MediaTek’s Helio P30 integrates the Tensilica Vision P5 DSP and HiSilicon has selected the Cadence® Tensilica® Vision P6 DSP for its 10nm Kirin 970 mobile application processor. The Kirin 970 being integrated into Huawei’s new Mate 10 Series mobile phones (HiSilicon is a subsidiary of Huawei), we can expect the IC production volumes to be huge. In fact, Huawei is ranked #3 for WW smartphone shipment in 2017, with a market share becoming closer to the #2 Apple. Let’s take a look at the various Tensilica DSP IP cores and figure out their positioning in respect with imaging, vision processing or emerging applications such as 3D sensing, human/machine interface, AR/VR and biometric identification for the mobile platform.
The above picture is useful to discriminate between the Vision P5 DSP, Vision P6 and Vision C5 DSP. At first the architecture, wide vector/SIMD (Single Instruction Multiple Data), is identical when the instruction set is optimized for imaging application (P5 and P6) or for Neural Network (NN) for the Vision C5 DSP.
The Vision P5 DSP was released in September 2015. It’s a general-purpose imaging DSP with 64 MACs, optimized for computational photography algorithms, like the Vision P6, but the latter (released in September 2016) is offering occasional-use neural network recognition and 4X MACs, with 256 MACs. Designer can select an optional 32 ways SIMD vector FPU with 16-bits (FP 16).
The Vision C5 DSP, released in September 2017, also offers 4X MACs count, with 1024 8-bit MACs or 512 16-bit. But the main difference with the P family is that the complete DSP is optimized to run all NN layers and allows running full-time NN (Always-on NN), supporting face detection, people detection, object detection and gesture detection and running video analysis and AI. The Vision C5 is optimized for vision, radar/lidar and fused-sensor applications and target surveillance, drone and mobile/wearable markets.
I remember the time where the only DSP into a mobile phone was integrated to support the modem… if you look at the Kirin 970 bloc diagram (above), you realize that digital signal processing is now intensively used in a mobile phone.
The global-mode modem is LTE modem (a Category 18 modem) with download capabilities of 1.2Gbps, based on DSP. Dual-back sensors are now integrated into mobile phone, and dual camera requires increased computational requirements for the imaging functionality -another DSP like function, supported by a dual camera ISP in the Kirin 970. Huawei’s i7 sensor processor is also a DSP based function, like obviously the Cadence/Tensilica Vision P6 image DSP doing Pre-and Post-image processing and the HiFi Audio processing.
Let’s address the dual-back sensors capability of the Kirin 970. According with a report from IBS “Image Sensor and Image Signal Processing” (Sep 2016), the integration of dual-back image sensors will replace the single-back sensor, as shipments will be at 50%/50% in 2020. The CMOS Image Sensor (CIS) market is not as well-known as the Apps Processor or modem market, but it’s weighting $12 billion in 2016 and will grow with 10% CAGR up to 2025 (according with IBS or with Yole, French based analyst specialized in the sensor industry). As far as I am concerned, I didn’t know that much about this market one year ago as I discovered it in 2017 while working for an IP start-up targeting CIS, but I can now tell that it will be one of the fastest growing semiconductor segment, thanks to the dual-back sensors adoption in mobile and also to the CIS pervasion in automotive, new cars integrating from 3 to up to 10 cameras! Stay tuned as the CIS IP segment could be one of the session of the next DAC IP in 2018…
If the phone integrates two back sensors, that make sense to use dual ISP to extract the best picture quality (in fact Huawei has shown a comparison of the same image taken with Samsung Galaxy S8 and Huawei Mate 10 Pro during a presentation in Berlin in September, and the result is a blurry pic with Samsung). But two ISP also means that the Vision processor (Tensilica Vision P6 DSP here) has to be much more powerful than before. Cadence is claiming to have the highest per-cycle processing with 4 vectors per cycle (each 64-way SIMD), the widest memory interface at 1024 bits. As the Vision P6 is running at 1.1 GHz on 16nm FF, we may expect it to run even faster in the Kirin 970 targeting 10nm.
I end up with this last picture showing the great energy efficiency of Tensilica Vision DSP, up to 25X better than CPU. More than just low power, energy efficiency will become the key concern of semiconductor devices of the future… and yes, we will most probably also address this topic during IP session at DAC 2018!
How MediaTek is using the Vision P5 DSP in their Helio P30 SoC, you can find some info on AnandTech here:
http://www.anandtech.com/show/11770/mediatek-helio-p23-helio-p30-midrange-socs
By Eric Esteve fromIPnest
The complexity of silicon chips is exploding. Actually, it has been growing at a tremendous speed for decades. So far, the semiconductor industry has been successful at providing new ways to master new levels of complexity, over and over again.
Standardizing hardware platforms, using higher-level languages with a knowledge of the underlying hardware (like OpenCL), heavily reusing IPs, simulating from system to the gate, speeding up our EDA software, leaving the bulk of functionality to software…
All this has been a relentless quest for new strategies to master complexity.
We all know that this is not always a rosy picture, however. Despite adopting new strategies and deploying new tools, making an ASIC, a SoC or a FPGA ready for production is a long path paved with sweat, doubts and excitement too.
How about ‘Desillusion’? Maybe as well.
We,FPGA engineers, have run against quite some of it. For some time, we had thought that we had been blessed among other electronic engineers, because, well, the chip can be changed and fixed in the field, right?No worries about the high NRE cost, no risk of wasting a few 100th of millions dollars because of a respin.
Using a prototype provides much faster execution than simulation and reveals the imperfections of the models we use in simulation.
In the end, we can just take a sample in the field before production, so there is no risk of any unforeseen behavior…
Right? Right?
Well, not quite. Prototyping a complex chip on a FPGA is a good approach only if you can get a reasonable visibility out of it. Once on a board, a chip is fast and essentially opaque.
Should we give up debugging and analysis on FPGA prototypes because we lack visibility? Actually, using FPGA prototypes is not the problem. The problem is that the tools we use with FPGA prototypes did not scale with their gigantic complexity. Using FPGA prototypes is not the problem. The problem is that the tools we use did not scale with FPGAs’ gigantic complexity.
‘Did not’ scale you say?
Please watch the recording below: it show a capture of live data from inside a FPGA placed in the field, that spans over more than 1 hour – that is far more than what simulation usually shows – and this, in real condition.
For more information, you can contact meor go to : www.exostivlabs.com
Thank you for reading –
-Frederic Leens
Exostiv Labs provides innovative solution to debug FPGA. Our software / hardware products provide up to 100.000 times more observability than the usual embedded instrumentation solutions at the FPGA speed of operation. Today’s FPGA complexities require a new generation of debugging tools. Exostiv Labs focuses on reaching ultra large observability while preserving the target FPGA memory and I/O resources. This allows visiting new debugging scenarios, with extended reach in time and unprecedented Gigabyte-range debug information recordings.
Automotive markets have added pressure on semiconductor/systems design through demand for ISO26262 compliance – this we all know. But they have also changed the mix of important design types. Once class of design that has become very significant in ADAS, and ultimately autonomous applications, is image signal processing (ISP). Collision-avoidance, pedestrian detection, lane departure and many other features depend on processing images from a variety of sources. In all these cases, fast response is essential, especially in image preconditioning where hardware-based solutions will typically have an edge.
These functions handle a wide range of operations: defect correction, noise filtering, white balance, sharpening and many others. These can be handled through sequences of custom-tuned algorithms which are data-processing-centric rather than control-centric so particularly well-suited to high-level synthesis (HLS).
I check-in to HLS periodically to see how usage is evolving. You can look at this from a generic point of view – will it eventually replace RTL-based design across the majority of designs? I’m not sure that perspective is very illuminating. Methods change often not because a better way emerges to do exactly the same thing but because needs change and a new method better handles those new needs. In this case, automotive needs may be a stimulus for change.
ISP is one example. If you need highest performance along with lowest power and cost, you want a hardware-based solution but this needs careful co-design with associated image-processing software. Getting to the best-possible solution also demands a lot of experimentation through architecture options, for example on word-widths, pipelining and operand sharing.
This is where HLS can really shine. Once you have got through the learning curve (with C++ or SystemC) and you have built up a library of reusable templates, for a new IP development verification and maintenance is much faster, in part because there are simply less lines of unique code for such an IP that would be required in RTL. This isn’t just my view. The Imaging group in ST in a recent webinar say that over the last 3 years they have built a library of 50+ IP, ranging from 10K gates to 2M gates, in a team of less than 10 designers. Naturally the templates are an important part of this and are, I would guess, fairly application-specific. But once built-up, it seems new IPs can be added/adapted quite quickly. This is a pay now or pay more later proposition.
The payback in this flow is quite compelling. First, an IP group is able to deliver very quickly to the SoC verification team a model for basic integration testing. After that the IP team go into detailed functional design for the IP, while exploring architecture tradeoffs and synthesizing to RTL tool (they are using Mentor Catapult). Their verification methodology is a very interesting aspect of this stage. First, the team use the same UVM testbench for both the high-level model and the generated RTL, which means that at RTL, no new verification development should be required, and indeed they find that once the C-level model verifies clean, the generated RTL also verifies clean.
Second, these testbenches are largely developed by the IP designers (with verification experts jumping into to handle special cases). Nice idea. Few product teams are swimming in under-utilized resources (and if they are, that’s probably not a good thing). Better leveraging what resources you have is always a plus, in this case getting more of the verification assets (TB, sequences, constraints, etc.) developed in the design team.
In the final phase of IP development, the team focus on PPA optimization. Again, the high-level nature of the design provides a lot of flexibility to make late-stage changes, in architecture if needed, to get to the most competitive solution that can be delivered. Unlike late-stage changes in RTL which can be very disruptive, here there’s no drama. HLS simply regenerates a new RTL, adapting also to parameter-controlled option changes as needed and the same UVM testbench is again used to test the generated RTL, a very quick process since it has already been proven on the C-level design.
The ST speaker wraps up with a few other observations. Following their methodology, they have been able to reduce total development/verification time on a typical IP by nearly 70%. And by doing the bulk of their verification development at the C++ level (where verification runs much faster), they are able to run thousands of tests in minutes rather than the hours that would be required at RTL, which means they can get to coverage closure much faster.
ST has been in the ISP business for a long time so their suggestions have to be considered expert. If you want to learn more about how they are using Mentor Catapult, you can read the white-paper HERE and view the webinar HERE.
