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DAC 2017 Review

DAC 2017 Review
by Bernard Murphy on 06-15-2017 at 7:00 am

DAC is coming, next week, in beautiful downtown Austin at the Convention Center. I’ll be there Monday and Tuesday, running around the exhibit area. If you haven’t yet got your plane and hotel tickets, drop everything and start looking. I’m guessing this will be as popular as it always is, especially given the venue. I know of multiple parties: the Gary Smith EDA kickoff Sunday night, another Gary Smith party and Solido, Cadence Denali, Silvaco and Cliosoft are all hosting parties downtown.

On the off-chance you’re going to DAC to do something other than party, on keynotes the iconic Joe Costello kicks off Monday with a pitch on “IoT: Tales from the front-line”. Tuesday Chuck Grindstaff from Siemens PLM will talk about digital twins (no, not robot doppelgangers). Wednesday Tyson Tuttle from Silicon Labs will give his view on accelerating the IoT. And Thursday Rosalind Picard will talk about a very intriguing topic, emotion technology, and how this can potentially help people with autism, depression and other problems. I hope they post all the talks because I’ll probably miss them thanks to my schedule.

There’s a lot of focus on IoT, starting with keynotes, but also getting into security, a perennial and constantly evolving challenge. There’s also an interesting looking contest on FPGA-based IoT which should be a must-see for the maker-types among you. Beyond this there is a rich palette of topics of which I can touch on just a few that piqued my interest.

On Sunday, I see a fascinating-sounding workshop on design automation for cyber-physical systems with speakers from Texas A&M, National Taiwan Univ, GM, Technische Univ in Munich, Upenn, UCI and UCF. They’ll be talking about automotive and transportation systems, smart home, building and community, smart battery and energy systems, surveillance systems, cyber-physical biochips, and wearable devices. They’ll be looking at the unique challenges posed by cyber physical systems, certainly in power, performance security and so on, but also real-time operation, handling uncertainties in sensor readings and more.

There will also be a workshop on autonomous vehicles, avionics, transportation and robotics which goes by the catchy handle of AVATAR, though I didn’t notice James Cameron among the speakers. They plan to touch on how needs in these areas intersect or can intersect with EDA, which should make this a very interesting opportunity for EDA product strategists.

On Monday, you’ll find sessions on Security IP for the IoT, also a tutorial on security validation for SoCs. Can’t-miss for any new designs. There are also a couple of machine learning sessions in the morning. In the afternoon, there’s a standard tutorial topic on the future of SoC validation and debug. Standard topic, yes, but you really can’t afford to miss this if you have anything to do with V&V. There will also be a session on safe platforms which probably also is a can’t miss for anyone designing for automotive applications.

Tuesday I noticed a session on security analysis and defense and a very perturbing session called “patch your car like your phone – design for extensibility in automotive systems”. Yikes. In the afternoon, you’ll find a session on model-based design for medical devices (I hope there’s no suggestion those be patchable). Later there’s a topic on AI and CNNs which should be fun. Another interesting theme in the afternoon, for verification geeks like me, is on nearby advances and far frontiers in verification. Then there are more very interesting sessions on security, especially a likely contentious topic asking whether hardware security is making a difference.

Wednesday opens with several topics on cyber-physical systems, including hardware design and time control. There’s a very timely topic on how we should test cognitive systems, particularly since unsupervised learning is becoming so hot. There’s a topic that designers, architects and product managers who can’t make it to Austin will wish they could attend – “Is integration leaving less room for design innovation?”. Then there’s more on safety and advances in security and, for the truly ambitious, several talks on design methods for quantum computing.

Thursday has a session on security nuts and bolts, a deep-dive into neural networks, an intriguing session on microfluidics and approximate computing, pushing beyond deep learning into neuromorphic computing and a topically-inspired session on “making neural networks great again”.

Phew – this is just a sample. First, book your tickets, then check out the full agenda HERE.


The FPGA Business Just Got Interesting Again!

The FPGA Business Just Got Interesting Again!
by Daniel Nenni on 06-14-2017 at 8:00 am

FPGA’s have played an important role in the fabless semiconductor ecosystem which is why it has a full chapter in our book Fabless: The Transformation of the Semiconductor Industry. Along my career path I spent time at a start-up FPGA so I know how hard it is. I worked for GateField which was then acquired by FPGA pioneer Actel which was then acquired by MicroSemi. There are still GateField people at Microsemi and the architecture they developed is still in play so congratulations to them.

Intel acquiring Altera was a big blow to the mainstream FPGA industry which left me wondering who will step up and compete with Xilinx. As it turns out the answer is Achronix:

“2017 is a breakout growth year, which establishes Achronix as one of the fastest growing semiconductor companies in the world. We are experiencing strong customer demand for both our Speedster FPGAs as well as our newer Speedcore embedded FPGA in hardware accelerator applications. We are looking for new talent to complement a very strong core team to continue delivering highly innovative silicon and software products,” said Robert Blake, President and CEO, Achronix Semiconductor.

“Looking forward, we are entering a new high growth era where our customized core FPGA technology can accelerate a broad range of complex compute tasks in machine learning, artificial intelligence, software defined networks and 5G base stations.”


Honestly I was blown away by the numbers since I have known Achronix since they appeared on SemiWiki in April of 2011:Wanted: FPGA start-up! …Dead or Alive?

Coincidentally, I happen to know the Achronix VP of Marketing, Steve Mensor. Steve spent most of his career at Altera with another good friend of mine so that is how we are connected. I had a quick phone chat with Steve about this press release and found out Achronix will be at DAC next week for the first time so we will speak more then and dig into the technology for follow-up blogs. He did share a slide deck with me and I have to say I was impressed.

Steve’s presentation hit on two very hot topics in the semiconductor industry and that is embedded FPGAs and hardware acceleration (think artificial intelligence). SemiWiki’s readership was fairly predictable until IoT hit us in 2014. Now we have a very diverse readership from many domains I don’t recognize. We are seeing the same thing with AI as it touches almost all of the markets we cover including Mobile, IoT, Automotive, and Security.

According to Steve, in addition to Speedster standalone FPGAs and Speedcore eFPGAs they are working on a new product they call Chiplets which is a die for 2.5D package integration.

If you are attending #54DAC next week you can meet Steve and the Achronix team at booth #1821 which is across the aisle from SMIC.

About Achronix Semiconductor Corporation
Achronix is a privately held, fabless semiconductor corporation based in Santa Clara, California. The Company developed its FPGA technology which is the basis of the Speedster22i FPGAs and Speedcore eFPGA technology. All Achronix FPGA products are supported by its ACE design tools that include integrated support for Synopsys (NASDAQ:SNPS) Synplify Pro. The company has sales offices and representatives in the United States, Europe, and China, and has a research and design office in Bangalore, India. Find out more at https://www.achronix.com.


Worldwide Design IP Revenue Grew 13.1% in 2016, According to Final Results by IPnest

Worldwide Design IP Revenue Grew 13.1% in 2016, According to Final Results by IPnest
by Eric Esteve on 06-14-2017 at 7:00 am

Despite the strong consolidation in the semiconductor industry, the Design IP market is going well, very well with YoY growth of 13.1% in 2016, according with the Design IP Report from IPnest. ARM Group of Softbank (previously known as ARM Holding) is again the strong #1 with IP revenues (licenses plus royalties) of $1,647 million and 48.4% market share, followed by Synopsys with about $450 million and 13% share. Imagination technologies is still #3, despite IP revenues for 2016 decreasing by more than 20% and Cadence is #4, while the IP revenues have also decreased in 2016.

IPnest has defined 11 categories and 3 groups, Processor, Physical and Digital IP, ranking IP vendors in these 11 categories. The processor IP group is the largest, with about 60% of revenues from design IP. The group is split into Microprocessor (CPU), Digital Signal Processors (DSP) and Graphic and Image Processors (GPU and ISP) categories. There are strong disparities between these 3 categories as the weight of the CPU category is about 10x the DSP and 5x the GPU/ISP.

ARM is obviously the strong #1 in the CPU category, and will probably keep this position forever, due to the royalty mechanism… and the successful company strategy of diversification outside of the mobile phone, namely in storage (95% market share), wearable (90%), networking (15%) or embedded intelligence (25%). In this CPU category, Imagination Technologies (IMG) is #2 with their MIPS IP family and Synopsys #3 with ARC IP family. Now, if we consider the market dynamics in 2016 where IMG has seen MIPS IP revenues decrease by 10% while Synopsys has grown ARC IP revenues by 13.5%, it wouldn’t be surprising to see Synopsys becoming #2 in 2017. The good question is “who will consolidate MIPS IP revenues?”, as the product line is for sale since the beginning of 2017…

In the GPU/ISP category, ARM was #2 with MALI GPU IP just behind IMG in 2015, but has passed IMG in 2016. ARM has now 46.5% market share in GPU/ISP, for 35.8% for IMG in 2016. More than a brilliant success from ARM (the company has seen a 2.2% YoY with GPU in 2016), this change is sanctioning the deficient performance of IMG, with GPU IP revenue drop of 23.9% in 2016! As a side notice, this revenue drop has happened before than Apple, IMG’s best customer, has announced that they plan to internally develop the GPU IP to be integrated in their next application processor for smartphone…

To end up with a positive point, Verisilicon (after Vivante acquisition) is the #3 in this category, and we can expect the company to keep growing in the future, as their home market (China) is expected to explode during the next years.

The DSP IP category is leaded by Cadence (#1) and CEVA, and the #2 is doing extremely well in 2016, with 22.6% revenues growth. I had the opportunity to review the financial communication by quarter from CEVA for the last 3 or 4 years, and the most noticeable point if the company constant diversification out of the mobile phone. In the latest communication for Q1 2017, CEVA is announcing height new DSP IP licenses, all of them non-handset baseband applications!

The next group after processor is the Physical IP, including Wired Interface IP, SRAM memory compiler, Other memory compilers, Physical Libraries, Analog and Mixed-Signal and Wireless Interface IP, weighting slightly less than 30% of the total, but more than 50% of the license only revenues. The clear leader, Synopsys with 29% market share, is active in most of the categories and leader with 50%+ market share in the Wired Interface IP. This category is also the largest with more than $500 million in 2016 and IPnest has made extensive research work since 2009 on wired interface, including this 2010-2020 Survey/Forecast which can be found in the “Interface IP Survey”, the best seller from IPnest.

In the 2[SUP]nd[/SUP] part of this article, I will propose a detailed analysis for the Physical IP categories not covered today, as well as for the Digital IP group (Chip Infrastructure and Miscellaneous Digital).

If you’re interested by this “Design IP Report” released in May 2017, just contact me: eric.esteve@ip-nest.com .

Last but not least, I hope you will go to the DAC 2017 in Austin! With my colleagues of the IP committee we have prepared conferences and panel sessions, and we really expect you to take benefit of these four days to learn about the hot topics in design IP from Verification, Security for IoT to the IP Paradox panel (moderated by Dan Nenni!)…

I will dedicate a complete blog to this panel very soon.


Eric Esteve from IPnest


The Official SemiWiki #54DAC Party Guide!

The Official SemiWiki #54DAC Party Guide!
by Daniel Nenni on 06-13-2017 at 12:00 pm

With the premier conference for semiconductor design enablement just around the corner I would like to take this time and space to talk about what is really happening at the #54DAC and that would be the parties! Granted the DAC parties are nothing like we used to have in the 1980s and the 1990s since we have matured as an industry but there is still fun to be had.

First I would like to mention my DAC speaking engagement for this year which is at the Minalogic Showcase on Tuesday from 4-6pm in room 8C, second floor mezzanine at the Austin Convention Center. You can read more about Minalogic HERE but certainly you will recognize the president’s name Philippe Magarshack. In my talk I will be covering Semiconductors: Past, Present, and Future which will be a retrospective based on my professional experience, writings on SemiWiki.com, and the analytics behind the writing. Really there are two premises: First, you have to thoroughly understand how you got to where you are today before you can plan for where you are going to tomorrow. Second, the pen truly is more powerful than the sword especially the analytics behind the pen.

The other presenters include:
Eric Mottin, Microelectronics’ Director – Minalogic
Presentation of Minalogic & EDA Members & Specificities
Firas Mohamed, General Manager – Silvaco France
“Fostering Innovation in TCAD, EDA & IP”
Thierry Collette, VP, Architecture, IC Design & Embedded Software Division, Leti
Overview of Design & EDA Challenges for SOI Technology
Ramy Iskander, CEO – Intento Design
Accelerated Constraint-Driven Analog Design and Migration at Functional Level
Isabelle Geday, CEO – Magillem
Integrating Specification, Design and Documentation to Optimize SoC Design Cycle and Legacy Reuse
Jean-Marc Talbot, Senior Engineering Director DSM/AMS – Mentor Graphics

The event is free but space is limited so please register HERE in advance. Following the speakers will be a networking reception which to me qualifies as a DAC party. My beautiful wife and I will be bringing copies of our book “Fabless: The Transformation of the Semiconductor Industry” if you would like a copy. Be sure and ask me to sign it and pretend I am important in front of my wife.

Now to the parties:

The first one of course is the traditional Sunday night Gary Smith EDA Kickoff which is from 5-5:30pm in Ballroom D of the convention center and is followed immediately by the official DAC Reception on the 4[SUP]th[/SUP] floor foyer that runs from 5:30-7pm. The Gary Smith Kickoff generally fills up so you should get there early if possible. DAC also hosts receptions on Monday, Tuesday, Wednesday, and Thursday evenings (same place and time). You can see a list of all DAC events HERE.

On Monday night the real parties start. After the DAC welcome reception (6:00pm – 7:00pm Trinity St. Foyer) my beautiful wife and I will be at the Gary Smith Benefit Party(7-10pm) at the Speakeasy on 412 Congress Ave in parallel with the first annual Solido Rooftop Party on the Speakeasy rooftop (7-11pm).

On Tuesday night it gets a bit crazy. You can choose from the Cadence Denali Party(8:00pm) at the Palm Door on Sixth 508 E 6th Street and/or the Stars of IP Party(7pm to 12am) again at the Speakeasy. My beautiful wife and I will be going to the Cliosoft Party(7-11pm) at Micheladas Café y Cantina on 333 E 2[SUP]nd[/SUP] Street. Why you ask? Because we received a personal invitation, they encourage you to bring spouses/friends, and we really like margaritas. Okay mostly because we really like margaritas and Michelas serves the best ones in town.

I’m sure I have missed some of the DAC parties so please add them in the comments section and I can put them on the blog as they come in.

Safe travels and we look forward to seeing you there!

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GlobalFoundries 7nm and EUV Update!

GlobalFoundries 7nm and EUV Update!
by Daniel Nenni on 06-13-2017 at 7:00 am

Scott Jones and I had the opportunity to talk again with Gary Patton, GlobalFoundries CTO and SVP of R&D for a quick update on 7nm and EUV. Gary has been at GF for two years now with more than 500 other technologists from the IBM semiconductor acquisition. 7nm is the first IBM based process from GF (14nm was licensed from Samsung), it will also be the first time AMD has a process advantage over Intel.

“We are very pleased with the leading-edge technology that GF is bringing with its advanced 7nm processtechnology. Our collaborative work with GF is focused on creating high-performance products that will drive more immersive and instinctive computing experiences.”MarkPapermaster, CTO and senior vice president of technology and engineering, AMD.

Scott Jones will be updating his 14nm 16nm 10nm and 7nm – What we know now blog with the latest specs from GF 7nm in the next week or so. One thing you will notice is that the GF 7nm and TSMC 7nm are much more similar than previously thought. GF however is leading with a high performance (LP equals Lead Performance in IBM speak) version of 7nm for AMD while TSMC is first with a low power version of 7nm for Apple, Qualcomm, MediaTek, and the other SoC vendors. The similarity between the TSMC and GF 7nm processes does open up the opportunity for GF to do some serious 2[SUP]nd[/SUP] sourcing which is a critical component to the pure-play foundries business model, absolutely.

GF 7LP will be in volume production in the second half of 2018 and is expected to provide a greater than 40% improvement and 2x the area scaling over Samsung 14nm. According to Gary, EUV tools will be installed in the second half of 2017 with the hopes of inserting EUV into 7nm in 2019. My guess would be 2020 at the earliest but the point here is that EUV is not holding up 7nm for TSMC or GF and we should all be thankful for that.


Back to the AMD thing. Given that the new AMD Ryzen architecture was launched on 14nm in Q1 2017, it should be reasonable to predict that AMD could refresh Ryzen on 7nm in the second half of 2018 putting AMD 7nm just six months behind Intel 10nm. I certainly hope this is the case because I really want to see how Intel PR spins that one!

GLOBALFOUNDRIES on Track to Deliver Leading-Performance 7nm FinFET Technology


An Approach to TFT and FPD Design

An Approach to TFT and FPD Design
by Daniel Payne on 06-12-2017 at 4:00 pm

Webinars are a powerful way for engineers to get updated on EDA and IC design approaches, so I’m sharing what I viewed last month at a Silvaco webinar on TFT and FPD design. You probably are using a TFT LCD display in your TV, monitor, mobile phone, video game system, GPS device or projector. The custom IC design flow offered by Silvaco is shown below for both front-end and back-end tools:
Continue reading “An Approach to TFT and FPD Design”


Design Rule Development Platform @ #54DAC!

Design Rule Development Platform @ #54DAC!
by Daniel Nenni on 06-12-2017 at 12:00 pm

While some might have expected the exponential growth in design rules number and complexity to cool down a little, it looks as if these are only heating up more. The multiplicity of technology nodes, lithography options, , fundamental technology options (Bulk, FD-SOI, FinFET), different process flavors and specific applications, have made design enablement and design rules in particular an even more painful issue than it used to be.

Sage-DA addresses this problem in a systematic way with iDRM, a complete end-to-end integrated Design Rule Management System. iDRM encompasses all steps of design rule development, from design rule capture by the process integration team to the delivery of a compiled and verified DRC deck that accurately matches and represents the design rule intent.

The system significantly shortens the turnaround time of every PDK release, reduces the engineering effort and most importantly – maintains consistency and eliminates errors.

The benefits of automation are apparent and the value in this case is enormous, since the cost of mistakes and delayed delivery is so high. However at the same time, automation can sometimes seem disruptive and intimidating and therefore not always quick to adopt. To facilitate a smooth and easy adoption of this new automation technology, Sage-DA has developed new features in the new iDRM system, which it will show this year at DAC.

The system puts an emphasis on interface and integration with existing tools and environments, so that iDRM can be easily integrated into current technology development and enablement flows. It includes features such as:

Reading from and synchronizing with design rule spreadsheets. This enables automatic import of design rules into the iDRM system and instant synchronization of any rule update or new rule additions.
Using pre-defined rule templates. Most rules can be entered using a pre-defined rule type (or template) , this makes adding rules and rule editing quicker, easier and more consistent.
Extraction of design rule values from existing layouts so that they don’t need to be typed in manually
Compilation of sign-off DRC code. Users can automatically generate DRC code for their signoff DRC tool by using rule templates.
QA and test of DRC code by automatic generation of pass/fail patterns with coverage measurement


Early customer deployment successful experience

The significant investment Sage has put into the new upgraded system is already paying off for Sage and its customers. Sage mentioned two recent successful customer use-cases:

1. An advanced technology semiconductor company uses iDRM to enforce consistency and to automatically generate 3rd party DRC code for its most advanced node technology (below 14nm). The results are faster turnaround times for DRC runsets and ensured consistency.

2. Another semiconductor company develops multiple and diverse IC technologies for different markets and applications. It uses iDRM to qualify and validate their DRC signoff runsets, using the DRVerify tool of iDRM. DRVerify automatically generates high coverage QA test layout to test the DRC runset. Using the system, the users were already able to detect errors and gaps in their existing signoff DRC runsets, which until then were traditionally coded and qualified.

Sage-DA will demo the new system and functionality at DAC in Austin next week. You can find them at booth #513 or see http://www.sage-da.com/news/1706-sage-dac2017.html


Visual Quality

Visual Quality
by Bernard Murphy on 06-12-2017 at 7:00 am

A few years ago, I started looking at data visualization methods as a way to make sense of large quantities of complex data. This is a technique that has become very popular in big data analytics where it is effectively impossible to see patterns in data in any other way. There are vast numbers of different types of diagram – treemap, network and Sankey are just a few examples – each designed to highlight certain aspects of the data – concentration, connectivity, relative size and other characteristics. Given the right type of diagram, key attributes of mountains of data can become immediately obvious.


I didn’t get beyond an experimental stage in my work, so I was very happy to see that Rene Donkers, CEO at Fractal, had finished the job in delivering a production capability for data visualization around library analytics, which he calls error fingerprint visualization.

Library (Liberty) files can get pretty large, covering OCV timing models and power models among many other characteristics. Which raises an obvious question – how do you check that this stuff is correct? I’m not thinking here about the basics – whether each model has the right name and the right pins, or basic consistency checks between these and the tables. Questions around table data can become more challenging. Monotonicity and the correct sign of the slope are already covered in the Fractal Crossfire product, but whether values fall within reasonable bounds is no longer a binary question – there is no bright line separating reasonable from unreasonable.


Crossfire now provides help in analyzing these cases through visualization. For example, for rule 7201: “Range check for cell_rise/cell_fall delay values”, you start by specifying what you think is an acceptable range for these delays, say 0-10ns. Delay values outside this range will be flagged in the normal type of error listing, but that could amount to a lot of error messages. The trick in this or any other effective visualization is to present aspects of that information in a way that makes it easy to reach conclusions about root causes. In the example above, they present all violations in a network diagram, starting from the cell-name, with connections to associated tables and from there variously through pin names, min and max values and applicable range limits.

You can temporarily extend an allowed range through waivers. In the example above, blue lines show violations which fall within waiver limits, whereas red lines show cases falling outside those limits. Waivers provide a way to experiment with more relaxed bounds before committing to those changes.

What stands out from the diagram above (OK, you need to look closely; try magnifying or look at the white paper link below) is that a lot of errors are associated with the OAMOD pin. You immediately see that you need to drill down into problems with that pin. Maybe this is a design problem, maybe a characterization problem, either way it’s obvious that addressing this area can resolve a lot of the flagged errors.

This goes to the heart of the value of visualization methods. When looking at failures from any kind of pass/fail analysis (or indeed any binary division of data), it is unlikely that the data is randomly distributed, especially when effort has been made to reduce failures. It is probable that many failures can be attributed to a relatively small number of root-causes.


Similarly, the visual can help you decide if maybe the limits you set on values should be adjusted. If values beyond an upper limit increase at a modest pace, perhaps the upper bound should be increased. If they show signs of rising rapidly, perhaps that signals a design or characterization problem, or maybe an unavoidable characteristic of this cell in this usage, indicating that designers need to be warned not to stray into this area.

I’m a believer in visualization aids to analysis of complex data. We can only do so much with pass-fail metrics presented in lists and spreadsheets. Visualization provides a way to tap skills we already have that can be much more powerful than our limited ability to see patterns through text and number inspection. Until we have deep-learning to handle these problems, perhaps we should put our visual cortex to work. You can learn more about Crossfire error fingerprints HERE.


Cadence Design Systems @ #54DAC!

Cadence Design Systems @ #54DAC!
by Daniel Nenni on 06-11-2017 at 8:00 am

This year Cadence Design Systems is showcasing system design enablement in their booth, capitalizing on the industry shift from naked chip design to system level chip design. Apple started it with making the chips inside the iProducts as part of the system and now other systems companies are looking to take more control over their silicon. We can see it with the SemiWiki readership and the widening distribution of domains over the last six years. Companies we would have never expected to be reading about semiconductor design enablement are stopping by much more frequently, especially with IoT, Automotive, and Artificial Intelligence, it really is all about the system.

Historically Cadence does a great DAC and this year will be no different. Let’s start with the Cadence luncheon series because that involves FREE FOOD, the opportunity for some great table talk, more FREE FOOD, and some trending topics:

Towards Smarter Verification
Monday, June 19 – 12:00-1:30pm, Ballroom B/C

High-Performance Digital Design at 7nm
Tuesday, June 20 – 12:00-1:30pm, Ballroom B/C

Overcoming Mixed-Signal Design and Verification Challenges in Automotive and IoT Systems
Wednesday, June 21 – 12:00-1:30pm, Ballroom B/C

Speaking of 7nm, TSMC and GlobalFoundries are both shipping production quality PDKs so you will see a lot of 7nm design talk at DAC this year. GF is a quarter or two behind TSMC on 7nm but it is close enough for some of the top semiconductor companies to hedge their bets and design to both, absolutely. I don’t even recall the last time two pure-play foundries had competitive leading edge technology out at the same time, if ever.

Cadence is doing the expert bar again this year which is something I enjoy. It is kind of like the Apple Genius Bar except Cadence actually has geniuses. There are 60 different slots on a variety of topics which you can see HERE.

Cadence is hosting more than 20 technical sessions on the latest developments in digital, custom/analog, and verification that you can choose from HERE.The Cadence Theater is also packed with 30+ presentations from partners and customers HERE. The partner and customer talks are the most interesting to me. Partners and customers really do say a lot about a company, right? It is all about the ecosystem…

Last but not least for content there are the Cadence DAC sessions starting with the One-on-One with Lip-Bu Tan in the DAC Pavilion. This is a session I will be at because not only do I remember Cadence before Lip-Bu, I remember Cadence before Cadence was actually Cadence (the ECAD days…). After Lip-Bu’s arrival in 2009, Cadence went through an EDA transformation like no other I have witnessed in my 30+ years and I am interested to hear about what is next. It truly has been an honor covering Cadence the past 6 years on SemiWiki, absolutely.

And let’s not forget about the Denali Party. Space is limited so register today:

Mix, Mingle, and Enjoy!
The Denali Party by Cadence
Tuesday, June 20, 8:00pm
Palm Door on Sixth
508 E 6th Street, Austin, TX

Ready for a night to remember? Catch up with old friends and meet some new ones at the popular Denali[SUP]®[/SUP] Party by Cadence. For your musical entertainment, Disco Inferno will be back to rock the house.

NOTE: You must pick up your wristband from the Cadence team in booth #107 before noon on Tuesday, June 20 or your reservation will be given to another guest.


Mentor a Siemens Business @#54thDAC

Mentor a Siemens Business @#54thDAC
by Daniel Nenni on 06-11-2017 at 7:00 am

This year the Mentor booth will be quite interesting now that they are part of Siemens. I expect zero changes to their DAC presence but we shall see. It will certainly be good to see Wally again. More importantly, I will be afforded the opportunity to talk personally with both Wally Rhines, CEO of Mentor ANDChuck Grindstaff executive chair, Siemens PLM Software, about the recent acquisitionand what happens moving forward. Inquiring minds want to know……


If you look at the Mentor DAC landing page you will see IoT front and center with a panel on Overcoming the Challenges of Creating Custom SoCs for IoT:

The hardware industry finds itself in a new wave of innovation driven by custom SoC development for mixed-signal IoT devices. These devices span an incredibly diverse set of markets, from medical to white goods, and everything in between. With the demand for IoT connectivity and secure data management, what are the best options for today’s systems designers? This panel will explore various options and viable solutions to help designers innovate and to provide unprecedented services to the personal, industrial, and societal levels.

Looking at the SemiWiki analytics I still see IoT as driving not only the most total traffic but also the most diverse collection of domains and crossing the most SemiWiki catagories. In fact, as of today, we have published close to 400 IoT related articles that have been viewed more than 1,000,000 times.

The next highlighted panel is The Explosion of Emulation Use Models in Diverse segments:

Hardware emulation is the star in today’s verification flow. Complexity and the rising cost of doing verification forces project groups to become more innovative about SoC debug and the validation of HW/SW system integration. Expanding emulation use models makes emulation an easy choice. It’s flexible, versatile and scalable. Data center access makes it a cost effective approach for global project groups. Stop by the Mentor, a Siemens Business, DAC booth (#947) to hear a panel of experts describe how to use emulation to build an effective verification and validation platform.

Emulation is certainly a trending topic in semiconductor and system design, in fact, Bernard Murphy and I are finishing up a book on emulation to be published later this year so stay tuned to SemiWiki.com.

The other highlighted panel is on the Impact of ISO 26262 on the fabless Ecosystem:

As fabless companies design products for the rapidly-expanding automotive semiconductor market, whether they are power window controllers or drive-by-wire systems, they have to meet the exacting requirements of the ISO 26262 standard for functional safety. Those requirements affect not only the end product itself, but the software that it runs and the software used to create, validate, and test it. As a result, ISO 26262 has far-reaching impact on the fabless ecosystem, including EDA tools, software, and IP. Come listen to leaders in the industry who have pioneered the way forward for ISO 26262 in the fabless ecosystem as they discuss the challenges that they have faced, what they have done, and what they think still needs to be done in the industry.

Personally, I’m a big fan of interactive panels and I have asked the SemiWiki bloggers to attend as many as possible to share this content with our readers who could not attend.

Mentor will also give us access to some of the best researchers and partners in their booth for you to meet and exchange ideas with (Experts at the Mentor Graphics Booth). There are literally dozens to choose from but you need to sign up for them. The foundries are well represented here as well as some of the top semiconductor companies.

Mentor is also hosting several Networking and Lunches which I find huge value in. Not only does it include FREE FOOD and FREE DRINK (I blog for food and drink), you can actually learn stuff and meet other semiconductor professionals to further your professional goals.

And of course there are Partner Activities because where would we be without partners to collaborate with? We would still be using rotary phones no doubt. There are 18 partners listed including the Foundries, Universities, Customers, EDA and IP companies.

I hope to see you there, absolutely!