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Webinar of Recent NCTU CDM/ESD Keynote Talk by Dundar Dumlugol – Thursday September 26th

Webinar of Recent NCTU CDM/ESD Keynote Talk by Dundar Dumlugol – Thursday September 26th
by Daniel Nenni on 09-24-2019 at 10:00 am
Categories: EDA, Magwel

With many design teams still searching for an effective means of identifying Charged Device Model (CDM) issues early in the design process, it comes as no surprise that events on this topic generate a lot of interest and are well attended. In July Magwel’s CEO Dr. Dundar Dumlugol had the honor of being invited by Professor Ming-Dou Ker to speak at Taiwan’s National Chiao-Tung University (NCTU) on the topic of ESD and CDM event simulation. NCTU’s esteemed electrical engineering department serves as a center of expertise on the topic of ESD.

The session was well attended (myself included) and provided an excellent overview of the larger scope of ESD in general and on CDM specifically. Dundar reviewed the existing methods of analyzing an IC design for weaknesses that could lead to CDM related failures. He also discussed Magwel’s approach to solving these challenging design problems. During the talk he showed several examples of CDM discharge scenarios and what tools should be looking for in order to properly simulate the events.

The July seminar was recorded and is replayed HERE. This is a good opportunity to learn about the most effective ways to prevent CDM failures in finished designs. Magwel has applied their expertise in solver-based extractors and dynamic simulation to develop their CDMi tool. CDMi simulates current flows during high speed CDM pulses and determines which ESD devices are triggered. Overvoltage or overcurrent violations are reported through an intuitive UI.

About Us
Magwel® offers 3D field solver and simulation based analysis and design solutions for digital, analog/mixed-signal, power management, automotive, and RF semiconductors. Magwel® software products address power device design with Rdson extraction and electro-migration analysis, ESD protection network simulation/analysis, latch-up analysis and power distribution network integrity with EMIR and thermal analysis. Leading semiconductor vendors use Magwel’s tools to improve productivity, avoid redesign, respins and field failures. Magwel is privately held and is headquartered in Leuven, Belgium. Further information on Magwel can be found at www.magwel.com

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Cadence Celsius Heats Up 3D System-Level Electro-Thermal Modeling Market

Cadence Celsius Heats Up 3D System-Level Electro-Thermal Modeling Market
by Tom Simon on 09-24-2019 at 6:00 am
Categories: Cadence, EDA

A few years back people were saying that the “EDA” problem was solved and that design tools had become commodity. At the same time people hailed ADAS, smart homes, mobile communication and AI as the frontiers of electronics.  Perhaps it could be said that layout tools, routers, placers, and circuit simulators had largely matured and often could be used interchangeably to successfully complete electronic designs. However, there were new challenges arising due to the increasing complexity of electronic systems – like the very ones used in cars, smart homes, mobile and AI.

At more advanced nodes and with increasing computational requirements, ICs have become bigger consumers of power. ICs are also being packaged tightly together in configurations using interposers, 3D ICs, etc. Heat buildup in these systems is a very real concern. IC performance and behavior are affected by temperature, and of course too much heat can lead to failure over time or rapidly in some cases. We all have experienced laptops heating up on our laps or cell phones warming up in our pockets. If the exterior is getting hot, what is happening on the inside, from silicon, to package, board, heat sink and chassis?

Cadence Celsius

System level thermal performance cannot be left to chance, it needs to be simulated and well understood during the design process. Up until now there has not been a solution for system level behavior. Cadence has just announced a system level electro-thermal simulator that includes multi-physics and interfaces with other design tools to effectively solve this problem. IC designs are in Virtuoso, packages are in SiP and boards are in Allegro. 3D assemblies come from 3D CAD packages. Celsius can import the full system design and then model thermal behavior.

Power information is obtained from Cadence Voltus, then steady state or transient thermal results can be obtained through Celsius. With accurate temperature information, Voltus can then provide more accurate power information, improving accuracy of the final results. Celsius uses Finite Element Analysis (FEA) and Computational Fluid Dynamics (CFD) to model internal thermal flux and airflow inside of the fully assembled system.

At smaller scales the problem of electro-thermal analysis has been tractable, but with the sizes of current and future generations of electronics systems, there has not been a feasible solution. Cadence Celsius is using massively parallel execution to increase capacity and boost performance. Interestingly, they are using a similar capability for their Clarity EM solver for system level analysis. Celsius can add hundreds of CPUs to effectively increase performance. An example provided by Cadence shows that with 320 CPUs, runtime is 10.2X faster than legacy solvers running on 40 CPUs. Even with the baseline 40 CPUs, Celsius is 2.5X faster.

Building today’s advanced electronic products and systems requires integration of many disciplines at once to ensure good results. For instance, an electronic system might appear to have adequate heat dissipation capacity, but transitions from one operating mode to another or changes in power consumption due to elevated temperatures may lead to exceeding allowable design parameters. Simulation and analysis that includes both thermal and electronic domains is necessary to avoid costly late cycle iterations to fix design problems.

With Celsius, Cadence is delivering its second system-level high-capacity and high-performance analysis tool. Both Clarity and Celsius use highly scalable solver technology to boost capacity so real-world systems can be fully analyzed. They also both accept inputs from 3D modeling, board, package an IC design flows, to permit full integration of all design elements. What they are doing today is a far cry from the era when EDA tools were siloed and only looked at a small part of the overall problem. With this move, Cadence is showing how EDA vendors, with the right vision, can leave behind the notion that EDA is a “solved problem” that offers little differentiation. Companies that adopt these tools will have a significant advantage in their design process that will lead to more successful products. Full information on Celsius is available on the Cadence website.

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AI Inference at the Edge – Architecture and Design

AI Inference at the Edge – Architecture and Design
by Tom Dillinger on 09-23-2019 at 10:00 am
Categories: eFPGA, Flex Logix, IP

In the old days, product architects would throw a functional block diagram “over the wall” to the design team, who would plan the physical implementation, analyze the timing of estimated critical paths, and forecast the signal switching activity on representative benchmarks.  A common reply back to the architects was, “We’ve evaluated the preliminary results against the power, performance, and cost targets – pick two.”  Today, this traditional “silo-based” division of tasks is insufficient.  A close collaboration between architecture and design addressing all facets of product development is required.  This is perhaps best exemplified by AI inference engines at the edge, where there is a huge demand for analysis of image data, specifically object recognition and object classification (typically in a dense visual field).

The requirements for object classification at the edge differ from a more general product application.  Raw performance data – e.g., maximal operations per section (TOPS) – is less meaningful.  Designers seek to optimize the inference engine frames per second (fps), frames per watt (fpW), and frames per dollar (fp$).  Correspondingly, architects must address the convolutional neural network (CNN) topologies that achieve high classification accuracy, while meeting the fps, fpW, and fp$ product goals.  This activity is further complicated by the rapidly evolving results of CNN research – the architecture must also be sufficiently extendible to support advances in CNN technology.

Background

AI inference for analysis of image data consists of two primary steps – please refer to the figure below.

Feature extraction commonly utilizes a (three-dimensional) CNN, supporting the two dimensions of the pixel image plus the (RGB) color intensity.  A convolutional filter is applied to strides of pixels in the image.  The filter matrix is a set of learned weights.  The size of the filter coefficient array is larger than the stride to incorporate data from surrounding pixels, to identify distinct feature characteristics.  (The perimeter of the image is “padded” with data values, for the filter calculation at edge pixels.)  The simplest example would use a 3×3 filter with a stride of 1 pixel.  Multiple convolution filters are commonly applied (with different feature extraction properties), resulting in multiple feature maps for the image, to be combined as the output of the convolution layer.  This output is then provided to a non-linear function, such as Rectified Linear Unit (ReLU), sigmoid, tanh, softmax, etc.

The dimensionality of the data for subsequent layers in the neural network is reduced by pooling – various approaches are used to select the stride and mathematical algorithm to reduce the dataset to a smaller dimension.

Feature extraction is followed by object classification.  The data from the CNN layers is flattened and input to a conventional, fully-connected neural network, whose output identifies the presence and location of the objects in the image, from the set of predefined classes used during training.

Training of a complex CNN is similar to that of a conventional neural network.  A set of images with identified object classes is provided to the network.  The architect selects the number and size of filters and the stride for each CNN layer.  Optimization algorithms work backward from the final classification results on the image set, to update the CNN filter values.

Note that the image set used for training is often quite complex.  (For example, check out the Microsoft COCO, PASCAL VOC, and Google Open Images datasets.)  The number of object classes is large.  Objects may be scaled in unusual aspect ratios.  Objects may be partially obscured or truncated.  Objects may be present in varied viewpoints and diverse lighting conditions.  Object classification research strives to achieve greater accuracy on these training sets.

Early CNN approaches applied “sliding windows” across the image for analysis.  Iterations of the algorithm would adaptively size the windows to isolate objects in bounding boxes for classification.  Although high in accuracy, the computational effort of this method is extremely high and the throughput is low – not suitable for inference at the edge.  The main thrust for image analysis requiring real-time fps throughput is to use full-image, one-step CNN networks, as was depicted in the figure above.  A single convolutional network simultaneously predicts multiple bounding boxes and object class probabilities for those boxes.  Higher resolution images are needed to approach the accuracy of region-based classifiers.  (Note that a higher resolution image also improves extraction for small objects.)

Edge Inference Architecture and Design

I recently had the opportunity to chat with the team at Flex Logix, who recently announced a product for AI inference at the edge, InferX X1.  Geoff Tate, Flex Logix CEO, shared his insights into how the architecture and design teams collaborated on achieving the product goals.

“We were focused on the optimizing inferences per watt and inferences per dollar for high-density images, such as one to four megapixels.”, Geoff said.  “Inference engine chip cost is strongly dependent on the amount of local SRAM, to store weight coefficients and intermediate layer results – that SRAM capacity is balanced against the power associated with transferring weights and layer data to/from external DRAM.  For power optimization, the goal is to maximize MAC utilization for the neural network – the remaining data movement is overhead.”

For a depiction of the memory requirements associated with different CNN’s and image sizes, Geoff shared the chart below.  The graph shows the maximum memory to store weights and data for network layers n and n+1.

The figure highlights the amount of die area required to integrate sufficient local SRAM for the n/n+1 activation layer evaluation — e.g., 160MB for YOLOv3 and a 2MP image, with the largest activation layer storage of ~67MB.  This memory requirement would not be feasible for a low-cost edge inference solution.

Geoff continued, “We evaluated many design tradeoffs with regards to the storage architecture, such as the amount of local SRAM (improved fps, higher cost) versus the requisite external LPDDR4 capacity and bandwidth (reduced fps, higher power).  We evaluated the MAC architecture appropriate for edge inference – an “ASIC-like’ MAC implementation is needed at the edge, rather than a general-purpose GPU/NPU.  For edge inference on complex CNN’s, the time to reconfigure the hardware is also critical.  Throughout these optimizations, the focus was on supporting advanced one-step algorithms with high pixel count images.”

The final InferX X1 architecture and physical design implementation selected by the Flex Logix team is illustrated in the figure below.

The on-chip SRAM is present in two hierarchies:  (1) distributed locally with clusters of the MAC’s (providing 8×8 or 16×8 computation) to store current weights and layer calculations, and (2) outside the MAC array for future weights.

The MAC’s are clustered into groups of 64.  “The design builds upon the expertise in MAC implementations from our embedded FPGA IP development.”, Geoff indicated.  “However, edge inference is a different calculation, with deterministic data movement patterns known at compile time.  The granularity of general eFPGA support is not required, enabling the architecture to integrate the MAC’s into clusters with distributed SRAM.  Also, with this architecture, the internal MAC array can be reconfigured in less than 2 microseconds.”

Multiple smaller layers can be “fused” into the MAC array for pipelined evaluation, reducing the external DRAM bandwidth – the figure below illustrates two layers in the array (with a ReLU function after the convolution).  Similarly, the external DRAM data is loaded into the chip for the next layer in the background, while the current layer is evaluated.

Geoff provided benchmark data for the InferX X1 design, and shared a screen shot from the InferX X1 compiler (TensorFlowLite), providing detailed performance calculations – see the figure below.

“The compiler and performance modeling tools are available now.”, Geoff indicated.  “Customer samples of InferX X1 and our evaluation board will be available late Q1’2020.”

 

I learned a lot about inference requirements at the edge from my discussion with Geoff.  There’s a plethora of CNN benchmark data available, but edge inference requires laser focus by architecture and design teams on fps, fpW, fp$, and accuracy goals, for one-step algorithms with high pixel images.  As CNN research continues, designs must also be extendible to accommodate new approaches.  The Flex Logix InferX X1 architecture and design teams are addressing those goals.

For more info on InferX X1, please refer to the following link.

-chipguy

 

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Actel Goes Public – The IPO

Actel Goes Public – The IPO
by John East on 09-23-2019 at 6:00 am
Categories: John East
8 Comments

In 1990 Xilinx notified us that they believed Actel was infringing a patent that had just been issued to them.  My immediate thoughts – the patent system is all screwed up!  Actel had been developing our product for five years. We had been shipping it for a year and a half.  During all that time, we were totally unaware that there was or ever would be such a patent —   there was no way to know that Xilinx had filed for a patent or what was in the filing.   Then,  when the patent finally issued  —- BAM!!  We’d been blindsided!!  The “normal” way to handle this situation is to take a license  — to agree to pay a royalty to the owner of the patent.  There was a problem with that.  Bernie Vonderschmitt (The CEO of Xilinx) didn’t want to give any licenses.  I can’t really say that I blame him for wanting to keep the FPGA market to himself.  It was hard to get mad at Bernie.  He was a classy guy.  Yet,  if it had gone to court and Xilinx had won,  they would have been completely within their legal rights to enjoin Actel from shipping our FPGAs.  That would have forced us to close our doors – to shut Actel down.  I spent the better part of three years trying to solve this potentially very, very serious problem.

In those days the rule of thumb was that a start-up could go public once they had achieved two consecutive profitable quarters.  We reached profitability in 1990 and were hot to go public.  We selected bankers  — Goldman Sachs was the bulge-bracket bank  —  and started preparation.  Then, Goldman’s lawyers started to get cold feet.  What if the patent battle couldn’t be settled?  If the worst case came to pass   — that is — we went public, took money from new shareholders, and then had to shut our doors because we had lost the patent suit —   the lawsuits would be everywhere. Eventually we had to put the IPO on hold.  (IPO = Initial Public Offering AKA “going public”.)

I’m not sure that we could have settled the Xilinx patent suit.  Bernie hadn’t shown any interest in doing so.  But then a good break came our way.  Khalid el Ayat found that the early Xilinx parts didn’t use what we called segmented routing but that their later family (the 4000 family) did.  One of our original patents had some claims dealing with segmented routing techniques (thanks Abbas El Gamal,  John Green and team).  That allowed us to file a countersuit against Xilinx.  Calmer minds prevailed.  We settled the suits peacefully.

Note:  Xilinx later sued Altera for infringing that same patent.  They weren’t able to settle and eventually went to trial.  My analysis was that Altera did infringe, but that the patent wasn’t valid over prior art.  The jury eventually ruled that the patent was indeed valid but that Altera didn’t infringe.  In my mind, wrong on both counts.   That’s the reason that you never want to go to a jury trial with a technical issue.  The jury won’t understand it and has an excellent chance of getting it wrong.  This case was very technical.  I doubt that the jury members understood 10% of what they were being told.

Once the Xilinx suit was settled,  our IPO efforts cranked up in full force.  Everything was looking good.  Then we hit another snag.  We had been selling 1.2 micron material, but we needed 1.0 micron product if we were to be cost competitive.  The process was ready to go,  or so we thought,  but the first production runs to come out had terrible yields.  If we couldn’t run the 1.0 process,  we couldn’t compete well cost-wise.  That would have to be disclosed in the IPO documents.  We had to put the IPO on hold for a second time.  Then, we cracked the code.  We figured out the problem and fixed it.  Thanks Steve Chiang!  Thanks Esmat. The IPO was back on.

IPOs are hard work.  Huge amounts of effort go into putting together the documents.  Everything that could end up mattering to a prospective shareholder must be disclosed and explained.  The explanations had to be right.  If the stock went down for any reason other than the market’s fickle nature,  you could expect a lawsuit.  The point of the suit would be that you hadn’t properly disclosed the risk of some aspect of the company and that if you had, the shareholders wouldn’t have bought the stock and hence wouldn’t have lost their money.  I spent many, many, many hours writing those documents. It took a long time and a lot of effort by a lot of people to get the documents ready!  Those documents are a big, big deal!

Once you have the documents done they must be approved by the Security Exchange Commission.  The SEC folks are tough.  They invariably find fault and demand improvements.  Once the SEC has given their approval,  you can start the “road show”.  The point of the road show is to meet with the people who are about to invest and teach them the basics of the company’s business. The road show is grueling.  You present the company pitch over and over and over again.  Breakfast presentations.  Morning one-on-ones.  Lunch presentations.  Afternoon one-on-ones.  Dinner presentations.  Then, you head to the airport, fly to a new city, and do it again.  One day we had a breakfast meeting in Minneapolis, a lunch meeting in Chicago,  a dinner meeting in Madison, and then flew to the east coast where a full day was set up for the following day.  When we landed, Dave Courtney (Our Goldman Sachs guy) had a message that our afternoon meeting the next day had been canceled.  That would mean that we had a couple of hours on our hands.  I suggested that we go see the Liberty Bell  — I had never seen it.  Dave thought that I was really stupid!  “John, the Liberty Bell is in Philadelphia.  We’re in Boston.”  Actually, I knew where the Liberty Bell was.  I just didn’t know where I was.  All the cities had become a blur by then.

A couple of days later in New York we got on a plane at Kennedy Airport and prepared to head home.  We were done!!!  It was a Friday afternoon.  We would celebrate over the weekend – then  – Monday morning when NASDAQ opened  — there would be a new listing:  ACTL.  Has a nice ring to it,  don’t you think?  ACTL!!!!!  Just before I boarded the plane, someone from Goldman brought me a fax that had arrived a few minutes earlier.  I took a sip from the glass of wine that I’d already treated myself to and opened the envelope.  It was a letter from a struggling start-up accusing us of infringing a patent of theirs.  I almost spit out the wine!!!  When I took a quick look at the patent, it wasn’t clear that it really applied to us.  But  — their timing was clearly calculated to get some quick cash from us.  The patent would constitute a new “risk factor” that should be disclosed to all potential investors.  To do that, though, would mean putting the IPO on hold for a third time  — redrafting and reprinting all of the documents, waiting a month or so for the new info to disseminate, going through SEC approval again and then doing the road show all over again.  Devilishly clever timing, don’t you think? But also, in my mind, completely without class.  We were supposed to “price” and open the market Monday morning.  The weekend when I planned to relax and celebrate was shot.  We sorted it out that weekend.  I don’t remember any details, but I’m sure it involved a tidy payment to the very clever offended party.  What I do remember is being really relieved that we had sorted it out.

Monday morning, August 3,1993 when they rang the opening bell*,  Actel stock was trading publicly right along with the likes of Apple and Intel!!  We opened at $9.50 per share.  During the day we ran up to $13.00. We were a public company.

Next week:  The Mars Rovers.

*Actually they don’t ring a bell at NASDAQ.  They just push a button.  It’s the NYSE that rings a bell.  I found that out in 2003 when I was invited to open the market as we celebrated our tenth anniversary of being a public company.  I gave a little speech,  waited a couple of minutes, and when they gave the sign, reached out and pushed a small black button.  Six years in college for that?!!

Pictured:  NASDAQ building at 42nd and Broadway in New York City on the celebration of our tenth year of being listed on NASDAQ.

See the entire John East series HERE.

# Bernie Vonderschmitt, Goldman Sachs, IPO, NASDAQ, Xilinx, Altera, Microchip

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Criminals Luring in Bitcoin Sellers to Launder Money

Criminals Luring in Bitcoin Sellers to Launder Money
by Matthew Rosenquist on 09-22-2019 at 10:00 am
Categories: Security
1 Comment

Cybercriminals are luring in bitcoin holders with the promise of easy money if they become a mule to convert stolen assets into clean currency. The reality is these volunteers will just join the ranks of other victims. But that is not stopping people from joining up to replace other mules who have paid the price.

Criminals are selling cash for pennies on the dollar to buyers willing to trade it for Bitcoin, according to the new Q3 2019 Black Market Report from Armor’s Threat Resistance Unit. A recent Cointelegraph article outlines how $800 in Bitcoin buys $10000 in cash on the Dark Web.

Digital cybercrime is a huge business, accounting for an estimated global cost of $3 trillion in 2015 and predicted to rise to $6 trillion by 2021 according to research from herjavecgroup.com.  A subset of that is monies stolen from victims which criminals want to launder so it cannot be traced back to them.

One of the most popular ways of laundering money is to use a 3rd party to transfer the money through their clean accounts.

For years, criminal outfits have been recruiting dim-witted volunteers to conduct such activities by giving them a percentage of the money they launder. This initially looks like a great opportunity for these volunteers but it is likely the worst decision of their lives.

Mules are a throw-away resource for organized criminals. They are the most exposed point to law enforcement and are often the ones caught. As the mules are purposely insulated from the criminals, they can’t negotiate a lesser sentence by informing who they work for. They are stuck with the burden of the full legal repercussions. The criminals simply recruit new mules to replace the old and leave a trail of discarded minions.

As for the mules who are caught, their future is pretty dark. First, they get arrested for a number of felonies. Supporting organized crime and transporting funds across borders are serious offenses. They should expect prison time. This gives them a lifelong criminal record of financial crime, which will then haunt them any time they seek employment at a company. What business would want to hire a thief? They may be put on travel watch lists, for fear of physically moving cash. The government will seize their assets and they will have to surrender or pay back all illicit profits to the government. Then, the IRS will come for them. Yes, they will still have to pay taxes on all the money they moved, not just their profits. This can be much more then they made being a mule. Those taxes also incur late fees.

Simply put, choosing to become a money mule for easy cash can ruin someone’s life. Doubtful the criminals tell all this in the job recruiting brochure.

It may be tempting, but don’t let yourself, family, or your colleagues be lured into this disaster by the promise of quick cash. Money laundering only helps the criminals and in turn, they will continue to victimize more people, including the mules.

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Forget about 5G

Forget about 5G
by Roger C. Lanctot on 09-20-2019 at 10:00 am
Categories: 5G, Automotive
3 Comments

There is a vast amount of hubbub in the automotive industry regarding the onset of 5G technology. Industry excitement is manifest in the 5G Automotive Association (5GAA) which is facilitating collaboration (among 120+ member) between the automotive industry and the wireless industry, possibly for the first time ever.

For years, cars and connectivity have gone together like fish and bicycles – in other words, not at all. General Motors’ OnStar automatic crash notification was a brilliant idea, but the arrival of the smartphone has almost completely erased any consumer enthusiasm for this application.

But cellular skeptics will be wise to arrest their tut-tutting about the future of connected cars because pre-5G LTE-based connectivity in the form of C-V2X is about to change everyone’s understanding of the value of connecting cars. More than 6,000 pedestrians were killed in traffic-related incidents in 2018 in the U.S., a 40% increase from 2008 and now representing 16% of all U.S. highway fatalities. That’s likely to get worse with the proliferation of micromobility. C-V2X is about to change that grim reality forever.

When Ford Motor Company announced its plans to adopt built-in C-V2X technology in all or most of its cars by 2022, the automotive industry shrugged. Ford had long trailed GM in its implementation of embedded connectivity – relying instead on connected smartphones with its clever SYNC solution created in partnership with Microsoft. Ford even found a way to enable automatic crash notifications from connected smartphones – i.e. 911 assist.

SYNC has since evolved, but so has Ford’s thinking about connectivity. The company’s singular embrace of C-V2X is likely to put the company in the vanguard of a movement to leverage vehicle-to-vehicle technology (enabled by C-V2X) and vehicle-to-pedestrian technology to reduce collisions between cars and between cars and pedestrians.

Enabling cars to “see” pedestrians is something of an industry Holy Grail. We’ve all seen the LiDAR images of pedestrians and even the camera-based and night-vision pedestrian detection systems. All of these modalities hint at the potential to use sensors to avoid collisions with pedestrians.

C-V2X, however, will enable so-equipped cars to detect the presence of pedestrians by “detecting” their C-V2X (or 5G enabled) smartphones. As C-V2X proliferates through mobile devices and, eventually, in cars, vehicles will increasingly be able to detect other vehicles and pedestrians.

This ability will initially manifest as driver alerts in dashboard-based systems such as the instrument cluster or infotainment system or even in head-up displays. Eventually, in-vehicle systems will be able to respond automatically, braking or taking other evasive action to avoid collisions.

Qualcomm will be holding an Automotive Showcase next Tuesday, Sept. 24, at the NextEnergy Center in Detroit, Mich., to demonstrate the capabilities inherent in C-V2X technology and explore new life-saving applications. There is no doubt that 5G, when it arrives in the U.S., will have its own transformative impact on vehicle technology development and deployment, but C-V2X will arrive even sooner in cars and in mobile devices.

Gil-Scott Heron was wrong. This revolution WILL be televised…in your dashboard.

Register for the Qualcomm Automotive Showcase here: https://tinyurl.com/yxawjuse

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Chapter Eleven – International Semiconductor Competition

Chapter Eleven – International Semiconductor Competition
by Wally Rhines on 09-20-2019 at 6:00 am
Categories: Wally Rhines
6 Comments

Semiconductor industry evolution was largely a U.S. phenomenon.  While there were important contributions made by persons all over the world, the basic technology grew from the invention of the transistor at Bell Labs which was licensed broadly in the U.S.  That created a level playing field for all who wanted to become producers.  The industry then evolved in a free market environment in the U.S. largely without regulation or patent disputes. By 1965, three companies, TI, Motorola and Fairchild, had a combined market share greater than two thirds of worldwide sales of semiconductors (Figure 7, Chapter Five). Barriers to the internationalization of the industry emerged through import tariffs in Europe and restrictions on setting up subsidiaries in Japan but even these limitations gradually disappeared.

After 1965, the semiconductor industry began a near continuous deconsolidation as new companies entered the market.  The market share of the largest competitor remained about the same for the next fifty-five years at 12 to 15% (Figures 7 and 8 in Chapter Five). Top ten semiconductor companies during the 1950s and 1960s did not include any non-U.S. companies (Figure 10, Chapter Five).

Japan Becomes a Significant Competitor
In the late 1970s and early 1980s, the industry became international with the entry of NEC, Toshiba, Hitachi and Matsushita into the list of the top 10 largest semiconductor companies. Philips, a European semiconductor company, also entered the top ten for the first time. The Japanese phenomenon was driven largely by the superior manufacturing process control applied to dynamic RAMs, or DRAMs.  This was the first wave of “trade wars”.  The Japanese Ministry of Industry and Trade, MITI, coordinated actions among Japanese companies that contributed to a cooling of tensions between SIA (U.S. Semiconductor Industry Association) and EIAJ (Electronics Industry Association of Japan).  Japanese companies were assigned quotas for purchases of semiconductors from U.S. companies, relieving some of the pressure.  The real end to the issue was predictable but not so obvious to many of us.  At a dinner I had with Saturo Ito, CEO of Hitachi Semiconductor, in the late 1980s, he explained to me that the U.S. shouldn’t worry about Japan taking over most of the manufacturing of semiconductors in the world, as I had feared.  Ito told me, “Japanese are optimizers, not inventors.  When standards are stable, Japan will do well.  When standards are evolving, not so well.”  He was right.  As the personal computer and cell phone industries grew, the U.S. recaptured substantial innovation momentum.

Enter Korea
Less predictable than the Japanese success in DRAM manufacturing was the entry of Korea.  When Samsung announced its intent to design and produce the 64K DRAM and sent their managers on a 64-mile hike as a symbolic start, we didn’t pay much attention.  How could they catch up in an industry that was so mature?

Their success came from the determination of Koreans when they decide upon a specific goal.  The path was not easy.  As late as 2008, the combined market share of the three largest DRAM producers in the world, Samsung, SK Hynix and Micron, was only modestly greater than 50% of the entire worldwide market.  Today, their combined market share is greater than 95% (Figure 6 of Chapter Five).

Taiwan
As with Japan, Korea and China, Asian governments understood very early the importance of domestic semiconductor capability.  Evolution of worldwide leadership in the silicon foundry business by Taiwan is truly remarkable. The Taiwanese semiconductor industry grew from a team of Taiwanese engineers who went to work for RCA in the late 1970s.  These individuals were very talented.  They started many semiconductor companies when they returned to Taiwan.  When the Taiwanese government formed ITRI and ERSO to promote advanced development in Taiwan, the country was fortunate to have Morris Chang, former head of TI’s semiconductor business, available to move to Taiwan to head up these two entities.  When TSMC and UMC were formed, Morris filled the role of Chairman of both.  Securing funding from Philips, he was able to take advantage of an unlikely transition of the semiconductor industry.  Those of us in the industry at the time wondered how a company whose business consisted only of wafer fabrication could ever survive.  Those of us working for integrated device manufacturers like TI viewed wafer fabs as our biggest problem.  Whenever a recession came along, the fabs became under-loaded and were astoundingly unprofitable.  The depreciation cost continued but the revenue did not.  If someone else was willing to take over the wafer fabs, then the semiconductor business volatility would be reduced making it a more attractive, stable industry. The U.S. had already experienced the pain of wafer fab ownership when Japanese competitors in the 1985 recession kept running wafers at a loss, partly because they couldn’t lay off their people.  In the U.S. we shut down some of our wafer fabs to stop the financial bleeding.  Step by step we created an opportunity for Japan to gain market share when the recovery inevitably came. Now TSMC and UMC in Taiwan were taking over the one aspect of the industry that caused us the greatest pain.

TSMC recognized the value of being a dedicated foundry with no products of its own to compete with its customers, unlike its competitors such as UMC, Seiko Epson, NEC and more.  By becoming a pure play foundry and popularizing its design rules, TSMC gained momentum that was hard to match.  Today, only Samsung comes close to providing real competition at the leading edge of semiconductor technology.

This leaves the U.S. in the interesting position that, other than Intel plus some limited capacity in Texas and New York, there is no significant domestic manufacturing capability at the advanced nodes of semiconductor technology. Anything that disrupts free trade between Taiwan and the U.S. could severely disrupt much of the U.S. manufacturing and defense industries.

China
Despite China’s rise as the world’s largest assembler of consumer electronic equipment, the Chinese semiconductor industry has evolved slowly. The largest Chinese semiconductor foundry, SMIC, is still two technology nodes behind TSMC in manufacturing capability as of 2019.

The Chinese government is dedicated to changing this situation.  Figure 1 shows the investment that is being made.

Figure 1.  Chinese government stimulus for semiconductor investment has been matched by a much greater investment by private equity companies

These numbers dwarf anything that the U.S. government is likely to do.  The entire annual revenue of the worldwide semiconductor industry is less than $500 billion.  The Chinese government is investing more than $20 billion per year.  They are doing it in an insightful way.  The money is invested as a share of private equity companies who are motivated to invest in semiconductor companies that can make an attractive return on the investment.  Many of the startup companies have an optimistic outlook because the Chinese population of over one billion people can drive its own standards for communications and computing.

How well have they done with the investment?  Figure 2 shows a comparison of the size of the semiconductor companies that have benefited from the investment.

Figure 2.  Growth of Chinese fabless semiconductor companies

Average employment of the semiconductor companies in China has grown between 2006 and 2015.  The number of companies with more than five hundred employees in 2006 was less than one half of one percent. In 2015, it was 6.1%.  The number of Chinese fabless semiconductor companies that had between 100 and 500 employees in 2006 was 9.8%.  In 2015, it was 43.3%.  This growth provides a challenge for semiconductor competitors in the rest of the world including the U.S. where governments can’t afford to provide the kind of subsidies that are available in China.  Even so, the problem was manageable with innovative U.S. companies operating in a semi-free market environment for creating new technologies.  The U.S., however, created a “Sputnik moment” for China that may have changed the outlook.

Historical Perspective of Export Controls
In 1982, I joined the Technical Advisory Committee of the Department of Commerce that was set up to advise the Department regarding the granting of validated licenses for export of semiconductors and semiconductor manufacturing equipment.  Soon I became Chairman of the committee.  In the 1970s, U.S. companies like Applied Materials, Lam Research, Novellus, Varian and many more dominated the worldwide semiconductor manufacturing equipment business.  Japanese companies like TEL were growing but their base of customers was largely in Japan.  The Export Administration Act of 1979 was one of the contributing factors that changed that competitive situation. Concern about the military implications of semiconductor capability led to a set of restrictions on semiconductor related exports from the U.S. and its allies to controlled destinations that were enemies of the free world.

Allies like Japan were much more efficient at administration of bureaucratic export control rules.  Validated licenses for customers of Japanese manufacturers could reliably be obtained in three days plus or minus a day or two.  For the U.S., the time and the variability were much greater.  Companies in places like Taiwan rightly concluded that the U.S. could not be trusted as a supplier because spare parts and user manuals also required separate validated licenses.  Market share of U.S. companies in the semiconductor manufacturing equipment industry fell from more than 4X Japan’s market share in 1980 to about equal shares for Japan and the U.S. in 1990. In a sense, the U.S. moved toward a role as the “vendor of last resort” for semiconductor manufacturing equipment sold to controlled destinations and probably even to some destinations that were COCOM allies.

China’s Sputnik Moment
ZTE clearly violated internationally accepted export restrictions on Iran.  The U.S. reaction was not totally unexpected.  What surprised the world was the swift action taken to shut down the free market purchase of semiconductor components.  The degree of dependence that ZTE had developed upon U.S. semiconductor suppliers made this a life or death issue for the company.  President Trump ultimately waived the export restrictions. Although the embargo was lifted, the impact of the threat was now apparent to China.  Dependence upon U.S. suppliers of semiconductors was no longer a viable strategy.

As the Chinese government continued its move toward dictatorship, rules were imposed upon foreign companies for the opportunity to establish operations in China. Google was prevented from operating in China, as were others. These restrictions became increasingly egregious (such as the threat that U.S. software companies might have to turn over their source code to the Chinese government if they wished to operate in China). As frictions developed in the trade negotiations between the U.S. and China, a U.S. decision was made to embargo exports to Huawei by placing Huawei on the “entity list”. This created an even more untenable situation for China, the worldwide leader in wireless communication technology.

China did the expected.  They focused upon developing non-U.S. capabilities for all their components.  Since China buys more than 50% of all semiconductor components in the world, this is a big problem for the U.S. semiconductor industry.  It is probably not reversible.

Another question is whether other countries will follow suit out of fear that political disagreements with the U.S. could result in an embargo of semiconductor components from U.S. suppliers. As with the Export Administration Act, events in China will lead to a reduction in market share of U.S. based semiconductor suppliers and a loss of their lead in many new technologies.

How long will it take for China to eliminate its dependence upon U.S. semiconductor suppliers?  Probably many years, especially for FPGAs and RF components, and it may never be achieved.  China’s demand is so large that non-U.S. suppliers will probably find a way, given enough time, to displace U.S. suppliers but it’s hard for any country to become totally self-sufficient.  In addition, China’s move toward a closed, controlled society will restrict innovation. That will work to the advantage of the U.S.

While China’s direction is not likely to change, we still have the possibility of convincing the rest of the world that the U.S. can be treated as a reliable supplier.  Hopefully, there will be policies articulated by  the U.S. that convey that confidence and restore the U.S. position as a leader in free trade.

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Is Samsung having problems with 7NM? Do long lines at TSMC prove that?

Is Samsung having problems with 7NM? Do long lines at TSMC prove that?
by Robert Maire on 09-19-2019 at 2:00 pm
Categories: Semiconductor Advisors, Semiconductor Services
4 Comments

Reports of increasing TSMC 7NM lead times
There have been a number of increasing media reports about lengthening leads times for TSMC 7NM process. From what we have been able to determine its not due to TSMC having a yield bust or other production issues, it is simply one of stronger than expected demand.

There have been reports of up to 6 month lead time quotes which is untenable for companies that need to keep releasing newer, faster, better versions of products to stay ahead of the pack or at least keep up with the pack.

This begs the question as to whats happening in the leading edge foundry market? Normally there is some sort of balance between TSMC and Samsung with each taking a portion of leading edge business and customers, such as Qualcomm, like it that way so they are not dependent upon one supplier who would otherwise have them over a barrel.

Or are they??

Samsung 7NM yield problems?
It sounds as if Samsung is having yield issues at 7NM. This may be a repeat of Samsung’s 10NM which was prematurely pre-announced and then fell flat. If foundry customers can’t get yield from Samsung then TSMC is the only 7NM game in town and the lines will be out the door (like they apparently are…).

With GloFo dead and everyone else years behind, TSMC may be opening up an unstoppable lead.

Is EUV the culprit?
Samsung has been very aggressive in pushing EUV , in their foundry operations, and suggesting they had the lead in EUV and their designs would be far superior.

Samsung was obviously trying to tweak Apple into re-considering using their “frenemy” Samsung as a foundry ever since Apple dropped them.  Apple has had a high interest in EUV due to potential power savings and other benefits.

It seems as if Samsung may have bit off more than they could chew and the aggressive use of EUV for more layers may be the cause of the yield problems.  They were basically pushing something that was not yet ready for prime time.

Its going to be both hard and embarrassing to reverse course and reduce EUV use now to get yields back up….not pretty.

Maybe Intel is smarter than we think for go slow on EUV
Intel has been slower than both TSMC & Samsung in the adoption of EUV.  Perhaps its because of being gun shy after the 10NM debacle or perhaps they understood the challenges better.

It may turn out that go slow on EUV may have reduced the risk of another yield black eye, which Samsung may be dealing with now.

TSMC is the only game in foundry town
TSMC has been all but unstoppable. They have kept up the Moore’s law cadence without a hiccup and recently said that Moore’s law has a long life ahead of it. If customers want bleeding edge chip performance there is clearly one game in town.

TSMC should be able to make bank on this advantage in the market. Now just with 7NM but future generations as well as more customers will sign up for 6NM, 5NM and beyond.

Customers of Samsung will have to pay up big time when they go to TSMC to get devices foundered. This just accelerates the move to TSMC that was already occurring but turns it more into a stampede

Collateral Damage & Benefit

ASML
Obviously if EUV is finally revealed to be the issue it would be a large negative for ASML from a PR perspective.  From an actual P&L perspective I think there would be minimal damage as ASML is sold out on EUV any way.

EUV is absolutely inevitable but it was clearly very difficult and long to get machines built and just as hard to get the process to work. ASML can still point to TSMC’s success and Intel’s future success and probably shift the blame to Samsung.

Its unclear where the yield issues may specifically be and we may never know for sure….just like Intel at 10NM

Apple is safe
Apple has been TSMC’s BFF for a number of nodes now and they are fully signed on with TSMC and TSMC will bend over backwards to get Apple al the chips it needs, so no problem here. They have a permanent pass at the velvet rope.

AMD also in good shape
AMD threw all its eggs into TSMC’s basket, and while not nearly as big as Apple or others, they are clearly a friend of TSMC. They have also signed on for wafer production so they already have secured their place in line.

The only issue here is that if AMD has huge share gains against Intel they may be supply limited as they likely signed up for a specific amount of production which was probably a conservative number.

Qualcomm has a problem
Qualcomm is or was the most significant customer of Samsung, trying to split the business with TSMC to diversify supply and play them off against one another. Now they have to go back to TSMC and get on the end of the 7NM line and probably pay a premium to boot. Not a good place to be right now especially with the hypercritical roll out of 5G coming up right now.

Qualcomm has absolutely no choice but to pay whatever TSMC demands and sign up for whatever TSMC wants.  The timing couldn’t be worse for them. The Samsung yield issue could cause a major problem for Qualcomm’s on time roll out of 5G. I would imagine that Qualcomm might think twice about risking future production with Samsung.

While investors are all excited about 5G, a delay could be a big blow which could cause a drop in the stock especially if they had to announce it.  We would consider being light or short the stock if this pans out.

Broadcom is happy
As both a customer and friend of TSMC , Broadcom has no problems and obviously could benefit at Qualcomm’s problems if Qualcomm can’t get new 7NM parts in a timely manner.  Broadcom does not have a significant Samsung exposure so little downside.

Intel could use FUD factor against AMD
Although Intel gets no direct impact either way they could try to put the FUD (fear, uncertainty & doubt) factor into customers minds who can choose between AMD and Intel by questioning AMD’s ability to deliver based on growing TSMC lead times.  We don’t see this as a real issue but it could cause problems.

Samsung
Obviously Samsung is already suffering under poor memory pricing with the prospects of a very slow memory recovery.  The foundry side of the business did not account for a lot of external revenue, especially when compared to memory but none the less it would be a further blow to Samsung’s revenue coming at a very bad time given that semiconductor sales is the vast majority of Samsung’s profits. This is of course not to mention that Samsung makes its own processors for its phones whose supply could also be at risk.

This is on top of the risk of supply of semiconductor materials from Japan that are threatened to be cut off. A yield problem at 7NM is the last thing Samsung needs right now.

This of course adds to the probability that Samsung’s spending will remain low as they now have even less semiconductor revenue to pour back into their fabs.

Not pretty at all….maybe a “short”

KLA
Given that KLA specializes in yield management and increasing yield and finding problems it could benefit from any added spending to find and fix the problems as well as prevent future problems.

Nothing helps the sale of process monitoring equipment like a good yield bust…..

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Speeding Up Physical Failure Analysis (PFA)

Speeding Up Physical Failure Analysis (PFA)
by Daniel Payne on 09-19-2019 at 10:00 am
Categories: EDA, Siemens EDA

Mentor - design defect

The cost of an IC depends on many factors like: NRE, masks, fabrication, testing, packaging. Product engineers are tasked with testing each part and understanding what exactly is limiting the yields. Every company has a methodology for Physical Failure Analysis (PFA), and the challenge is to make this process as quick as possible, because time is money especially when using testers that can cost millions of dollars.

Volume scan diagnostics is a popular method for creating defect paretos and plotting yield, and the larger the sampling size the better the accuracy. There are many challenges for product engineers these days:

  • Larger design sizes slow down testing
  • New process nodes have new failure mechanisms
  • Cell-aware diagnosis takes more time
  • Compute resources are growing

Let’s take a closer look at what happens during volume scan diagnosis; a design netlist is read into a simulator along with scan patterns and the log from a failing chip. To handle multiple fail logs quickly the diagnosis is simulated in parallel across a grid of computers.

With large designs there can be practical computational limits to scan diagnosis, so let’s assume that your design takes 100GB of RAM and requires an hour for each diagnosis. If your compute grid has 11 machines as shown below:

Only Machine 1 has enough RAM to fit the design and with 2 parallel jobs it will diagnose only 48 results per day. Machines 2-11 don’t have enough RAM to fit the design, so they remain idle.

The actual diagnosis throughput can be described as an equation that depends on how much diagnosis memory and diagnostic time is required.

To shorten the diagnosis throughput requires that we somehow reduce the memory and time requirements, and it turns out that a technique called Dynamic Partitioning as used in the Tessent Diagnosis tool from Mentor does this.

In the following figure we see a design fragment with three scan chains, and a defect is found in the top logic cloud which then causes two scan bits to fail in the second scan chain shown as red logic values. Using dynamic partitioning only this design fragment needs to be simulated by Tessent Diagnosis, thus requiring much less RAM than a full netlist.

Here’s the smaller partition that needs to be simulated:

With Tessent Diagnosis Server all of the dynamic partitioning is automated and it works with your compute grid setup, like LSF, so that run times are minimized.

You can even choose the number of partitioners and analyzers to be used on your grid, where the partitioners automatically create dynamic partitions for diagnosis and analyzers do the diagnosis on the smaller partitions.

Let’s go back to the first test case and this time apply dynamic partitioning:

With dynamic partitioning the diagnosis throughput jumps from 48 results/day up to 528 results/day because all 11 machines can be utilized in parallel. Two test cases from actual designs show throughput improvements between 11X and 16X faster by using dynamic partitioning:

When using dynamic partitioning there’s no change in the quality of the scan diagnosis result, you just get back results much quicker from your compute grid using less RAM.

Summary

Divide and conquer is a proven approach to simplifying EDA problems and for product engineers doing PFA there’s some welcome relief in improving throughput based on dynamic partitioning technology. The old adage, “Work smarter, not harder”, applies again in this case because you can now use your compute grid more efficiently to shorten volume scan diagnosis.

Read the complete 6 page White Paper online, after a short registration process.

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WEBINAR: AI-Powered Automated Timing Arc Prediction for AMS IP’s

WEBINAR: AI-Powered Automated Timing Arc Prediction for AMS IP’s
by Daniel Nenni on 09-19-2019 at 6:00 am
Categories: EDA, Empyrean

A directed approach to reduce Risk and improve Quality

Safety and reliability are critical for most applications of integrated circuits (ICs) today. Even more so when they serve markets like ADAS, autonomous driving, healthcare and aeronautics where they are paramount. Safety and reliability transcend all levels of an integrated circuit and the quality of timing definition at every level plays a critical role in ensuring them. Every integrated circuit, small or big, uses from tens of IP’s to hundreds of them. Proper timing behavior of every component is key to the overall safety and reliability of the IC and the system the IC goes into. Creating a comprehensive set of timing arcs for the IPs is an essential component of its quality metric and ensures better safety and reliability in the end applications of the IP. It also plays a key role in the reduction of a variety of risk factors for the IP and the IC it goes into.

Timing arc generation for digital IPs is well understood and is automated. The same is not true for the analog and AMS IP’s. Timing arc generation for analog and AMS IP’s is manual. In addition, IPs get integrated into many applications beyond what an IP designer designed his/her IP for. It relies on the designer’s expertise to not miss an arc. How can you trust the SoCs that make use of such analog and AMS IP’s created using error prone methods for mission-critical applications like autonomous driving, aeronautics, healthcare? An AI-powered methodology that allows the generation of a comprehensive set of timing arcs analog/AMS IP’s – high quality and low risk – is essential for their use on mission-critical applications.

Integration of analog or AMS IP into a SoC is challenging and the larger the IP, the greater is the challenge. With analog designs being sensitive to layout, proximity and matching, the impact on timing is direct and typically ranges from delayed tape-out to silicon failure, and multiple silicon iterations.

Thanks to recent advances in artificial intelligence (AI) and machine learning (ML), automation of the timing arc generation for analog and AMS IP’s is becoming a reality. Empyrean Software, working with some key customers has taken the lead to develop the automation of timing arc creation for analog and AMS IP’s. A joint paper, Machine Learning based Timing Arc Prediction for AMS Design, with a customer (NVIDIA) was presented at the “Designer Track” of the most recent Design Automation Conference (DAC 2019) in Las Vegas, Nevada.

A webinar titled, “Reduce Risk and Improve Quality of AMS IP’s using AI-Powered Automated Timing Arc Prediction,” will focus on the new AI-powered automated timing arc prediction and validation capability, the first commercial capability of its kind for IPs. It will talk about the motivation., technology and a methodology for using AI-powered automated timing arc prediction. The 30-minute webinar is scheduled for September 24th at 10:00 am (PST) and you can register to attend and get access to the presentation.

About Empyrean Software
Empyrean Software provides electronic design automation (EDA) software, design IPs and design services, including analog and mixed-signal IC design solutions, SoC design optimization solutions, and Flat Panel Design (FPD) solutions and customized consulting services.

Empyrean Software is the largest EDA software provider in China, and its research and development team has more than 30 years of experience in technology and product development. Our company has comprehensive cooperation with many corporations, universities and research laboratories.

Empyrean’s core values are dedication, collaboration, innovation, and professionalism. Our company is committed to working with customers and partners through win-win collaboration to achieve our common goals.