Intel Will Again Compete With TSMC

Intel Will Again Compete With TSMC
by Daniel Nenni on 03-23-2021 at 2:00 pm
Categories: Foundries, Intel Foundry
24 Comments

New Intel CEO Pat Gelsinger is not wasting any time in changing the course of the largest semiconductor company the world has ever seen. Today he announced the IDM 2.0 strategy which will better leverage Intel’s manufacturing abilities. There is a lot to talk about here but let’s focus on the new Intel Foundry Services because the mainstream media will have no idea what this really means and I am one of the only people with a website who can explain it.

IDM 2.0 is the Powerful Combination of Intel’s Internal Factory Network, Third-party Capacity and New Intel Foundry Services

Intel has dabbled in the foundry business on multiple occasions throughout the years but the biggest push was Intel Custom Foundry in 2014 . Unfortunately, the Intel Custom Foundry strategy was very critical of the pure-play foundry business model which did not go over well with the fabless semiconductor ecosystem, not even close.

In fact, looking back, it reminds me of the famous sleeping giant quote: “I fear all we have done is to awaken a sleeping giant and fill him with a terrible resolve”. The sleeping giant is the fabless semiconductor ecosystem of course.

On a side note: TSMC already shared their thoughts on this with Mark Liu’s IEDM keynote: Unleashing the Future of Innovation which speaks to the downside of IDM foundries.

Per today’s press release:

“Building a world-class foundry business, Intel Foundry Services

Building a world-class foundry business, Intel Foundry Services. Intel announced plans to become a major provider of U.S.– and Europe-based foundry capacity to serve the incredible global demand for semiconductor manufacturing. To deliver this vision, Intel is establishing a new standalone business unit, Intel Foundry Services (IFS), led by semiconductor industry veteran Dr. Randhir Thakur, who will report directly to Gelsinger. IFS will be differentiated from other foundry offerings with a combination of leading-edge process technology and packaging, committed capacity in the U.S. and Europe, and a world-class IP portfolio for customers, including x86 cores as well as ARM and RISC-V ecosystem IPs. Gelsinger noted that Intel’s foundry plans have already received strong enthusiasm and statements of support from across the industry.

I am one of the above mentioned supporters from across the industry. Competition is critical in the semiconductor industry as with any other industry that relies on innovation and pricing. Intel can easily replace Samsung as the #2 foundry based on the US and UK fab locations alone given the semiconductor supply chain issues we are seeing today.

But it’s not as easy as it sounds and there are many potential pitfalls. First and foremost is the support of the giant fabless semiconductor ecosystem. It will be interesting to see how Intel goes about this. Personally, I would go all-in-it-to-win-it and start writing some very big, very strategic checks. Acquisitions will be key here as well as partnerships.

Another pitfall is trust. This has been a serious problem for Samsung even after they “spun off” the foundry business. Capacity and delivery for customers has always been a sticking point for IDM foundries starting with the early days of the fabless business where IDMs auctioned off their excess fab space while they had it. When they didn’t have it the fabless customers were out of luck.

Another trust issue is competing with customers. Today’s systems companies are the fastest growing fabless customers (Apple et al) and who is one of the biggest systems companies in the world? Samsung. Which is why the majority of Samsung Foundry customers are chip only companies. Word to the wise for Intel Foundry Services do not compete with customers.

The other piece of advice I have for Intel Foundry Services is to speak softly and carry a big stick, which is the opposite of what Intel Custom Foundry did. This also goes to trust. The semiconductor industry is filled with highly intelligent people who do not suffer fools gladly. And speaking of that, Intel please change your process node names to better align with the ecosystem. Us highly intelligent semiconductor people really feel strongly about this, absolutely.

I’m over 600 words so let’s talk more in the comments section.

Podcast EP12: A Close Look at Intel with Stacy Rasgon

March 23, 2021March 25, 2022

Observation Scan Solves ISO 26262 In-System Test Issues

Observation Scan Solves ISO 26262 In-System Test Issues
by Tom Simon on 03-23-2021 at 10:00 am
Categories: Automotive, EDA, Siemens EDA
1 Comment

Automotive electronic content has been growing at an accelerating pace, along with a shift from infotainment toward mission critical functions such as traction control, safety systems, engine control, autonomous driving, etc. The ISO 26262 automotive electronics safety standard evolved to help ensure that these systems operate safely. There are four safety levels, ASIL-A though ASIL-D that help determine what level of safety features need to be implemented in a system. ASIL-A applies to a system where failure would only be a nuisance, ASIL-D is applied for systems where failure could lead to death.

In ISO 26262 there are requirements for detecting faults in the running systems. The goal is to detect a fault and return the system to a safe state before a hazardous event would occur. In normal operation a fault can occur at any time and the system must be periodically checking for them. The time between when a fault occurs and when it is detected is called the Diagnostic Time Interval (DTI). After a fault is detected the time until it is corrected and the system is returned to a safe state is called the Fault Reaction Time Interval (FRTI). The sum of the DTI and FRTI must not exceed the Fault Tolerate Time Interval (FTTI), which is the time until a hazardous event would occur.

It is easy to tell that the Diagnostic Time Interval needs to be as short as possible, especially when the Fault Reaction Time is longer and/or the Fault Tolerant Time Interval is short. The technique of Logic Built in Self-Test (LBIST) is used to diagnose systems for failures during operation. The running system, or portions of it, are taken offline and LBIST is run in real-time to look for faults. It is essential that the tests run quickly and have high coverage to meet the ISO 26262 requirements.

Siemens EDA has written a white paper titled “Tessent LogicBIST with Observation Scan Technology” that discusses the considerations involved with running LBIST for In System Test (IST). ISO 26262’s ASIL-D safety level calls for 90% stuck-at fault detection. However, in many automotive systems only around 5 to 50 milliseconds is provided for running LBIST patterns. When using traditional scan chain methodologies, it can be difficult to reach the required coverage. Siemens EDA’s Tessent LogicBIST offers Observation Scan Technology, which adds observation points in the design that can be captured by dedicated observation scan chain scan flops. These observation scan flops can capture faults at every shift cycle.

Observation scan for ISO 26262

These observation scan-flops can be shared with multiple observation test points to save silicon area. The observation scan chains are continuously shifted into the compactor which drives MISR signature generation. The observation scan chains are also shared with traditional LBIST scan chains, delivering responses once the entire test pattern has been shifted-in.

The Siemens EDA white paper describes the options available for placing the observation test points and how the modified scan cells operate. The overall flow is very similar to the typical LBIST flow. The Tessent Shell is used to create RTL based test logic and allows for a single pass flow for the gate level logic insertion.

The white paper includes a section on measured results comparing LBIST with and without observation scan technology. They ran tests on 10 designs ranging in size from 1M to 14M gates, with 44K-900K scan cells, and 200 – 3,200 scan chains. They considered three scenarios, baseline test coverage with no test points, using traditional test points and finally with the addition of observation test points. Test coverage went up significantly when observation test points were added, increasing by 7% to 27% with their addition.

As impressive as the coverage results were, the reduction in pattern count is the real story here. To reach 90% test coverage using observation scan used anywhere from 3X to 16X fewer patterns across the designs they looked at. The average reduction was around 10X. At the same time the silicon overhead for test points was reduced from 2% to 0.5% of the chip.

Siemens EDA talks about some very compelling technology that should make meeting the design goals of ISO 26262 much easier. Without pattern count reductions performing in-system test to get 90% stuck-at fault coverage will be impractical or difficult. The white paper discusses the flow and the specifics of the methodology in more detail. The full white paper can be downloaded from the Siemens EDA website.

Also Read:

Siemens EDA wants to help you engineer a smarter future faster

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March 23, 2021March 16, 2022

The Electromagnetic Solution Buyer’s Guide

The Electromagnetic Solution Buyer’s Guide
by Jim DeLap on 03-23-2021 at 6:00 am
Categories: Ansys, Inc., EDA

So you’ve decided to buy a new car? First you need to research, compare, and test drive before you finally get to drive that shiny new car home. Engineering teams choosing their preferred electromagnetic analysis tool face similar challenges. Historically, electromagnetic problems and analysis tools were relegated to a few “gurus” within an organization, however, more recently, tools are becoming more automated and easily used by the entire electrical engineering design team.

When exploring options for electromagnetic solutions, one of the first criteria for comparison is to look at the latest model. You wouldn’t compare the features and capabilities of the latest SUV with that of a five- or ten-year-old model. The latest SUV has all the best safety features, performance, and efficiency features that are just not present in older models. The same is true for analysis tools. The latest versions of electromagnetic solvers use current numerical methods for matrix solutions, the latest in meshing technology, as well as the most efficient use of HPC resources. Along with the latest version, it helps to be using the best known methods for setting up a design. Just like you no longer change out the spark plugs every tune up like you used to do to your 1976 Plymouth Duster, conditions that used to be “rules of thumb” when you used the tool back in college evolve over time, and some best-known methods turn out to be counterintuitive, or even counter to your previous practices. Check out this article discussing some of the best methods for Ansys HFSS.

One of the main selection criteria for EM solvers is how fast you get your answer, so that includes model setup and definition, analysis setup, solve, and post-processing. For the solve piece of that decision, you should make sure you’re using the same set of compute resources to run all your solutions. Whether you use existing company “on-premise” compute hardware or you are accessing cloud resources, it’s best to make sure you are performing an apples-to-apples comparison. This is just like taking those competing SUVs for test drives on the same roads. You want to see how they’re going to perform whether running errands in the city or commuting to the office on the highway.

One last consideration when making comparisons between electromagnetic solvers, and cars, is their efficiency, or how well they utilize resources. There are times where you may be limited to certain hardware resources inside your company environment, but with cloud resources readily available, it’s important to understand how much faster you could design if those constraints were removed. For Ansys HFSS, it’s a simple matter of choosing Ansys Cloud for the job submission, and you are open to almost unlimited possibilities. An example of solving an automotive radar array module is shown in the images. By using the cloud resources, this model solved almost five times faster. To read about these possibilities using Ansys HFSS in the Ansys Cloud powered by Microsoft Azure, check out this Microsoft post.

Automotive Radar Antenna Array Module

Automotive Radar Antenna Array Simulation Performance

Just as you have to research, compare, and test drive that new car before you get to enjoy the benefits, so should you take your electromagnetic solver out for a test drive. When you use the latest version combined with the best-known methods for problem setup and solve, combined with the virtually unlimited power of HPC with the Ansys Cloud, you will find that HFSS shines brighter than others in the industry. To find out more about HFSS, please find more information here, or join the world’s largest engineering simulation event, Ansys Simulation World.

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March 22, 2021March 25, 2022

Siemens EDA Wants to Help you Engineer a Smarter Future Faster

Siemens EDA Wants to Help you Engineer a Smarter Future Faster
by Daniel Nenni on 03-22-2021 at 10:00 am
Categories: EDA, Siemens EDA

In case you missed it earlier this year, Mentor Graphics the oldest EDA brand officially changed its name to Siemens EDA and launched a new website under its parent Siemens Digital Industries Software.

Under Siemens Digital Industries Software, Siemens EDA adds IC, advanced IC packaging and PCB systems design, verification/validation and manufacturing tools to Siemens Digital Industries Software’s line of Product Lifecycle Management (PLM) tools – a mix of mechanical engineering design and simulation technologies and end-product and manufacturing/factory-automation software built to improve product design as well as the processes for how products are manufactured.

The merging of the EDA and PLM worlds under Siemens Digital Industries Software comes at a seemingly opportune time, where several megatrends in electronics are converging.

From an IC perspective, an increasing percentage of systems companies are beginning to develop their own complex ICs for their end systems, and they are increasingly adding various forms of artificial intelligence and wireless communications to these ICs. This gives the systems companies a competitive advantage and allows them to leverage the data generated by the use of their products to monetize the data as well as to improve the quality and reliability of their products.

From a PLM perspective, an increasing number of customers are either just now making the jump to digitalization or making their digitalization more robust. Digitalization in a factory application, for example, means ensuring factory equipment from disparate vendors are connected and work together seamlessly and that a factory’s output can be monitored to achieve new levels of efficiency and safety – thus profitability. Digitalization also means that these factories can then, in turn, connect more closely with their supply chain, if in fact the suppliers also have a robust digital infrastructure.

You can see where this is going if you think of the trends not only toward smart, connected everything/IoT and monetizing big data, but also autonomous vehicles, smart factories, smart infrastructure and smart cities. Systems companies and their suppliers, including semiconductor vendors, are starting to develop a system of systems mindset. The real end-system isn’t just the IC, or the packaged IC, or PCB, the embedded software, or the ECU or even the autonomous automobile. The system will eventually be all that connected to the smart communications infrastructure. And at all levels, safety and security will be imperative and need to be verified, validated and tested individually and running together.

That’s where Siemens Digital Industries Software purports to have a differentiated offering and a lead over its key rivals – those providing technical software to industry that compete in only one or two domains. Siemens Digital Industries Software provides technical software and services in the greater PLM, IC, PCB and Systems Software markets and it also has offerings in areas like IoT Platforms, Application Lifecycle management, embedded software and Low-code markets. The combined offering and related services are marketed as its “Xcelerator Portfolio.”

Expanding the EDA landscape

Viewed solely through the lens as a pure-play EDA vendor and three years after Siemens announced the acquisition of Mentor Graphics, Siemens EDA still remains the third largest player in the EDA market. Like its competitors in EDA, Siemens EDA continues by all public reports to increase its revenue year over year, despite not having an IP business, which remains a sizable percentage of both Synopsys’ and Cadence’s reported EDA revenue. Maintaining a growing revenue record is no small feat considering most acquired companies typically see their revenue fall after an acquisition.

Certainly one of the main reasons for this growth is that Siemens has continued to invest heavily in Siemens EDA’s EDA portfolio over the last three years, making six notable acquisitions – including AI-in-EDA pioneer Solido, advanced IC place and route tool vendor Avatar, and semiconductor lifecycle management company UltraSoC – while also reportedly increasing its investment in EDA R&D.

After Wally Rhines’ departure from the company, Siemens also wisely promoted Mentor’s key executives to grow its EDA business. After a storied career introducing and turning the Calibre physical verification suite into the top brand and revenue earner for Mentor, Joseph Sawicki is now in charge of the entire IC business at Siemens EDA. Meanwhile, AJ Incorvaia, a long-time and well respectied veteran of the PCB systems space, was tapped to grow the IC advanced packaging and PCB systems divisions of the Siemens EDA business. Both report to Tony Hemmelgarn, CEO of Siemens Digital Industries Software.

All three executives have been emphatic about Siemens’ commitment to the electronics design community while also pointing to the unique advantages of a portfolio that brings EDA, mechanical design and software worlds closer together in potentially interesting and ground breaking ways.

In particular on the IC EDA front, Joe Sawicki has been outlining Siemens EDA IC strategy and how it is addressing three classes of scaling challenges: Process Technology scaling, Design scaling and Systems scaling to help customers “engineer a smarter future faster”:

Enable process technology scaling – Despite the ever growing challenges of device physics presented with each new process technology node, Siemens EDA continues to work closely with customers and foundry partners to deliver signoff, DFM, lithography and test for each emerging process node. Siemens EDA, said Sawicki, is also committed to delivering 2.5D and 3D advanced packaging for those customers wanting to achieve “More than Moore” densities and is also pioneering synthesis and layout tools for companies pioneering next gen IO with silicon photonics.

Enable design scaling – As companies take a more holistic systems of systems view of their chip designs and especially as more integrate AI/ML into their SoCs, chip architects can develop algorithms in C of their AI/ML blocks and leverage high-level synthesis to determine the optimal HW/SW architecture for their smart SoCs and achieve power, performance and area goals. Alternatively, they can use 2.5D and 3D advanced packaging to achieve their system goals. Whichever route they go, they can leverage power analysis throughout the entire flow from C level design down to implementation, which will become increasingly noteworthy with last year’s acquisition of Avatar and its Aprisa place and route tool.

Enable systems scaling – Siemens EDA has already begun to pioneer new ground in verification, validation and more so what is commonly known as the digital twin. In fact, a year and a half ago, Siemens announced its PAVE 360, which ties Siemens EDA’s Veloce emulation system with a slew of PLM technologies to essentially verify automotive IC designs and validate related software in virtual driving scenarios before committing the silicon and the rest of the system to manufacturing. Siemens EDA’s Tessent group also pioneered a silicon lifecycle management technology called MissionMode and last year acquired UltraSoC, which enable companies to insert specialized IP blocks into their ICs that monitor in real time on-chip faults, security, power and performance of their ICs over the lifetime of the devices to perform tasks ranging from operating warnings to preventative maintenance or to improve derivative designs and even manufacturing processes.

If you are interested in learning more, check out the new Siemens EDA website. The new site is organized by electrical engineering functional discipline plus EDA consulting services:

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March 22, 2021July 18, 2025

Why In-Memory Computing Will Disrupt Your AI SoC Development

Why In-Memory Computing Will Disrupt Your AI SoC Development
by Ron Lowman on 03-22-2021 at 6:00 am
Categories: IP, Synopsys

dwtb q121 in memory comp fig1.jpg.imgw .850.x 1

Artificial intelligence (AI) algorithms thirsting for higher performance per watt have driven the development of specific hardware design techniques, including in-memory computing, for system-on-chip (SoC) designs. In-memory computing has predominantly been publicly seen in semiconductor startups looking to disrupt the industry, but many industry leaders are also applying in-memory computing techniques under the hood.

Innovative designs using in-memory computing are intending to disrupt the landscape of AI SoCs. First let’s take a look at the status-quo that startups using in-memory computing intend to disrupt. AI hardware has taken a huge leap forward since 2015 when companies and VCs started investing heavily into new SoCs specifically for AI. Investment has only accelerated over the past 5 years, leading to many improvements in AI hardware design for industry leaders. Intel’s x86 processors have added new instructions and even a separate NPU engine. Nvidia has added specific Tensor Cores and forsaken GDDR to implement HBM technologies to increase memory bandwidth. Google has developed specific ASIC TPUs, or Tensor Processing Units, dedicated to AI algorithms (Figure 1). But even though these architectures continue to improve, investors are looking to startups to develop the next disruption in AI technology.

Figure 1: Intel, Nvidia and Google are introducing new hardware architectures to improve performance per watt for AI applications

Why are Disruptions for AI Compute so Interesting?

The three key reasons for heavy investment into AI hardware are: 1) the amount of data generated is growing exponentially and AI is the critical technology to address the complexity; 2) the costs of running AI algorithms in power and time are still too high with existing architectures, specifically at the edge; 3) the parallelization of AI compute engines is reaching die size limits, driving these systems to scale to multiple chips which is only practical in cloud or edge-cloud data centers. Together, these new challenges are driving designers to explore new, innovative hardware architectures. In-memory compute is looked upon as one of the most promising hardware innovations because it may provide multiple orders of magnitude in improvements.

Paths for AI Compute Disruption

Startups and leading semiconductor providers are looking at potential paths for AI compute acceleration.

New types of AI models: New neural networks are being introduced quite often. For example, Google’s huge research team dedicated to releasing models has produced EfficientNet. Advanced Brain Research has released the LMU, and Lightelligence has partnered with MIT to run Efficient Unitary Neural Network (EUNNs).
Integrated photonics is being explored by several startups as another method for disruption.
Compression, pruning and other techniques are being developed to enable specific AI functions to operate on small, efficient processors such as a DesignWare® ARC® EM Processor IP running under 100MHz.
Scaling compute systems by packaging multiple die, multiple boards, or multiple systems is already in full production from the industry leaders. This solution is used to solve the most complex, costly challenges with AI.
These methods to increase performance are all being pursued or already realized. In-memory computing designs can build on these methods to drive efficiencies with multiple times improvements in addition to the other developing technologies.

What is In-Memory Computing?

In-memory computing is the design of memories next to or within the processing elements of hardware. In-memory computing leverages register files, memories within processors, or turns arrays of SRAMs or new memory technologies into register files or compute engines themselves. For semiconductors, the essence of in-memory computing will likely drive significant improvements to AI costs, reducing compute time and power usage.

Software and Hardware for In-Memory Compute

In-memory computing includes both hardware and software elements, which can cause some confusion. From a software perspective, in-memory computing refers to processing analytics in local storage. Basically, the software takes full advantage of the memories closer to the compute. “Memories” is a bit vague from a hardware perspective and can refer to DRAMs, SRAMs, NAND Flash and other types of memories within the local system rather than sourcing data over a networked software infrastructure. Optimizing software to take advantage of more localized memories has vast opportunity for industry improvement and teams of engineers will need to continue focus on these innovations at a system level. However, for hardware optimizations, in-memory compute offers bit level innovations that more closely mimic the human brain which is 1000s of times more efficient than today’s compute.

In-Memory Compute, Near-Memory Compute, and Analog Compute

In-memory computing hasn’t just arrived as a magic solution to AI algorithms—it has differing implementations and is evolving from a progression of innovations. The implementation of register files and caches has been around for decades and near-memory computing has been the natural progression of improvement and has seen implementations in new SoCs over the past several years. AI algorithms require millions, if not billions, of coefficients and multiply-accumulates (MACs). To efficiently perform all these MACs, customized local SRAMs for an array of MACs are now designed into SoCs for the sole purpose of performing AI model math, i.e., matrix/tensor math. Integrating dedicated specialized local SRAMs for an array of MACs to perform AI model math is the concept of near-memory compute. In near-memory compute, local SRAMs are optimized for the purpose of storing weights and activations needed for their designated MAC units.

The next natural progression to develop in-memory compute is analog computing. Analog computing enables additional parallelism and more closely mimics the efficiencies of a human brain. For analog systems, MACs and memories are parallelized, improving the system efficiency even further than near-memory compute alone. Traditional SRAMs can be the basis for in-memory analog computing implementations and Synopsys has delivered customizations for this very purpose.

Memory Technologies Address In-Memory Compute Challenges

New memory technologies are such as MRAM, ReRAM and others are promising as they provide higher density and non-volatility when compared to traditional SRAMs. Improvements over SRAMs can increase the utilization of the compute and memory on-chip. Utilization is one of the most critical design challenges for AI SoC designers (Figure 2). SoC designers need memory subsystems designed specifically for AI data movement and compute regardless of the technology used.

Figure 2: AI SoCs have extremely intensive computation and data movement, which can impact latency, area, and performance

The key challenges for AI SoC design with memory systems relate back to the number of MACs and coefficients that need to be stored. For ResNet-50, over 23M weights are needed and that computes into 3.5 billion MACs and 105B memory accesses. Not all are running at the same time, so the size of the largest activation can be the critical bottleneck to the memory subsystems. Control engineers know that efficiencies are made by designing bottlenecks to be at the most expensive functions of execution. Thus, designs need to ensure that their in-memory compute architectures can handle the largest layer of activation coefficients effectively.

Meeting these requirements demands huge amounts of on-chip memory and intensive computation of the multiple layers. Unique techniques in memory design are being developed to remove latencies, remove the size of coefficients and remove the amount of data that must be moved around the SoC.

DesignWare IP Solutions for In-Memory Compute

Synopsys provides a wide array of IP options for customers to implement in-memory computing. Optimized memory compilers specific for density or leakage are used to develop the local SRAMs for near-memory implementations where sometimes 1000s of MACs are instantiated. MACs can leverage a portfolio of Synopsys Foundation Core primitive math functions that includes flexible functions such as Dot Product, a common AI function.

In addition, Synopsys DesignWare Multi-Port Memory IP enabling up to 8 inputs or 8 outputs improves parallelism within the compute architectures. Multi-port memories are much more common within designs since AI has become so prevalent.

Synopsys developed a patented circuit that demonstrates innovations supportive of in-memory compute. A Word All Zero function, shown in Figure 3, essentially eliminates zeros from being processed. Why move zeros to multiply? The Word All Zero function significantly reduces the compute required and can reduce power by up to 60% for data movement within the chip.

Figure 3: In addition to the Word All Zero function, Synopsys DesignWare Embedded Memory IP offers multiple features to address power, area, and latency challenges

Conclusion

How fast in-memory compute is adopted in the industry remains to be seen; however, the promise of the technology and conceptual implementation with new memories, innovative circuits and creative designers will surely be an exciting engineering accomplishment. The journey to the solution is sometimes as interesting as the final result.

For more information:

White paper: Neuromorphic Computing Drives the Landscape of Emerging Memories for Artificial Intelligence SoCs

March 21, 2021March 21, 2021

Upcoming Webinar on Resistive RAM (ReRAM) Technology

Upcoming Webinar on Resistive RAM (ReRAM) Technology
by Kalar Rajendiran on 03-21-2021 at 10:00 am
Categories: eMemory, Events, IP

On-chip memory (embedded memory) makes computing applications run faster. In the early days of the semiconductor industry, the desire to utilize large amount of on-chip memory was limited by cost, manufacturing difficulties and technology mismatches between logic and memory circuit implementations. Since then, advancements in semiconductor manufacturing have been bringing on-chip memory costs down. In parallel, leading edge process nodes have been throwing new challenges to embedded memories. Of course, high-speed I/O interfaces have made it easier to use off-chip memories without sacrificing computing application speed. At the same time, new applications such as AI, machine learning, mobile and other low-power applications have been fueling demands for large amounts of embedded memories. Many of the existing embedded memory technologies face challenges as the process node goes below 28nm. The challenges are due to additional material layers and masks, supply voltages, speed, read & write granularity and area.

It is in this context that eMemory Technology Inc. will be hosting a webinar that will be very informative and useful for chip designers and semiconductor companies. The webinar is titled “eMemory’s Embedded ReRAM Solution on Nanometer Technologies” and is scheduled for March 24^th, 2021. I got an opportunity to preview the webinar content. Following is just a few of the salient points that I’d like to share in this blog. Please register for the webinar to learn the full and intricate details.

The webinar will focus on a very promising technology called Resistive RAM (ReRAM) that will be available in production very soon. ReRAM is specifically designed to work in 40nm and finer geometry process nodes. In contrast, many of the other memory types such as Split-Gate Flash, Logic process MTP and Logic Process EEPROM face challenges below 28nm.

Due to ReRAM’s simplicity for process manufacturing, it can be integrated into Back End of Line (BEOL) with only a few extra masks and steps. ReRAM technology enables high-speed, low-power write operations and increased storage density, all critical for AI computing-in-memory application as an example.

Attendees will gain insights into ReRAM cell structure, switching methodology, and the suitability of ReRAM to various prospective applications. eMemory Technology will also share measurement results of their 40nm ULP and 22nm ULL ReRAM reliability data at 85C and 125C operation and 10-year retention data after 10K cycles.

Anyone who is looking into designing chip solutions in advanced process nodes for applications that could benefit from embedded memories would learn a lot from attending this webinar. Register here for the “eMemory’s Embedded ReRAM Solution on Nanometer Technologies” webinar.

March 21, 2021May 7, 2021

RIP Jim Hogan – An Industry Icon

RIP Jim Hogan – An Industry Icon
by Bernard Murphy on 03-21-2021 at 8:00 am
Categories: AI, EDA, General, IP
5 Comments

An unavoidable consequence of getting older is that more frequently our friends and colleagues unexpectedly leave us for their final venture. Jim Hogan, widely known and loved in the semiconductor industry, has passed on. He will leave a substantial hole in the hearts of many. Always ready with seasoned advice, a sympathetic ear and a boundless stock of entertaining stories. I for one will never forget his patient and encouraging support. For now, I must make do by remembering the man who helped and inspired me in so many ways. My thanks also to Peter Calverley and Scott Becker of Tela Innovations for filling in some of the blanks. RIP Jim Hogan, a dear friend to many of us.

The early days

I first met Jim in the late 80’s at National Semiconductor. He was a big wheel in computer integrated manufacturing, and I was a lowly CAD manger in the ASIC group. He left to join Cadence and I independently left for Cadence not long after. Our orbits didn’t overlap too much during that period, but I remember a friendly easy-going recognition at those times our paths did cross.

Jim stayed at Cadence for a while, running a division, later Japan Operations before moving on to Artisan Components as the head of Business Development. Which culminated in Artisan’s acquisition by ARM. Jim then switched to what would become his true love – investing in and guiding early-stage ventures. If you were a Jim Hogan watcher at all, you’ll know he was involved with many successful exits. However, he was a modest guy. He told me that there were many more not-so-successful investments. He would often laugh about Theranos as one painful example.

Investing and guiding

Jim invested first through Cadence’s Telos Venture Partners. Later and together with Scott Becker, a close friend he first met at Artisan, he formed his own venture fund Vista Ventures. At the same time Jim helped Scott form Tela Innovations and served on the board for over fifteen years. Vista Ventures was the vehicle through which he invested in many of the companies we know he helped. Most recently Jim complemented his investment activity by joining the board of Silicon Catalyst.

Nothing could get Jim more excited than new technologies and new ideas. In my closing days at Atrenta, I got into blogging, particularly on harebrained ideas – which Jim enthusiastically encouraged. I’m not sure which of us was crazier. One blog was on how we could exploit biological security parallels (antibodies and so on) in system security. He wanted to turn it into a Ted talk. The guy was infectiously excited by any new tech idea.

He guided me in my early freelancing, helping setup assignments and introducing me to key executives looking for content marketing help or strategic marketing guidance. I was lucky to work together with Jim on some of these projects, for example the work we have done together with Paul Cunningham at Cadence in the “Innovation in Verification” series. Paul and I are the techie enthusiasts. Jim always grounded us with his investment insight. He also provided me with the content for chapter 4 of my recent book (The Tell-Tale Entrepreneur). That chapter offers a fascinating view into investment through the eyes of an investor.

The person

I wasn’t lucky enough to meet Jim’s family, but I know we shared common interests outside technology. We were always debating how to manage fire clearance, tractors and attachments, drilling new wells and building versus buying a new home. He talked often and affectionately about Lisa and even more often about Jake and his adventures, most recently his fascination with chain saws (I can relate).

My abiding impression of Jim is that for all his accomplishment and renown in the industry, he topped it by being one of the most genuinely nice human beings you could ever hope to meet and count as a friend. We all want to succeed in fame and fortune. Jim had those but more important he left a lasting impression as the kind of person we all hope to be when our time finally comes. Rest in peace Jim. We won’t find your like again.

If you would like to express your appreciation of Jim, please submit your entry to nominate him the the Phil Kaufman Hall of Fame.

Podcast EP3: Tomorrow’s Semiconductors with Jim Hogan

March 21, 2021March 26, 2023

Micron- Optane runs out of Octane- Bye Bye Lehi- US chip effort takes a hit

Micron- Optane runs out of Octane- Bye Bye Lehi- US chip effort takes a hit
by Robert Maire on 03-21-2021 at 6:00 am
Categories: Semiconductor Advisors, Semiconductor Services
2 Comments

– Micron shuts down once promising XPoint
– Lehi Utah fab to be sold off- Had been a $400M drain
– Unique memory couldn’t follow flash down cost/yield curve
– Savings helps Micron but its now just another memory maker

XPoint “Coulda been a contender”

XPoint should have amounted to more than a footnote in semiconductor history. It promised speed between NAND and DRAM, closer to DRAM at costs approaching NAND with the benefit of being non-volatile.
But it wasn’t meant to be.

Intel pulled out of the partnership a while ago, not wanting to throw more money down a hole. It now looks like Micron was cleaning things up to get ready to shut it down.

We are certainly vey disappointed that in the end it didn’t work as it had clear promise and a shot at being the next memory technology since NAND was invented back in 1980.

Couldn’t get on the Moore’s Law cost/yield curve

The problems appears to be that the technology was never able to get on , let alone stay on, the Moore’s Law cost curve that keeps driving memory prices ever lower on a per bit basis.

You need two basic ingredients to make it work; yield and shrinks. The yield (percentage of working chips on a wafer) has to get to a point where there are enough working chips per wafer divided by the per wafer cost to make the needed market price to be competitive. Second the technology also has to work to the point where you can reliably shrink the dimensions of the chip design on a regular cadence to continually increase the number of bits per square inch to keep up with the market.

Was it the failure of XPOINT or the Success of NAND that caused XPoint’s demise?

Maybe it was both…..One could argue that moving NAND to a 3D architecture just accelerated it too far ahead from XPoint’s ability to ever keep up. Others could argue that XPoint never met its intended goals of price, performance and yield.

At this point a post mortem is almost pointless as its dead anyway.
However it does amplify exactly how incredibly difficult the semiconductor industry is, even with very deep pockets and both Intel and Micron supporting it, they still couldn’t get it to work well enough to make the cut.

Good and bad for Micron

The good news is that Micron will get rid of a $400M/year cash drain, the bad news is that Micron will be just another memory competitor up against the likes of Samsung and a more determined SK.

XPoint, had it worked , could have been a great differentiator that no other memory company had and would have put Micron in a unique position. Now they are relegated to slugging it out with Samsung and trying to find small niches where they have a unique advantage.

Don’t get me wrong….Micron has proven very good at weaving and dodging among the big boys and just outmaneuvered them by keeping a step or two ahead in certain areas. But XPoint could have been a different type of lifeline.

Not good for MRAM, RRAM & PRAM

There are a number of other memory technologies that are also being developed as competitors to todays DRAM NAND duopoly. All offer attractive alternative characteristics to DRAM or NAND. In our view, XPoint was likely the best funded memory alternative, had the best supporters, Intel & Micron and had both a dedicated fab as well as commercial installations in end customer products and it still failed.

Its going to be very difficult to do what XPoint couldn’t, even with all the attributes it had going for it.

Bye Bye Lehi- Its sale won’t help current shortage

Micron is selling off the associated fab in Lehi. The positive here is that they will likely get a reasonable price as compared to the scrap value that old fabs usually sell for given current demand.

It will cost a lot of time and money to re-configure the fab for logic as it is likely not big enough for anything other than specialty memory.

We would guess it could take a couple of years to re-configure so it isn’t going to be any help at all for todays current chip shortage.

We also wouldn’t be too sure that it will stay a fab at all. It may be more financially attractive for Micron to sell off the tools to be shipped off to Asia to be installed into fabs there as we have seen happen with other US fabs.

Maybe even Micron itself, which is the King of getting fabs on the cheap, might part out the bits and pieces of the fab to its own fabs where they could add incremental capacity.

Its not clear whether its worth more as parts or as a whole.

Doesn’t bode well for US chip efforts

This clearly flies directly in the face of current discussions about helping the US chip industry. Here we are with a US company, located in the heartland of Boise Idaho shutting down a US fab while continuing their overseas operations which have been expanding.

The US government, could put its money and effort where its mouth is and keep the fab in the US and in US hands. Perhaps it could be the first poster child and spearhead of the effort to boost the US semiconductor industry and save it from itself, or not. Wake up! this is an opportunity!

The stocks

Investors will clearly view this as a positive for Micron as it cuts the cash drain and may supply some short term cash before the end of the year. Longer term it makes Micron less competitive but investors don’t generally care about the longer term.

Its likely a neutral to slightly positive for equipment companies as Micron will have more money to spend but won’t be spending it on Lehi (not that there were any plans to spend anyway). Shutting down XPoint was somewhat expected so its not a huge surprise just more of a relief.

Micron’s stock is not that expensive as many investors do not believe forward earnings given the volatility of the memory industry. This may help them make numbers.

R.I.P. – XPoint/Optane & Lehi

Also Read:

Chip Channel Check- Semi Shortage Spreading- Beyond autos-Will impact earnings

Semiconductor Shortage – No Quick Fix – Years of neglect & financial hills to climb

“For Want of a Chip, the Auto Industry was Lost”

Podcast EP12: A Close Look at Intel with Stacy Rasgon

Podcast EP12: A Close Look at Intel with Stacy Rasgon
by Daniel Nenni on 03-19-2021 at 10:00 am
10 Comments

Dan takes an in-depth look at Intel with Stacy Rasgon, Managing Director and Senior Analyst, U.S. Semiconductors at Bernstein Research. Stacy is an unusual semiconductor analyst as he holds a Ph.D. in chemical engineering from MIT. His substantial technical knowledge allows for a deep dive on Intel that you will find refreshing and quite interesting.

We cover several CEO regimes at Intel with a frank assessment of the latest talent infusion. What will Intel do next? Stacy offers some interesting perspectives during our discussion.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

Intel on SemiWiki

March 19, 2021May 4, 2022

Electronics Back Strongly in 2021

Electronics Back Strongly in 2021
by Bill Jewell on 03-19-2021 at 8:00 am
Categories: China, Semiconductor Intelligence, Semiconductor Services

Electronics production has recovered strongly from slowdowns due to the COVID-19 pandemic. Most major Asian electronic producers reported double-digit increases in early 2021. The chart below shows three-month-average change versus a year ago for electronics production. The data is from each country’s official statistics and is in local currency.

China, by far the largest producer of electronics, was growing at about a 10% average rate in 2019. As many factories were shut in early 2020 due to the COVID-19 pandemic, electronics production change versus a year ago turned negative. Production growth was back to the 10% range in May 2020. Production came back robustly in early 2021 compared to the weakness of a year ago. In February 2021, China’s electronics production was up 36%.

Vietnam was one of the most successful countries in fighting the COVID-19 outbreak. According to the World Health Organization (WHO), Vietnam had only 2,567 cases and 35 deaths out of a population of over 94 million. The country did shut down for three weeks in April 2020, which resulted in a slowdown in electronics production. Production bounced back to double-digit growth in October 2020. Vietnam’s electronics production growth in February 2021 was 23% versus a year ago.

South Korea was relatively successful in fighting COVID-19, with WHO reporting 97,294 cases and 1,688 deaths out of a population of over 50 million. South Korea never shut down businesses, which enabled growth in electronics production throughout 2020. Growth was over 20% in January through March of 2020, with South Korean manufacturing benefiting from slowdowns in other countries. South Korea’s electronic production growth was 12% in January 2021.

Taiwan experienced electronics production growth averaging over 20% in the months of 2019, benefiting from production shifts from China during the U.S.-China trade disputes. Growth slowed to single digits in 2020, but never went negative. Taiwan was also very effective in fighting COVID-19, with only 990 cases and 10 deaths out of a population of over 24 million according to Johns Hopkins University of Medicine.

China’s production growth is reflected in the unit production of two key electronics products – PCs and mobile phones. China produces over 80% of the world’s supply of each of these products. Unit production change versus a year ago of both PCs and mobile phones turned negative in early 2020. PCs returned to growth in April 2020, but mobile phones remained negative throughout 2020. In February 2021, PCs were up 73% and mobile phones were up 19%. These growth rates are impressive but are being measured against a very weak early 2020.

The United States and the United Kingdom (UK) were two of the countries hardest hit by COVID-19, with death rates of over 160 per 100,000 people according to WHO. Several major European Union (EU) countries were also severely impacted, especially Italy, Spain, and France. Lockdowns in the U.S. varied by state, but in general did not have much effect on manufacturing. U.S. electronics production slowed from over 5% year-to-year growth in the first five months of 2019 to less than 1% in December 2019, prior to any COVID-19 related slowdowns. U.S. growth remained below 1% until July 2020 and picked up to over 8% in November 2020. January 2021 growth was 8.7%.

EU electronics production change versus a year ago in 2020 was similar to 2019 – single digit declines in most months. COVID-19 related lockdowns did not seem to significantly affect electronics production. Growth picked up to 11% in December 2020 and 23% in January 2021. The UK officially left the EU on January 31, 2020, a process known as Brexit. A transition period lasted until December 31, 2020 with a final trade agreement at the last minute. The UK electronics production change was like the EU, except for a double-digit decline beginning in April 2020. UK shutdowns impacted manufacturing for several months in mid-2020. UK growth in January 2021 was 0.7%. The UK has not seen the powerful recent growth the EU has experienced. The Financial Times reported over one-third of UK manufacturers have lost revenue since the UK left the EU, primarily due to delays in importing from and exporting to the EU. The long-term effect of Brexit on UK electronics production remains to be seen. Brexit critics foresee companies shifting production from the UK to EU countries to reach EU markets more easily. Brexit supporters predict with UK free of the EU it will be able to increase production for export to the world outside of the EU.

The substantial early 2021 growth in electronics production is reflected in semiconductor shipments, according to World Semiconductor Trade Statistics (WSTS) data. The semiconductor market in 2020 was on a recovery path from a 12% decline in 2019, with three-month-average change rebounding from a 16% decline in June 2019 to a 6.9% increase in March 2020. Growth plateaued in the 5% to 7% range until reaching 9.2% in November 2020. Revenues versus a year ago were up 13.2% in January 2021, the largest increase since October 2018. January 2021 monthly semiconductor shipments were $3,997 million, up 0.1% from $3,992 million in December 2020. The normal seasonal trend is a significant decline in January from December, ranging from -5% to -15% over the last ten years. January 2021 marks the first semiconductor revenue increase from December to January in the history of WSTS data going back to 1984.

Although the global economy has yet to fully recover from the COVID-19 pandemic, the electronics and semiconductor industries seem past the recovery phase and back to healthy growth.

Semiconductor Intelligence is a consulting firm providing market analysis, market insights and company analysis for anyone involved in the semiconductor industry – manufacturers, designers, foundries, suppliers, users or investors. Please contact me if you would like further information.

Also Read:

Semiconductors up 6.5% in 2020, >10% in 2021?

Semiconductor Boom in 2021

China Mobile and Computer Update 2020