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Can Our Privacy be Protected in Cars?

Can Our Privacy be Protected in Cars?
by Roger C. Lanctot on 03-28-2021 at 8:00 am
Categories: Automotive

Can Our Privacy be Protected in Cars

“Those who would give up essential liberty to purchase a little temporary safety deserve neither liberty nor safety.” — Benjamin Franklin

I hope Ben Franklin was not opposed to enhancing driving safety, but he may have looked with a jaundiced eye at the proliferation of in-cabin driver monitoring technology. It’s clear that Consumer Reports does not approve.

Mere months after applauding Comma.ai’s aftermarket driver assistance device for its integration of driver monitoring technology, Consumer Reports has taken issue with Tesla Motors’ acknowledged use of in-cabin video to advance its development of self-driving technology. CR sees the activity as an undisclosed invasion of privacy.

I am no expert on privacy. Listening in on Morrison & Foerster’s Webinar on the new Virginia Consumer Privacy Act and how it compares and contrasts with California’s Consumer Privacy Act and the European Union’s Global Data Protection Regulation it became clear that if these three jurisdictions were unable to agree on a single path to privacy protection it is clearly not an easily resolved issue.

Virginia’s Consumer Data Protection Act: What Changes Does It Require, and How Does It Compare to CPRA 

The complexity of preserving privacy – which will now be left to attorneys and judges to sort out in the context of these new laws – is unfortunate given the proliferation of cameras in public spaces, on mobile devices, and in and around automobiles. This proliferation raises questions of access and control and, of course, privacy.

Making the matter even more difficult to resolve is the reality that privacy regulations are not confined by boarders. A company or an individual based or living in the U.S. that does business in the E.U. – even without traveling there – is subject to GDPR, just as anyone transacting in or traveling through California or Virginia must be mindful of these new regulations. And all of these regulations have already seen revisions and will be forced to respond to legal interpretations.

The fundamentals are the same everywhere. Clear and concise disclosures. Require affirmative consumer opt in. Data access and transparency. Disclosure of intended uses. Right to erasure. It’s the details that get thorny.

Jon Fasman’s “We See It All” chronicles the increasing role of technology in law enforcement and the many ways privacy is steadily being compromised in the pursuit of enhanced security and public safety. Early on in the book he notes the use of facial recognition technology by airlines during boarding and he advises readers to avoid this technology at all cost – even if doing so makes boarding less convenient.

Fasman’s message, which is conveyed throughout the book, is that if an intrusive potentially privacy violating technology can be abused, it will be. No pollyanna, he goes on to note the range of negative collateral impacts from the use of “shotspotting,” body cameras, and widely dispersed closed circuit video cameras as well as the use of artificial intelligence for deploying police forces and in sentencing.

Fasman argues for improvements in the regulation of these technologies including such measures as limiting access to the data gathered by these systems and limiting the period of time allowed for their storage or retention for future use. But the moral of the story appears to be that the battle to preserve privacy must be fought continuously even though it already appears to be lost.

China is, of course, the worst case scenario, as detailed in Kai Strittmatter’s “We Have been Harmonized.” The author describes a scenario where the local police’s city ubiquitous CCTV-based surveillance system, equipped with facial recognition technology, is able to locate allowing officers to detain him in a matter of minutes in a test.

Something similar is coming to the cabins of cars. In-cabin sensors are increasingly being used to detect driver drowsiness. But the transition to camera-based systems is being pioneered for solutions such as General Motors’ Super Cruise driver assistance system – which uses camera-based monitoring to ensure driver vigilance when the hands-free driving function is activated.

The European New Car Assessment Program (Euro-NCAP) – Europe’s protocol for granting five-star safety ratings for new cars – will require driver monitoring systems beginning sometime after 2022. Like local privacy policies that have global influence, Euro-NCAP’s requirement will have a global impact.

What remains unclear is how consumers will react. In the past few years, consumers have “discovered” far more passive monitoring systems in their cars – such as Daimler’s in-dash coffee cup icon when one has been driving too long uninterrupted – but inward facing cameras is something new.

Seeing Machines, which provides in-cabin cameras for General Motors’ Super Cruise and for fleet operators, has been careful to note that its devices do not store video and that they neither transmit video nor are externally hackable. But cameras do represent both a privacy and a security vulnerability.

In its own research, Strategy Analytics has found a wide range of conflicting insights regarding consumer perceptions of privacy. Consumers have expressed concerns about protecting their privacy, but readily surrender that privacy when pressed by a manufacturer or service provider – somewhat more so in the U.S. than in the E.U.

Ironically, a global survey conducted by Strategy Analytics revealed that policies, such as the E.U.’s GDPR, have caused consumers to lower their privacy guard even further. Presumably the institution of the regulation instills a sense of security and safety rather than raising a sense of necessary vigilance.

Not all consumers are so sanguine. An Amazon driver recently created headlines when he quit as a result of the company’s deployment of Netradyne four-camera vehicle monitoring systems. Thomson Reuters quoted the man: “It was both a privacy violation, and a breach of trust, and I was not going to stand for it.”

It may well be that the price of access to semi-autonomous vehicle functions, like GM’s Super Cruise, will be a loss of consumer privacy manifest in cabin-mounted cameras. Car makers will surely promise not to store or transmit sensitive data, but the best consumers may be able to hope for is to have fun sending selfies while driving. That sounds like a reasonable tradeoff, right?

There is a bit of good news from Strategy Analytics research. In a world increasingly bereft of privacy protections in spite of new regulations, car makers stand out in the minds of consumers. According to Strategy Analytics research: “Though consumers have mixed feelings about trusting telecom and tech-centric hardware and software firms with their data, this concern clearly does not extend to automakers.” Time will tell whether auto makers can preserve this perception as they flirt with invasive monitoring technologies.

Consumers and the Data Trust Gaps Between Automakers and Big Tech

Data Privacy: Lack of Knowledge, Resignation, and Unfounded Confidence 

Survey Highlights Privacy Paradox 

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SALELE Double Patterning for 7nm and 5nm Nodes

SALELE Double Patterning for 7nm and 5nm Nodes
by Fred Chen on 03-28-2021 at 6:00 am
Categories: Lithography
2 Comments

SALELE Double Patterning for 7nm and 5nm Nodes 4

In this article, we will explore the use of self-aligned litho-etch-litho-etch (SALELE) double patterning for BEOL metal layers in the 7nm node (40 nm minimum metal pitch [1]) with DUV, and 5nm node (28 nm minimum metal pitch [2]) with EUV. First, we mention the evidence that this technique is being used; Xilinx [3] disclosed the use of the technique in 7nm BEOL. Secondly, a minimum metal pitch as small as 28 nm leads to restricted illumination (low pupil fill) reducing the transmitted source power by 50% [4]. Throughput would be faster with the use of two EUV tools in series for double patterning (with 56 nm minimum metal pitch) since the number of wafers per day is tied to one litho tool handing off to the next. More seriously, stochastic defects [5] are a serious issue for single exposure at pitches ~30 nm [6]; however, pitch splitting by printing the same feature twice at twice the pitch exacerbates this [5]. Fortunately, SALELE [7] offers a way out, as will be explained below.

To achieve 14 nm features on a 28 nm pitch, for example, SALELE may start with 28 nm features, e.g., trenches, on a 56 nm pitch (Figure 1). This is advantageous over using 14 nm features on a 56 nm pitch or 28 nm pitch, due to the high incidence of EUV stochastic defects for the smaller features.

Figure 1. First patterned trenches (28 nm width on 56 nm pitch).

The trenches can be expanded, e.g., photoresist trimming [8], to 42 nm width. Then a 14 nm sidewall spacer is deposited and etched back to leave a 14 nm sidewall liner surrounding a 14 nm core feature filled within (Figure 2).

Figure 2. Trenches are expanded to 42 nm width, then sidewall liner of 14 nm formed on inside wall.

Outside and between two adjacent liners, an additional 14 nm trench may be patterned directly (actual width can be close to 28 nm); the liners help keep the latter trench aligned with the previous ones (hence, the self-aligned aspect) (Figure 3).

Figure 3. Additional trench patterned with alignment margin provided by the sidewall liners. The dotted line indicates the margin for printing or placing the feature.

The trenches patterned at the two different stages can be filled with two different materials which etch differently, such as oxide and nitride. This allows those trenches to be cut more safely (Figure 4), since a cutting line can extend over the neighboring trench.

Figure 4. Trenches from the two stages are cut separately.

In total, four masks are used [7], two for the trenches, and two for the separate trench cuts. Self-aligned quadruple patterning (SAQP) using only DUV immersion tools can bring this down to three masks, but requires further process control maturity in addressing pitch walking [9].

While the cuts can be performed in EUV, they would suffer the previously mentioned stochastic defects issue, so DUV is more likely to be used. This would mean two EUV tools and two DUV tools being set up for the SALELE flow. This would be preferable to binding four EUV tools to this flow. For the earlier 7nm process [1], four immersion tools would be allocated. A more conventional self-aligned double patterning (SADP) can also reduce this to three masks, three tools. 20 nm features still pose a stochastic defect risk for EUV [5,6]. SALELE offers an easy transition from the LELE double patterning flow of the older 14/16/22nm nodes, but requires a substantial increase in lithography tooling.

References

[1] S-Y. Wu et al., “A 7nm CMOS platform technology featuring 4th generation FinFET transistors with a 0.027um2 high density 6-T SRAM cell for mobile SoC applications,” IEDM 2016.

[2] J. C. Liu et al., “A Reliability Enhanced 5nm CMOS Technology Featuring 5th Generation FinFET with Fully-Developed EUV and High Mobility Channel for Mobile SoC and High Performance Computing Application,” IEDM 2020.

[3] Q. Lin et al., “Improvement of SADP CD control in 7nm BEOL application,” Proc. SPIE 11327, 113270X (2020).

[4] D. Rio et al., “Extending 0.33 NA EUVL to 28 nm pitch using alternative mask and controlled aberrations,” Proc. SPIE 11609, 116090T (2021).

[5] P. de Bisschop and E. Hendrickx, “On the dependencies of the stochastic patterrning- failure cliffs in EUVL lithography,” Proc. SPIE 11323, 113230J (2020).

[6] J. Church et al., “Fundamental characterization of stochastic variation for improved single-expose extreme ultraviolet patterning at aggressive pitch,” J. Micro/Nanolith. MEMS MOEMS 19, 034001 (2020).

[7] Y. Drissi et al., “SALELE process from theory to fabrication,” Proc. SPIE 10962, 109620V (2019).

[8] L.Jang et al., “SADP for BEOL using chemical slimming with resist mandrel for beyond 22nm nodes,” Proc. SPIE 8325, 83250D (2012).

[9] H. Ren et al., “Advanced process control loop for SAQP pitch walk with combined lithography, deposition and etch actuators,” Proc. SPIE 11325, 1132523 (2020).

This article first appeared in LinkedIn Pulse: SALELE Double Patterning for 7nm and 5nm Nodes

Related Lithography Posts

Podcast EP13: The Three Pillars of Verification with Adnan Hamid

Podcast EP13: The Three Pillars of Verification with Adnan Hamid
by Daniel Nenni on 03-26-2021 at 10:00 am
2 Comments

Dan goes on a scenic tour of verification with Adnan Hamid, founder and CEO of Breker Verification Systems.  We discuss the rather unusual way Adnan got into semiconductors and SoC verification. Adnan then breaks down the verification task into its fundamental parts to reveal what the three pillars of verification are and why they are so important.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

Breker Verification Systems

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Foundry Fantasy- Deja Vu or IDM 2?

Foundry Fantasy- Deja Vu or IDM 2?
by Robert Maire on 03-26-2021 at 8:00 am
Categories: Foundries, GlobalFoundries, Intel Foundry, Samsung Foundry, Semiconductor Advisors, Semiconductor Services, TSMC
9 Comments

Foundry Profit 2020

– Intel announced 2 new fabs & New Foundry Services
– Not only do they want to catch TSMC they want to beat them
– It’s a very, very tall order for a company that hasn’t executed
– It will require more than a makeover to get to IDM 2.0

Intel not only wants to catch TSMC but beat them at their own game

Intel announced that it was going to spend $20B on two new fabs in Arizona and establish Intel Foundry Services as part of re-imagining Intel into “IDM 2.0”. The stated goal would be to provide foundry services to customers much as TSMC does so well today.

This will not be easy. A lot of companies have died on that hill or been wounded. Global Foundries famously gave up. Samsung still spends oodles of money trying to keep within some sort of distance to TSMC. UMC, SMIC and many others just don’t hold a candle to TSMC’s capabilities and track record.

This all obviously creates a very strange dynamic where Intel is highly dependent upon TSMC’s production for the next several years but then thinks it can not only wean itself off of TSMC’s warm embrace but produce enough for itself as well as other customers to be a real foundry player.

If Pat Gelsinger can pull this off he deserves a billion dollar bonus

This goes beyond doubling down on Intel’s manufacturing and well into a Hail Mary type of play. This may turn out to be an aspirational type of goal in which everyone would be overjoyed if they just caught back up to TSMC.

Like Yogi Berra said “It’s Deja Vu all over again”- Foundry Services 2.0

Lest anyone conveniently forget, Intel tried this Foundry thing before and failed, badly. It just didn’t work. They were not at all competitive.

It could be that we are just past the point of remembering that it was a mistake and have forgotten long enough to try again.

We would admit that Intel’s prior attempt at being a foundry services provider seemed almost half hearted at best. We sometimes thought that many long time Intel insiders previously snickered at being a foundry as they somehow thought it beneath them.

Trying to “ride the wave” of chip shortage fever?

It could also be that Intel is trying to take advantage of the huge media buzz about the current chips shortage by playing into that theme, and claiming to have the solution.

We would remind investors that the current chip shortage that has everyone freaked out will be long over, done and fixed and a distant memory before the first brick is even laid for the two new fabs Intel announced today. But it does make for good timing and PR.

Could Intel be looking for a chunk of “Chips for America” money?

Although Intel said on the call that government funding had nothing to do with whether or not they did the project we are certain that Intel will have its hand out and lobby big time to be the leader of Chips for America.

We would remind investors that the prior management of Intel was lobbying the prior White House administration hard to be put in charge of the “Chips for America” while at the exact same time negotiating to send more product (& jobs) to TSMC.

This is also obviously well timed as is the current shortage. Taken together the idea of Intel providing foundry services makes some sense on the surface at least.

Intel needs to start with a completely clean slate with funding

We think it may be best for Intel to start as if it never tried being a foundry before. Don’t keep any of the prior participants as it didn’t work before.
Randhir Thakur has been tasked with running Intel Foundry Services. We would hope that enough resources are aimed at the foundry undertaking to make it successful. It needs to stand alone and apart.

Intel’s needs different “DNA” in foundry- two different companies in one

The DNA of a Foundry provider is completely different than that of being an IDM. They both do make chips but the similarity stops there.

The customer and customer mindset is completely different. Even the technology is significantly different from the design of the chips, to the process flows in the fabs to package and test. The design tools are different, the manufacturing tools are different and so is packaging and test equipment.

While there is a lot of synergy between being a fab and an IDM it would be best to run this as two different companies under one corporate roof. It’s going to be very difficult to share: Who gets priority? Who’s needs come first? One of the reason’s Intel’s foundry previously failed was the the main Intel seemed to take priority over foundry and customers will not like the obvious conflict which has to be managed.

Maybe Intel should hire a bunch of TSMC people

Much as SMIC hired a bunch of TSMC people when it first started out, maybe Intel would be well served to hire some people from TSMC to get a jump start on how to properly become a real foundry. It would be poetic justice of a US company copying an Asian company that made its bones copying US companies in the chip business.

We have heard rumor that TSMC is offering employees double pay to move from Taiwan to Arizona to start up their new fab there. Perhaps Intel should offer to triple pay TSMC employees to move and jump ship. It would be worth their while. Intel desperately needs the help.

Pat Gelsinger is bringing back a lot of old hands from prior years at Intel as well as others in the industry (including a recent hire from AMAT) but Intel needs people experienced in running a foundry and dealing with foundry customers. Intel has to hire a lot of new and experienced people because they not only need people to catch up their internal capacity, which is not easy, and it needs more people to become a foundry company and the skillsets, like the technology are completely different. This is not going to be either cheap or easy.

I don’t get the IBM “Partnership”

IBM hasn’t been a significant, real player in semiconductors in a very, very long time. It may have a bunch of old patents but it has no significant current process technology that is of true value. It certainly doesn’t build current leading edge or anything close nor does it bring anything to the foundry party.
Its not like IBM helped GloFo a lot. They brought nothing to the table. GloFo still failed in the Moore’s law race. In our view IBM could be a net negative as Intel has to “think different” to be two companies in one, it needs to re-invent itself.

The IBM “partnership” is just more PR “fluff” just like the plug from Microsoft and quotes from tech leaders in the industry that accompanied the press release. Its nonsense.

Don’t go out and buy semi equipment stocks based on Intel’s announcements

Investors need to stop and think how long its going to be before Intel starts ordering equipment for the two $10B fabs announced. Its going to be years and years away.

The buildings have to be designed, then built before equipment can even be ordered. Maybe if we are lucky the first shovel goes in the ground at the end of 2021 and equipment starts to roll in in 2023…maybe beginning production at reasonable scale by 2025 if lucky. Zero impact on current shortage – Even though Intel uses the current shortage as excuse to restart foundry

The announcement has zero, none, nada impact on the current shortage for two significant reasons;

First, as we have just indicated it will be years before these fabs come on line let alone are impactful in terms of capacity. The shortages will be made up for by TSMC, Samsung, SMIC, GloFo and others in the near term. The shortages will be ancient history by the time Intel gets the fabs on line.

Second, as we have previously reported, the vast majority of the shortages are at middle of the road or trailing edge capacity made in 10-20 years old fabs on old 8 inch equipment. You don’t make 25 cent microcontrollers for anti-lock brakes in bleeding edge 7NM $10B fabs, the math doesn’t work. So the excuse of getting into the foundry business because of the current shortage just doesn’t fly, even though management pointed to it on the call.

Could Intel get Apple back?

As we have said before, if we were Tim Apple, a supply chain expert, and the entire being of our company was based on Taiwan and China we might be a little nervous. We also might push our BFF TSMC to build a gigafab in the US to secure capacity. The next best thing might be for someone else like Intel or Samsung to build a gigafab foundry in the US that I could use and go back to two foundry suppliers fighting for my business with diverse locations.

The real reason Intel needs to be a foundry is the demise of X86

Intel has rightly figured out that the X86 architecture is on a downward spiral. Everybody wants their own custom ARM, AI, ML, RISC, Tensor, or what ever silicon chip. No one wants to buy off the rack anymore they all want their own bespoke silicon design to differentiate the Amazons from the Facebooks from the Googles.

Pat has rightly figured out that its all about manufacturing. Just like it always was at Intel and something TSMC never stopped believing. Yes, design does still matter but everybody can design their own chip these days but almost no one, except TSMC, can build them all.

Either Intel will have to start printing money or profits will suffer near term

We have been saying that Intel is going to be in a tight financial squeeze as they were going to have reduced gross margins by increasing outsourcing to TSMC while at the same time re-building their manufacturing, essentially having a period of almost double costs (or at least very elevated costs).

The problem just got even worse as Intel is now stuck with “triple spending”. Spending (or gross margins loss) on TSMC, re-building their own fabs and now a third cost of building additional foundry capacity for outside customers.
We don’t see how Intel avoids a financial hit.

Its not even sure that Intel can spend enough to catch up let alone build foundry capacity even if it has the cash

We would point out that TSMC has the EUV ASML scanner market virtually tied up for itself. They have more EUV scanners than the rest of the world put together.

Intel has been a distant third after Samsung in EUV efforts. If Intel wants to get cranking on 7NM and 5NM and beyond it has a lot of EUV to buy. It can’t multi-pattern its way out of it. Add on top of that a lot of EUV buying to become a foundry player as the PDKs for foundry process rely a lot less on the tricks that Intel can pull on its own in house design and process to avoid EUV. TSMC and foundry flows are a lot more EUV friendly.

As we have previously pointed out the supply of EUV scanners can’t be turned on like a light switch, they are like a 15 year old single malt, it takes a very long time to ramp up capacity, especially lenses which are a critical component.
I don’t know if Intel has done the math or called their friends at ASML to see if enough tools are available. ASML will likely start building now to be ready to handle Intel’s needs a few years from now if Intel is serious.

Being a foundry is even harder now

Intel was asked on the call “what’s different this time” in terms of why foundry will work now when it didn’t years ago and their answer was that foundry is a lot different now.

We would certainly agree and suggest that being a leading edge foundry is even much more difficult now. Its far beyond just spending money and understanding technology. Its mindset and process. Its not making mistakes. To underscore both TSMC and Pat Gelsinger its “execution, execution & execution” We couldn’t agree more. Pat certainly “gets it” the question is can he execute?

The tough road just became a lot tougher

Intel had a pretty tough road in front of it to catch the TSMC juggernaut. The road just got a lot more difficult to both catch them and beat them at their own game, that’s twice as hard.

However we think that Pat Gelsinger has the right idea. Intel can’t just go back to being the technology leader it was 10 or 20 years ago, it has to re-invent itself as a foundry because that is what the market wants today (Apple told them so).

It’s not just fixing the technology , it’s fixing the business model as well, to the new market reality.

It’s going to be very, very tough and challenging but we think that Intel is up for it. They have the strategy right and that is a great and important start.

All they have to do is execute….

Related:

Intel Will Again Compete With TSMC by Daniel Nenni 

Intel’s IDM 2.0 by Scotten Jones 

Intel Takes Another Shot at the Enticing Foundry Market by Terry Daly

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Intel Takes Another Shot at the Enticing Foundry Market

Intel Takes Another Shot at the Enticing Foundry Market
by Terry Daly on 03-26-2021 at 6:00 am
Categories: Foundries, Intel Foundry
6 Comments

Intel IDM 2.0

Intel made a big splash on March 23, 2021 by doubling down on manufacturing with the creation of Intel Foundry Services (IFS). The big announcement was supported by potential customers such as Qualcomm, Cisco, Ericsson, Google, Amazon, Microsoft, and IBM. With an accompanying $20B investment, the EDA and equipment industries, policymakers and governors were highly supportive.

Financial and industry analysts were a bit more skeptical. Pundits acknowledged new leadership in CEO Pat Gelsinger but recalled that Intel has tried this play before and failed. They pointed to the moat that TSMC has created in this space with its maniacal customer focus and execution excellence.

The strategy for an IDM to offer its capability to external customers as a Foundry is not without precedent. IBM made a similar move in the early 1990s and competed for almost 25 years prior to its acquisition by GLOBALFOUNDRIES. Samsung leveraged a big win with Apple into the Foundry model, and prior to the Intel announcement was alone in competing with TSMC on the leading edge.

Intel has substantial capabilities to bring to market, is establishing IFS as an “independent organization” with a separate P&L and says it will leverage three key pillars that it views as underpinning a world-class Foundry: Committed Capacity, Advanced Technology and Design Enablement. It asserts that it will differentiate on Service, Solutions and Scale. Fair enough.

But announcements are one thing; execution is another. The Foundry space is hyper-competitive, and despite Intel’s legacy IDM assets, it faces an uphill battle. One hopes that Intel has combined some deep introspection from its prior efforts with extensive benchmarking in the Foundry segment. Here are some lessons learned from a battle-scarred veteran of both IBM’s experience and that of GLOBALFOUNDRIES as a start-up in the pure-play Foundry industry – call it a preview of a day in the life of IFS.

“You can’t live with them and you can’t live without them.” Here we are talking about customers. They are the reason for your business existence, the source of income for innovation, investment, and shareholder return. They must be highly valued, the focal point for your company. On the other hand, they are demanding, but understandably so. After months designing products central to their market competitiveness and business success, they want their baby instantiated in hardware – ASAP – with cycle times faster than the raw process time of your factory. Top priority! IFS will have been an integral part of that creation, providing the design environment, IP, and perhaps some design services.

They expect “first time right” with high yields out of the chute – after all, they designed into your flow and used your design tools and IP blocks. They expect a seamless relationship with the OSAT partner, both in logistics and yield; you marketed a pre-qualified combination of silicon and packaging. They want immediate burst capacity to scale production and get their product into the marketplace – at benchmark yield. They will only pay for known good die; yield shortfalls to commit are on you. They want the ability to turn volumes on and off like a faucet. You have a lot of customers, so fab utilization is your problem.

And that was just your first customer. Then there is a dozen, then 50, then 100 – developed in pursuit of full fab utilization. Should you be more selective? The high-volume customers set an extremely high bar for execution – they tell stories of how life is so much better with TSMC. They have strong negotiating leverage. The small volume customers are similarly challenging. They all have a great growth story, but many are competing for the same end market. Are you double booking demand? The same work is required to qualify their parts, yet the demand is small and frequently moves to the right. Pricing is higher, but are these small accounts profitable? Can you afford to be more selective, or will you risk missing out on the next Qualcomm? You can only enable a certain number of expedites without slowing everything down in the line and risking supply commitments (that must be made “to the piece to the day”) to all customers. Allocating precious capacity is a challenge – every customer expects to be #1.

And then comes the call from the Intel mother ship. The Intel product team has finally finished its landmark design and needs everything cleared out of the way to qualify and ramp (notwithstanding that independent, separate P&L thing). No excuses. Go manage any necessary re-commits to your external customers; the future of Intel rests on getting this product to the marketplace. What? But you have contractual commitments to these customers. A solution is going to be painful but essential.

Next the Head of IFS R&D comes in the door, furious about the lack of tool and line priority for the qualification of the base Intel technologies and all the new technology platforms just committed to the marketplace. Remember that ultra-low power version? And the one that integrates embedded memory, RF, and the other features for the IoT customers just signed up? She needs priority over everything else to qualify these processes and the new ecosystem partner IP per IFS commitments.

Yikes. And the Intel Corporate COO and CFO are clamoring for improvements in your deteriorating operational and cost metrics driven by all this complexity. Then your lead fab manager calls with news of a new excursion that will impact supply commits. Seriously? When are those experienced Foundry hires from TSMC and GLOBALFOUNDRIES coming on board? Will they fit into the Intel culture? Will the Intel culture open itself to them? Can you accelerate the transformations needed to win? What a day!

Well, you get the idea. But Intel probably knows all this and has it figured out. Or do they? TSMC certainly makes it all appear effortless. But beneath their execution is brutally hard work. Perhaps a checklist for the refrigerators of Pat Gelsinger and Randhir Thakur will be of use for the journey ahead.

Critical Success Factors for Intel’s new Foundry business:

– Focus on initial target markets and customers, with a phased roadmap to expand over time.

– Competitive offerings tuned to those markets, including technology platforms, design enablement (PDKs, IP, services), and early access for lead customers to drive product-process co-optimization.

– Passion for the customer. Customer-centricity backed by organizational and business process re-design to translate passion to execution, including Product Management, Product Development, New Product Introduction, Supply Chain Management, and Customer Relationship Management.

– World class execution. Be the benchmark in manufacturing cycle times, yield (process and product); transparency (lot status, in-line parametric performance), quality and delivery commitments.

– Multi-tasking. Balancing the needs of internal and external customers and managing value chain conflicts, as Intel may be simultaneously competing with customers and outsourcing to other foundries.

– Scale. Establishing and maintaining scale to afford large annual R&D and capital investments.

– Consistently high factory utilization. There is nothing worse in chip manufacturing than an underloaded fab. Full utilization is required for profitability in this capital-intensive industry.

– Cost competitiveness across the board: Capex/$k (beware built-in costs on tool acquisition, install and hook-up), process complexity (beware designed-in cost), wafers, chemicals, gases, raw materials and operating supplies, labor, power, water, and other infrastructure support (exercise Intel VPA leverage).

Intel will have the benefit of depreciated fabs in mature technologies, but not on the leading edge.

This will be a transformation challenge of the highest order: from single customer (Intel) to multiple customers; from few high-volume parts to many high/medium/low volume parts; from a focused process technology menu (supporting only Intel products) to a diverse menu. And Intel is taking this challenge while struggling to “regain the recipe” on R&D execution. The toughest challenge may well be transforming culture, from “Intel knows best” to “the customer is central to our success and survival”.

In the end this will be a leadership challenge.

Many are pulling for Intel’s success. Why? The US needs a healthy Intel for national security and strengthening the US semiconductor manufacturing base (see The CHIPS ACT). The global semiconductor industry needs Intel to be successful in process leadership and manufacturing to broaden geographic and supplier diversification beyond TSMC and Samsung, as great as they are. And competition is always a good thing – for innovation, for customers, and ultimately for shareholders.

Wishing Intel all the success! It will be the run of a lifetime!

Terry Daly is a retired semiconductor industry executive, independent consultant, and senior fellow at The Council on Emerging Market Enterprises, The Fletcher School of Law & Diplomacy, Tufts University

 

Intel Will Again Compete With TSMC by Daniel Nenni 

Intel’s IDM 2.0 by Scotten Jones 

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Flex Logix Closes $55M in Series D Financing and Accelerates AI Inference and eFPGA Adoption

Flex Logix Closes $55M in Series D Financing and Accelerates AI Inference and eFPGA Adoption
by Mike Gianfagna on 03-25-2021 at 10:00 am
Categories: AI, eFPGA, Flex Logix

Flex Logix Closes 55M in Series D Financing and Accelerates AI Inference and eFPGA Adoption

Flex Logix is a unique company. It is one of the few that supplies both FPGA and embedded FPGA technology based on a proprietary programmable interconnect that uses half the transistors and half the metal layers of traditional FPGA interconnect. Their architecture provides some rather significant advantages. I wrote about their ground-breaking InferX X1 technology here. The company is gaining significant momentum in high-growth markets such as AI inference. Their low power opens up a lot of possibilities at the edge. Recently, Flex Logix announced a $55 million oversubscribed Series D funding round. This is a significant round of investment and opens up new possibilities for the company. I spent some time with their CEO, Geoff Tate to get some of the backstory behind this round.  Read on to get the details about how Flex Logix closes $55M in Series D financing and accelerates AI inference and eFPGA adoption.

Geoff Tate

First, a bit about Geoff Tate. Geoff has a storied career in semiconductors. After getting an MBA from Harvard Business School, Geoff did a stint as senior VP of microprocessors and logic at AMD. He then went on to lead Rambus from four people and $2 million in equity to a NASDAQ IPO and a multi-billion dollar market cap as its CEO and chairman. After several more CEO, board and advisory roles he co-founded Flex Logix as their CEO. Geoff has a strong command of the semi market, its trends and customer needs. His significant achievements essentially all came together to develop new and innovative solutions at Flex Logix.

During my discussion with Geoff, he explained that this funding round gives Flex Logix significant flexibility on how to grow the company. The plan is to double in size over the next year or so, with about 80 precent of the resources going to support the inference market. Geoff was quick to point out that he’s seeing substantial growth for the embedded FPGA product as well. This market seems to have reached something of a “tipping point”, with more and more customers now ready to integrate embedded FPGA technology into their advanced SoCs. Data center, 5G and base station designs are all moving toward embedded FPGAs. Geoff explained that these applications have always used discrete FPGAs. Embedded FPGAs offer the opportunity to reduce cost and power, with power being a critical item for all these applications.

I asked Geoff what caused embedded FPGAs to finally start taking off. He reviewed three key developments:

1) Proof the technology works – the price of entry for pretty much any new technology

2) Validation in real applications by early adopters. In this case, it was folks like Sandia Labs, Boeing, Morning Core (Datung Telecom), and DARPA. There was a compelling need to develop a domestic supply of advanced chips with embedded FPGA technology and this work laid the foundation for what was to follow

3) A mainstream application that proves success in a high-volume application. Geoff cited Flex Logix’s win at Dialog Semiconductor as a very high-volume application

With these three events the stage is now set for substantial growth in the adoption of embedded FPGA technology – watch this space. Of course, Flex Logix uses its embedded FPGA technology for its stand-alone chip products, so more proof there.

Back to some of the details of the funding round. Mithril Capital Management led the round with significant participation by existing investors Lux Capital, Eclipse Ventures and the Tate Family Trust. “We are impressed with the very high inference-throughput/$ architecture that Flex Logix has developed based on unique intellectual property that gives it a sustainable competitive advantage in a very high growth market,” said Ajay Royan, managing general partner and founder of Mithril Capital Management.

I concluded my discussion with Geoff discussing what the future looked like. Geoff sees significant growth across many markets, from AI inference at the edge to programmable networks in data centers, wireless networks and more. Geoff explained that, if you look at all the current and future opportunities, Flex Logix is essentially in the reconfigurable computing business. This was a great insight. We ended our discussion on that note. Now you know some of the backstory that allows Flex Logix to Close $55M in Series D financing and accelerate AI inference and eFPGA adoption.

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Reducing Compile Time in Emulation. Innovation in Verification

Reducing Compile Time in Emulation. Innovation in Verification
by Bernard Murphy on 03-25-2021 at 6:00 am
Categories: AI, Cadence, EDA

Innovation image 2021

Is there a way to reduce cycle time in mapping large SoCs to an FPGA-based emulator? Paul Cunningham (GM, Verification at Cadence), Jim Hogan (RIP) and I continue our series on research ideas. As always, feedback welcome.

The Innovation

This month’s pick is Improving FPGA-Based Logic Emulation Systems through Machine Learning. This paper was presented at the ACM Transactions on Design Automation of Electronic Systems in 2020. The authors are from Georgia Tech and Synopsys.

FPGA-based emulation, emulating a large SoC design through an array of FPGAs, is one way to model an SoC accurately yet fast enough to run significant software loads. But there’s a challenge: compiling a large design onto said array of FPGAs is not easy. A multi-billion-gate SoC must map onto hundreds of large FPGAs (300+ in some of the authors’ test cases), through a complex partitioning algorithm followed by multiple place and route (P&R) trials on “hard” partitions. P&R runs can be parallelized, but each still takes many hours. If any run fails, you must start over with a new partitioning or new P&R trials.

Because designers use emulation to optimize cycle-time through chip verification and debug, it is critical to optimize compile wall-clock time, within reasonable compute resources. Figuring out the best partitioning and best P&R strategies requires design know-how and experience from previous designs. Which makes this problem an appealing candidate for machine learning (ML) methods. The authors use ML to predict if a P&R job will be easy or hard and use this prediction to apply different P&R strategies. They also use ML to estimate best resourcing to optimize throughput and to fine-tune partitioning. They’re able to show improvements in both total compute and wall-clock time with their methods.

Paul’s view

Optimizing throughput in emulation is very relevant today as we continue to chase exponential growth in verification complexity. For typical emulation usage debug cycle time is critical and so compile wall-clock time is very important. The authors have shown a 20% reduction in P&R wall clock time which is very good. This paper is very well written, presenting some strong results based on using ML to predict if a P&R job will be “easy” or “hard” and then using these predictions to optimize partitioning and determine P&R strategies.

As with any ML system, the input feature set chosen is critical. The authors have some great insights here, in particular the use of Lloyd Shapley’s Nobel Prize winning techniques in game theory for feature importance weighting. One thought I have on possible further improvements would be to consider some local measures of P&R difficultyin their feature set – the features listed appear to all be global measures such as number of LUTs, wires, clocks. However, a local hotspot on a small subset of a partition can still make P&R difficult, even if these global metrics for the overall partition look easy.

The paper builds up to a strong headline result of reducing wall clock time for the overall P&R stage of emulation compile significantly, from 15 hours to 12 hours. Nice.

Jim’s view

Jim, an inspiration to many of us, passed away while we were working on this blog. We miss you dearly Jim. Wherever you’re watching us from, we hope we’ve correctly captured what you had shared with us live on this paper:

This is some impressive progress by Synopsys on FPGA-based emulation compile times. If it was coming from a startup then for sure I’d invest. “Outside” ML to drive smarter P&R strategies makes total sense, not only for emulation, but also ASIC implementation.

My view

I agree with Jim. This method should also be applicable to other forms of implementation: FPGA prototyping as well as FPGA emulation, ASIC implementation, and even the custom emulation processors that Cadence and Mentor have. Even for prototyping large designs which will go to production in FPGA implementations. I’m thinking of large infrastructure basebands and switches for example. I’m also tickled that while ML more readily finds a home in implementation rather than verification, here verification builds on that strength in implementation!

We know Jim would want us to continue this blog, as do Paul and I. We’re working to find a new partner to join us for next month. Stay tuned!

Also Read

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Smarter Product Lifecycle Management for Semiconductors

Smarter Product Lifecycle Management for Semiconductors
by Tom Simon on 03-24-2021 at 10:00 am
Categories: EDA, Siemens EDA

Lifecycle Management for Silicon

Product Lifecycle Management (PLM) for electronic systems has moved from a passive ‘fire and forget’ approach to one that is intimately involved not only during design, but also throughout the entire life of every unit delivered to the field. Siemens EDA has a white paper titled “Tessent Silicon Lifecycle Solutions” that talks in depth about the advances in PLM that have come about due to a number of forces. Not only are their new requirements, but there are large potential benefits to customers and manufactures that can translate into significant economic upside.

The white paper posits that there are three drivers for semiconductor industry growth: technology scaling, design scaling and system scaling. PLM, with a new vision make it into a Silicon Lifecycle Solutions (SLS) platform, can address the needs created by each of these drivers. Technology scaling introduces the possibility of new types of silicon defects. It also adds to the likelihood of more early failures and wear-outs. Design scaling adds more gates and pins, with lower visibility into the internal operation of chips. System scaling leads to the inclusion of silicon into new applications such as transportation, server farms and others that add reliability, safety and security requirements.

Siemens EDA suggests a completely new way to look at what PLM in the form of a SLS platform can offer. In design and manufacturing, applying advanced DFT techniques and diagnosis driven yield analysis can reduce costs and improve time-to market for semiconductor companies. However, further down the supply chain, an SLS platform has the potential to help out OEM customers with fine grain data about the chip’s real-world performance and operation. We also know that for ISO 26262 applications in the automotive space that there needs to be continuous diagnostics to verify and ensure proper system operation. For data centers or high demand applications, gathering data on chip operation can help detect security issues or performance bottlenecks caused by failures or system level interactions.

The Siemens EDA white paper articulates a vision for how a comprehensive SLS platform can be implemented to help gain the advantages mentioned above and others that can help with product development. Each stage of a product’s life cycle can be linked together providing feedback for continuous improvement and also forward predictive insights to improve system operation. This last point needs to be emphasized – a SLS platform has the potential to help optimize system performance in the field after installation.

What’s involved in implementing an SLS platform? At the front end there are on-chip resources, such as DFT logic and smart tools, parametric monitors and functional monitors to ensure that the hardware and software are operating as intended. In-system DFT and other monitors can produce prodigious amounts of data, so it is essential that there are tools to configure and manage these data streams. The Siemens SLS platform leverages tools that handle, process and correlate the data so it can be effectively used.

Lifecycle Management for Silicon

The white paper describes the Tessent SLS plaform with its four distinct layers. At the top it has software to assess, monitor and manage. Next is rapid analytics to help identify issues and their causes. Under this there is a database layer for managing the data from manufacturing, operation, and even databases for security with information to help identify cyber-attacks. The application layer has components that will be familiar to any hardware designer like DFT, BIST, and Tessent Diagnostics. It also ties into other domains such as safety analysis, predictive and preventive maintenance, security, and more.

The white paper discusses the details of how the Siemens SLS platform fulfills each of these layers. The Siemens Silicon Lifecycle Solutions platform is designed to provide all the parties in the design, manufacturing and deployment of semiconductor-based products with a means to ensure high quality, predictable reliability and efficient operation. We are seeing some of the anticipated benefits of Mentor’s acquisition by Siemens in the breadth and scope of this solution. The white paper is available on the Siemens EDA website.

Also Read:

Observation Scan Solves ISO 26262 In-System Test Issues

Siemens EDA wants to help you engineer a smarter future faster

Happy Birthday UVM! A Very Grown-Up 10-Year-Old

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SoC Integration – Predictable, Repeatable, Scalable

SoC Integration – Predictable, Repeatable, Scalable
by Bernard Murphy on 03-24-2021 at 6:00 am
Categories: Arteris, IP, Magillem

IPDD SIPD stack min

On its face System-on-chip (SoC) integration doesn’t seem so hard. You gather and configure all the intellectual properties (IPs) you’re going to need, then stitch them together. Something you could delegate to new college hires, maybe? But it isn’t that simple. What makes SoC integration challenging is that there are so many parts including IPs and connections. . Some are moving parts, changing as bugs are fixed. Some, like the interconnect, can only be completely defined when you integrate.

There’s a lot of interdependence between these parts. Make a small change like importing a new revision of an IP or adapting to a spec tweak, and the consequences can ripple through your integration. Not a big deal, perhaps, early in design. But a very big deal when you’ve finally wrestled hundreds of IPs and tens of thousands of connections into behaving. Then you have to drop in a couple more changes. Surely there’s a better way?

Merging Design Data Integration and NoC Integration

It is now possible to script much of design data assembly, configuring IP models and stitching them into a top-level netlist. Experts define interconnect as an independent step, to manage connectivity expectations with quality-of -service (QoS) goals. Altogether a surprisingly manual, highly human-dependent approach to assembling the crown jewel at the heart of a critical product plan. Experienced engineers and a proven base of scripts make it work but can look quite fragile when creating a new product family or when key team members leave.

A better way is to merge a proven, robust strategy for design data integration through IP-XACT with a proven approach for interconnect generation through network-on-chip (NoC) technology.

Design Data Configuration Through IP-XACT

IP-XACT usage is now well-established and very active. Teams get a consistent representation of an IP today in the IP-XACT model, whether from Arm, Synopsys, Cadence or any other supplier. Some designers still see these models as a passive store for bits of information they need (like register data). But they’re on the trailing edge of a growing trend to using these models directly in IP-XACT-based integration. Initially starting in automotive and consumer semiconductor shops, IP-XACT assembly is now spreading to the big systems houses, communications giants, medical instrumentation experts and more. They still have the flexibility to hand tweak where needed, but only where needed. Our one-time artisanal pride in hand-assembling or scripting top-level netlists is losing out to the urgency of system-level needs.

Naturally, this simplifies the connection to NoC generation. When each IP-XACT model is already configured with interconnect interfaces, NoC generation can pick those up seamlessly. Designers optimize for QoS, power, floorplan and other key performance indicators (KPIs), confident that the IP interfaces are correct. If a new IP drop comes in, the NoC can be reconfigured for those interface changes with fewer opportunities for human error.

Software Interface Generation

Each IP-XACT model comes with detailed register map information: zero-based register offsets, bitfield widths, descriptions, access types, etc. The interconnect designer defines memory map offsets for each IP connection when building the NoC. Together this combination achieves the complete (hardware) memory map. Software creates or runs checks to ensure there are no overlaps and that each bit can indeed be read or written along with other options as defined. You can run those checks in simulation or formal verification.

Integrators can automatically generate a complete set of software header files using symbolic names for each register, bitfield, access macro and possibly sequence macros. Files automatically update each time the underlying design changes, whether through an IP or a NoC update. The software team can continue their development and debug, confident that the header files will be accurate against the latest design update. Once more – fewer opportunities for human error.

Documentation and Traceability

There is an enterprise component to product build that does not get much press in design flows. In the good old days, tech pubs would start with a largely frozen spec from which they would build product documentation for in-house or customer needs. A few engineering reviews, and they could sign off the doc. Now that specs and implementation decisions are evolving in larger designs on more rapid cycles, mistakes are more likely. Reviews are still essential for free-form text, but you can derive tables like clock, reset, memory maps from the design. Which become fair game for automating into the documentation, simply to ensure they are always in sync with the design. XML standards make the connection to the design definition much simpler.

Another enterprise need is to generate traceability documentation, essential for any safety-critical design. This is necessary in in automotive, aerospace and defense, industrial or medical domains. Traceability is another area that has historically required a lot of manual creation and checking. More automation could simplify these tasks, at least close to the design. This is an emerging area with exciting possibilities.

Talk to Arteris IP. They are building SoC integration solutions for current and future needs.

Also Read:

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Intel’s IDM 2.0

Intel’s IDM 2.0
by Scotten Jones on 03-24-2021 at 4:00 am
Categories: Foundries, Intel Foundry
25 Comments

Slide1 1

In January I presented at the ISS conference a comparison of Intel’s, Samsung’s and TSMC’s leading edge offerings. You can read a write-up of my presentation here.

With the problems going on at Intel, that article generated a lot of interest in the investment community, and I have been holding a lot of calls with analysts who are trying to understand what is going on. Since I presented at ISS and have been participating in calls, I have continued to put effort into analyzing and understanding what is going on with Intel. This afternoon Pat Gelsinger announced Intel’s IDM 2.0 plan to bring the company back to technology leadership.

Before I get to today’s announcements I wanted to start with a little history and how intel got to where they are today.

CEOs

From 1968 until 2005 Intel had four highly technical CEOs, in fact they are among the giants of our industry. The first CEO was Robert N. Noyce, a Ph.D. in physics and a co-inventor of the Integrated Circuit, Next up was Gordan Moore, a Ph.D. in chemistry and the man who coined Moore’s law, the law that has propelled our industry for decades. Moore was followed by Andrew S. Grove, a Ph.D. in chemical engineering. When I first started in the industry, Grove’s book “Physics and Technology of Semiconductor Devices” was the bible of devices and processing, Grove also discovered the Deal-Grove Oxidation law with Bruce Deal. Grove was followed by Craig R. Barrett, a Ph.D. in materials science and professor at Stamford University.

In 2005 Paul S. Otellini, an MBA became Intel’s first non-technical CEO. It was at the end of Otellini’s tenure that Intel began to slip from their process introduction cadence. Otellini was followed by Brian M. Krzanich who has a B.S. in chemistry and a manufacturing background, but, as Stacy Rasgon observed in a recent Podcast, for some reason he never really seemed to get his arms around Intel’s manufacturing issues with substantial yield problems with Intel’s 10nm process on his watch. The podcast is available here.

In 2018 Robert H. Swan, another MBA became CEO and held that position until recently.

I believe a company like Intel that is a historical technology innovator, needs to be led by a technical visionary. Recently Patrick P. Gelsinger has taken over as CEO, he has an M.S. in electrical engineering, was the lead architect for the 80486 and is a well regraded technologist in the industry. Only time will tell but he seems like a good choice to lead a technical turn around.

Figure 1 presents Intel’s CEO history.

Figure 1. Intel CEOs.

 Nodes

Figure 2 presents Intel’s nodes versus time and puts into perspective just how dramatic Intel’s delays have been.

In the first column of the table are the node names and in the second column is Intel’s actual introduction dates through 22nm, and then expected dates for subsequent nodes if Intel had kept on the same cadence. From 2001 when Intel introduced 130nm there was a steady two-year cadence of new processes and innovations (the two-year cadence goes back even before 130nm, but I truncated the sequence to make it easier to present). 90nm in 2003 saw the introduction of embedded silicon-germanium for strain, an industry first, 2005 saw the industry’s first use of high-k metal gate (HKMG), something the foundries did not introduce until 28nm in 2011. In 2007 Intel introduced 32nm and finally in 2011, 22nm with the industries first FinFET, something the foundries did not introduce until 2014. Clearly Intel was executing industry leading technologies on a regular cadence.

The third column of the table presents “reset 1” where 14nm was a year delayed to 2014, 10nm was expected in 2017 on a three-year cadence and eventually as 10nm was further delayed 7nm was expected in 2021. The next column has reset 2 where 10nm enters volume production in 2019 and then 7nm is delayed until 2022 originally blamed on COVID. The next column has reset 3 where 7nm production is now expected in 2023, this is an amazing delay for a process that would have been expected in 2017 back when Intel was executing to a two-year cadence. The next column presents “reset 4” based on what could happen if Intel got back on a two-year cadence.

The last two columns present the interval between each process in years and comments on the processes.

Figure 2. Intel Nodes Versus Time.

 Hyper Scaling

Intel’s success in introducing industry leading technology in advance of the foundries led to hyper scaling, an acceleration of scaling per node. Historically a typical node delivered 2x the density but now Intel targeted 2.5x for 14nm and 2.7x for 10nm. I believe this played a role in Intel’s slips. If you think about coming up to bat in Baseball, you strike out a lot more when you are trying to hit home runs then when you are trying for singles. Hyper scaling was introduced while the industry was seeing a dramatic increase in process complexity due to multi-patterning.

Figure 3. illustrates Intel’s hyper scaling.

Figure 3. Hyper Scaling.

 While Intel has been slipping on process introductions, Samsung and TSMC have been introducing new nodes at a faster rate. The foundries generally take smaller jumps in density but do it more frequently. I believe this reduces risks and increases the rate of learning.

Figure 4. illustrates the foundries introduced five full nodes between 2014 and 2023 while Intel introduced 3 nodes.

Figure 4. Node Introductions.

There are some subtleties this figure does not address, for example Intel has 14, 14+, 14++, 14+++ and 14++++ variants and for 10nm has 10 and now 10SF. However, these plus processes are performance enhancement and do not improve density meaning they are missing out on density improvement learning. The foundries also have “half-nodes not shown here, for example Samsung has 11nm, 8nm, 6nm and 4nm process nodes, and TSMC has 12nm, 7nm plus, 6nm, 5nm plus and 4nm and most of these do provide density improvements.

Culture and brain drain

With Intel’s several year lead on key technologies such as HKMG and FinFETs, Intel had an incentive to not share technical information. Intel was known in the industry to buy tools, bring them in house and not share what they were doing with the Original Equipment Manufacturers (OEM). This helped to protect Intel’s technology but may have also cut them off from taking advantage of the OEM’s increasingly sophisticated in-house process development capabilities. When I first started in the industry, we bought process tools, brought them in house and developed a process to run on them. Today the OEMs provide integrated sets of tools and processes that provide complete process modules.

Internally I have heard that very few people at Intel have a holistic view of a process, that generally engineers only know their tool, if true this would make it difficult to troubleshoot complex interactions between tools.

It is reported that there has also been an exodus of talent from Intel where many of the more experienced engineers have left. I know people who used to work at Intel and told me they had no intension of leaving or retiring but they were offered such generous financial packages that it did not make sense not to leave.

Intel is only as good as their people.

Double edged swords

Intel has two practices that I will refer to as double edged swords because while they provide benefits they also cause problems.

The first one is “copy exact”. At Intel when a process is developed at one of the development fabs, the entire tool set is frozen and when the process is transferred to a production fab an exact replica of the development tool set is installed and set up the same way. This ensures that the process put into manufacturing exactly copies the process that was developed. This helps with initial yield but the downside to copy exact is that as time passes the OEMs are introducing improved tools and even after several years have passed new lines are being set up with tools that are several years old. If you consider Intel was adding 14nm capacity in 2020 and the process was developed around the 2012 timeframe, you can see where this could be a significant issue.

The second issue is nonstandard design flows. Now I am not an expert on design flows, but my understanding is foundries have design flows based on PDKs, with standard cells and relatively simple design rules. I have heard that Intel does a lot of custom tuning of cells. The custom tuning may help squeeze the last little bit of performance out of a design, but it also makes it harder to deal with process changes or port design to a whole new process. Because foundry customers often try to second source parts with more than one foundry, they must be efficient at adapting to different processes. I cannot help but wonder whether this plays a role in Intel’s +, ++, etc. process not including shrinks and also in Intel’s 10nm yield issues.

10nm

Intel’s 10nm process has suffered from well documented delays and yield ramp issues. Intel’s 10nm process was originally targeted to utilize EUV but then due to delays in the development of EUV Intel had to resort to optical multipatterning. It appears that the transition in this process to optical multipatterning did not go smoothly.

For example, at 10nm Metal 0 (M0) and Metal 1 (M1) are patterned with Self Aligned Quadruple Pattering (SAQP) with 2 and 3 cut masks. This is the only use of SAQP in interconnect layers that I am aware of in the industry. Intel’s 10nm M0 and M1 also have the industries only use of cobalt interconnects and aluminum oxide tip to tip spacers I am aware of. The net result is a more complex fabrication scheme for these layers than I believe anyone else in the industry uses. SEM shots I have seen of 10SF M0 and M1 patterns still do not look good compared to foundry 7nm M0 and M1 patterns.

There was a rumor at one point that Intel was going to adopt EUV for a couple of layers for 10SF to address yield issues but that did not materialize, I can’t help but wonder how much the difficulty of porting designs to EUV with the non-standard design flows discussed in the previous section played into that decision.

Node Name Disconnect

There was time when node names for logic processes were the gate length tying them to a specific measurable feature. That is no longer the case and node names today are largely the creation of the marketing departments with no correlation to measurable features. There is a large disconnect between Intel’s node names and the foundry node names. For example, I have taken TSMC’s node names and plotted them versus TSMC’s actual measured transistor density. I have fit a curve to that data and gotten a good curve fit with an R2 value of 0.99, see figure 5.

Figure 5. TSMC Node Names Versus Transistor Density.

Using the formula for the line in figure 5. and actual measured Intel transistor density we can determine equivalent node names for Intel’s processes using TSMC’s trend. The net result is Intel’s 10nm process has a TSMC equivalent node of 7.4nm and Intel’s forthcoming 7nm process is projected to have a TSMC equivalent node of 4.3nm (based on an announced 2x density improvement). Figure 6. presents a comparison of TSMC and Intel processes with TSMC equivalent nodes for Intel processes out to a projected 3nm process. Please note that the values in this table are updated relative to a previous article.

Figure 6. Node Name Disconnect.

 From the figure we can see that Intel’s 7nm process falls between TSMC’s 5nm and 3nm process in density. I would like to encourage Intel to consider changing their 7nm process node name to 4nm to more accurately reflect how it compares to TSMC’s industry leading process and address a lot of confusion among analysts on how the processes really compare.

The other interesting observation is if Intel can get back to a two-year node cadence with 2x density improvements around mid-decade they can be roughly at density parity with TSMC although generally about a year behind.

I do want to note that density is not everything, particularly for Intel’s microprocessors where performance is king. As best as I can estimated Intel’s 10SF process and TSMC 7nm process have similar performance, certainly AMD is producing microprocessors on TSMC’s 7nm process that are competitive with Intel’s microprocessors. My expectation is that Intel’s 7nm process will be competitive with TSMC’s 3nm process on a performance basis but with TSMC 3nm entering risk starts later this year and production next year, Intel needs their 7nm process to be complete by the end of next year and ready for high volume production in 2023 or AMD could gain a process advantage by utilizing TSMC 3nm.

In terms of Intel’s catching or passing TSMC, as Stacy Rasgon observed in the PodCast I mentioned earlier, TSMC would have to stumble. I have had several people ask me why Intel does not just accelerate 5nm development. As we will discuss shortly Intel has already struggled with 7nm, a process where the main innovation is EUV that is already in second generation production at Samsung and TSMC. At 5nm I expect Intel to adopt Horizontal Nano Sheets (HNS) a process I believe still has unsolved engineering challenges. Samsung is trying to begin risk starts on their 3nm GAA process using HNS later this year and I am hearing that process is delayed.

IDM 2.0

This brings us to todays presentation on Intel’s IDM 2.0 announcement.

Intel’s key goals are:

  1. Lead in every product category they participate in.
  2. Innovate with boldness.
  3. Execute flawlessly.
  4. Foster vibrant culture.

As general goals these are great. There appears to be a recognition of the kinds of cultural issues we discussed earlier, and execution definitely needs to improve. A favorite comment of mine from tonight was bringing back a “Groveian culture of execution” in reference to former CEO Andy Grove who was well know for relentlessly driving execution.

The central tenants of IDM 2.0 for Intel are:

  1. Utilize the Intel internal factory network to build the majority of Intel’s products internally.
  2. Expand use of foundries so that all products have some level of foundry production.
  3. Increasing engagement with TSMC, Samsung, GLOBALFOUNDRIES (GF) and UMC.
  4. Plan to be a major foundry with US and European based manufacturing to balance the reliance on Asia.

There was slide that showed something like 80% of leading edge in Asia centered around Taiwan and South Korea, 15% in the US and 5% in Europe.

The idea of making the majority of product internally while also expanding foundry use is somewhat at odds to each other. It seems like foundry is being used to hedge Intel’s bet on getting 7nm out on time. Also, how do you engage more with foundries while starting a foundry business to compete with them.

There was discussion that Intel is making big investments in industry standard PDKs and simplified design rules. This addresses the earlier comments on Intel’s nonstandard design practices and is both a key enabler for servicing foundry customers and making it easier for Intel to port their own designs to foundries.

There was a lot of emphasis on Intel’s packaging technology with EMIB and Foveros enabling tiles as opposed to chiplets where the quality of the chip-to-chip interconnect is more like long wires on a chip.

Intel is going to partner with IBM on technology, I am not sure I see this as a plus. Samsung and IBM developed the 5nm process Samsung is running and it isn’t competitive with TSMC. They also worked together on the HNS technology in Samsung’s 3nm process and that is even less competitive with TSMC.

Misjudging EUV

I found the comments on the issues with 7nm very interesting. 7nm was developed to limit EUV usage due to “immaturity”. Now that EUV is more mature they have rearchitected and simplified the process using 100% more EUV layers.

What I find particularly interesting is the problems at 10nm can be traced to expecting EUV to be ready before it was and having to redo the process and then at 7nm to underestimating EUV readiness and having to redo the process. This is suggestive of a fundamental problem in Intel’s ability to understand the readiness of a process and appropriately plan for it. This is particularly glaring considering TSMC executing flawlessly on implementing EUV on their 7+ process and 5nm process. Samsung also did a good job of timing EUV with their decision to only have a 7nm process that uses EUV for critical layers (TSMC did an optical 7nm and then EUV 7+ process).

Another area around Intel’s EUV implementation that continues to concern me is availability of tools. I have heard that Intel has pushed out or canceled EUV tool orders during the 7nm delay. If they are pushing out tool to get NXE:3600D tools in place of NXE:3400C tools that makes sense but if they are giving up EUV slots they may not be able to get the EUV tools they need when they need them. TSMC is buying tools to continue to the 5nm ramp, equip for 3nm and for 2nm development, Samsung is doing the same plus has started using EUV for DRAM. SK Hynix recently committed to over $4 billion dollars of EUV tools for DRAM.

Intel has roughly 170k wafer per month (wpm) of 14nm capacity and is ramping 10nm with around 130k wpm of current capacity. If they built out something like 140k wpm of 7nm they could need around 45 EUV tools. They also announced plans for two foundry fabs that could need another 30 EUV tools. Where are they all these EUV tools going to come from?

Foundry pluses and minuses

Part of today’s announcement was that Intel is going to get into the foundry business with a dedicated foundry business with its own P&L and reporting directly to the CEO. Further they plan to build two dedicated foundry fabs in Arizona for approximately $20 billion dollars. I estimate this investment is sufficient for 2 – 40k wpm fabs running 7nm. CORRECTION, these fabs are not dedicated to foundry, they will produce Intel’s own products and also support foundry.

This begs the question of why Intel is doing this and what are the pluses and minuses. The funny part about this is some people have been suggesting Intel should go Fabless and citing AMD going fabless as an example.

Some thoughts on this:

  1. Pat Gelsinger mentioned that they think foundry is a good business and want to be in it. The interesting thing about foundry is it an excellent business for TSMC but not as good for other leading-edge competitors who have much lower margins. TSMC’s margins for Q4-2020 were around 54%, their next biggest competitor who publicly discloses their results is UMC and their margins for Q4-2020 were only around 24%, SMIC and GF have had many years with negative gross margins.
  2. Intel was in the foundry business before and failed. Pat admitted they had not been serious about it before. My observation when they were in the foundry business was, they would introduce a new process for their microprocessors and then a year or more would pass before the foundry version was available. To send the message that you are serious in the foundry space, the processes would have to come out at the same time. Pat talked about making the full portfolio of Intel technology available to foundry customers including process technology, IP and packaging technologies. Intel will offer their own cores and support Arm cores.
  3. Intel plans to build two fabs in Arizona for foundry and then possibly dedicated capacity in Europe in the future, certainly dedicated capacity helps to send the message they are serious and will commit to meet customer needs.
  4. There is a lot of push right now in the US and Europe for onshore leading edge manufacturing and the promise of subsidy money. Intel could potentially get government money and they are going after department of defense opportunities.
  5. If you look at TSMC they build a fab for a particular technology and in many cases the fab stays on the technology forever. TSMC is still running 130nm, 90nm, 65nm, 40nm, etc. on 300mm wafers. Somewhat counter intuitively new processes have lower margin because the equipment is depreciating. TSMC often talks about a new process pulling down corporate margins by about two percentage points for the first two years it is in production. Once a fab equipment set is fully depreciated, the wafer manufacturing cost is cut by more than one half but the foundries don’t pass all of the saving on to the customers. The net result is the older fabs generate the highest margins. At Intel all the fabs making processes larger than 32nm have been converted to smaller nodes.
  6. A key consideration in all this is manufacturing scale. With scale you get more learning, and you can amortize the cost of developing a process over more wafers. This is what doomed GF 7nm, they were only going to build out 15k wpm of 7nm and that was not enough scale to stay competitive. By being in the foundry business Intel can build and maintain more scale. If they do not get in the foundry business, outsourcing to foundries and any market share losses to AMD reduce Intel’s scale potentially starting a death spiral. I was asked on a call whether Intel ran enough wafers to compete with TSMC, TSMC has roughly twice the total 300mm capacity of Intel but Intel’s capacity is concentrated more toward the leading edge meaning they run similar numbers of leading edge wafers, see figure 7.

Figure 7. Critical Mass.

  1. My big concern in all this is that it will take years to build up this business and engineering talent will have to be diverted to designing, building equipping and starting up the new fabs. Foundry specific versions of processes will have to be developed and PDKs built. This risks taking focus off of what is in my view Intel’s single biggest need right now, and that is to get 7nm out with good yield. Intel is also still struggling to make enough 10nm wafers.

Go Fabless

There has been a lot of talk about why Intel does not just go fabless like AMD did. There are several reasons why this is not a comparable situation:

  1. AMD went fabless because they had too, they simply could not afford to maintain a competitive fab capability.
  2. AMD was able to spin out their Fabs with backing from oil money. At the time AMD only had two – 300mm fabs with a combined capacity of around 45k wpm. Intel has roughly 15 logic fabs with around 450k wpm of capacity. Who is going to buy and be able to support that scale of manufacturing? Also keep in mind that GF lost money for a many years, who would be willing to support large losses from the Intel fabs.
  3. If Intel were to try to transfer all their business to a foundry even TSMC would need many years to build up the capacity. I suppose you could ask TSMC to take over Intel fabs but they would likely want to do a lot of retooling.
  4. If Intel were to go to TSMC, TSMC’s wafer prices are higher than Intel’s cost and it would drag down Intel’s margins. Intel’s internal manufacturing cost is higher than TSMC’s internal manufacturing cost, but TSMC adds an average gross margin of 54% to their wafers for sale. Although with Intel’s volumes they would pay a significantly lower margin, the margin would still yield wafer prices higher than Intel’s cost. Intel noted this on a previous call discussing this issue.
  5. In my opinion the best option for Intel is to get 7nm out the door, get back on track and make their products internally. They should hedge their bets at foundries to some extent but if they outsource too much, they lose scale.

To-Do List

I was writing a “What’s Wrong with Intel and How to Fix It” article before today’s call and I had been building my Intel to-do list. Here is my list with where things are after today:

  1. Hire a technical visionary CEO – Pat Gelsinger must show he can get the job done but he is certainly well regarded.
  2. Address the culture issues and brain drain – this seems to be recognized as a problem and getting attention. Some key players have returned.
  3. Adopt industry standard design practices – this was discussed today and is underway.
  4. Abandon “Copy Exact”, equip fabs with the best tools available at the time and take full advantage of OEMs process capabilities – I have not heard of any discussion on this.
  5. Go to more frequent new nodes with smaller jumps to accelerate learning and reduce risk – there was discussion today about fixing the development process and getting to a yearly cadence.
  6. Update node names – align nodes names with what the foundries are doing – I think this would help reduce confusion, but I do not know if it is being considered.
  7. Get 7nm into production by the end of 2022 and high volume in 2023 – I think this should be Intel’s number one priority.
  8. This one was not on my list until today, but I think Intel must be careful not to let building a foundry business dilute focus and interfere with execution. This is a lot to take on and frankly I am not convinced this is the right move at this time. Certainly, this could be good for the US, for the electronics industry starved for chips and for the defense department but Intel has to get back on track on process development.

Podcast EP12: A Close Look at Intel with Stacy Rasgon