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Semiconductor Expert Forum

Podcast EP4: Can China Really Become Self-Sufficient in Semiconductors?

Podcast EP4: Can China Really Become Self-Sufficient in Semiconductors?
by Daniel Nenni on 01-22-2021 at 10:00 am
11 Comments

Dan and Mike are joined by industry expert Robert Maire for a discussion on China based semiconductors. Robert is an internationally recognized expert on all aspects of semiconductor manufacturing. He joined SemiWiki in 2015 and his blogs have garnered more than 2 million views and many pointed discussions. Robert founded Semiconductor Advisors in 2007. Before that he held executive level positions with Morgan Stanley, Donaldson, Luftkin & Jenrette, Bear Sterns, and Needam & Company.

Official Bio: Robert Maire is President of Semiconductor Advisors, a consulting firm that provides financial and strategic advisory services to technology companies as well as investors specializing in the semiconductor, semiconductor equipment and electronic technology sectors.  Prior to that, he was among the first Wall Street analysts to cover semiconductor & semiconductor equipment companies for Morgan Stanley, DLJ, Bear Stearns and Needham, spanning a period of over 20 years. Mr Maire was responsible for raising billions of dollars, more than any other financial professional in the industry, through IPOs and other financing activity for companies such as Applied Materials, KLA, ASML, Sandisk, Agilent, Veeco, Cymer, Rudolph, MKS and many others.  He has provided critical insight and advice on many M&A transactions. He has been cited by both the Wall Street Journal and Institutional Investor for his analysis work.  He publishes his acclaimed “Semiwatch” newsletter, which is a leading source of information and opinion for investors in the sector. He is frequently quoted in financial media such as The Wall Street Journal, Barrons and numerous online sites . He holds BSEE and BSCS degrees from the State University of New York at Stony Brook.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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CEO Interview: Lee-Lean Shu of GSI Technology

CEO Interview: Lee-Lean Shu of GSI Technology
by Daniel Nenni on 01-22-2021 at 6:00 am
Categories: CEO Interviews, IoT, Security

Shu

Lee-Lean Shu co-founded GSI Technology in March 1995 and has served as President and Chief Executive Officer and as a member of the Board of Directors since its inception. In October 2000, Mr. Shu became Chairman of the Board of GSI Technology. Mr. Shu was has held various management positions in SRAM and DRAM designs at Sony Microelectronics Corp and AMD from July 1980 to March 1995. Shu holds a B.S. degree in Electrical Engineering from Tatung Institute of Technology and an M.S. degree in Electrical Engineering from the University of California, Los Angeles. Mr. Shu is the recipient of the award of Inventor of the year, 2017 from SVIPLA.

Tell me more about GSI Technology?
GSI Technology was started in 1995 and quickly became a leader in the global high performance SRAM market. In 2015 we acquired a very early-stage startup in the AI space, which enabled us to combine their technology and software with our advanced hardware design team to create and deliver our Associative Processing Unit (APU) chip. The first-generation device is called Gemini-I.

What challenge is your APU solving?  
At a high level, the APU is addressing the challenge that Von Neumann architectures present when attempting to increase compute performance on big data workloads. Processing cores have been increasing in speed, but they continue to use the Von Neumann architecture, so the limits of Moore’s law, power dissipation, and even more importantly the I/O limits brought about by the need to constantly move the workspace data in and out provide reduced system level benefits. The design philosophy in place now to address the Von Neumann issues is to concentrate more of the same processing in less space rather than truly increasing native processing capability – essentially putting more cores to the chip. However, this just miniaturizes the big server problem. It does not eliminate the Von Neumann I/O bottleneck because you still have to get external data into and back out of those cores. The current treadmill of reducing the size of a core and memory combination and then massively duplicating it provides more of the same compute in a smaller space with only limited power savings and ultimately not very much efficiency in an end-to-end system improvement.

Why is the GSI APU important to data processing?  
By removing or reducing the I/O cycles used at a system level, the clock speed can be reduced, providing a dual benefit of faster results and lower power. This increases processing efficiency.

What are the benefits of using Gemini?  
The Gemini technology results in significant increases for inference workloads (reduction of big data processing times from seconds to milliseconds, for example). The Gemini is akin to having a memory with RISC Boolean processing capability, (note: NOT a number of RISC processors with memory). It is cycle-by-cycle programmable on its memory compute. Due to this flexibility, it also has performance improvement in workload functions that can be efficiently decomposed into Boolean operations. These benefits avail themselves particularly to very large data set problems.

What is the roadmap for Gemini?  
Gemini-I is available today for shipment. We will be offering more options on the Leda boards in the next couple of quarters. The next-generation chip, Gemini-II, will be available in 2022. In this new chip, we have increased the L1 memory by 8x and will also double the clock frequency. This will allow us to further penetrate the big data market.

What applications do you see Gemini powering in the next 5-10 years?  
Currently, much effort across the industry is being expended on improving training. This is because training is not only done on the initial off-line evaluation of the problem, but also whenever completely new information arrives. Data is only increasing in volume, and the results of searches are only increasing in need as more users are brought on. The Gemini currently is well suited for the inference operation as opposed to the one-time training effort. Also, the goal of all this massive data collection is multi-faceted: data can provide information, which can provide insights, which can be used to improve a criterion or change a behavior. The last output of improvement is being sought after in all industries. The Gemini can accelerate getting this information in real-time for those markets where the fast response from a huge data store enables improvements. Some examples of this includes medical research, personal medical assistance, facial recognition, NLP, e-commerce, space-based environmental monitoring, actual prevention systems (cybersecurity, IIoT, physical security), and traffic intelligence systems.

ABOUT GSI TECHNOLOGY
Founded in 1995, GSI Technology, Inc. is a leading provider of semiconductor memory solutions. GSI’s resources are focused on new products that leverage the strengths of its legacy SRAM business. The Company recently launched radiation-hardened memory products for extreme environments and the Gemini APU, a memory-centric associative processing unit designed to deliver performance advantages for diverse AI applications. The APU’s architecture features massive parallel data processing with two million-bit processors per chip. The massive in-memory processing reduces computation time from minutes to milliseconds, even nanoseconds, while significantly reducing power consumption with a scalable format. Headquartered in Sunnyvale, California, GSI Technology has 172 employees, 114 engineers, and 92 granted patents. For more information, visit gsitechnology.com.

Also Read:

CEO Interview: Arun Iyengar of Untether AI

CEO Interview: Tony Pialis of Alphawave IP

CEO Interview: Dr. Chouki Aktouf of Defacto

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The Question That Has Guided My Analog Mixed Signal Career

The Question That Has Guided My Analog Mixed Signal Career
by Steve Logan on 01-21-2021 at 10:00 am
Categories: EDA
1 Comment

The Question That Has Guided My Analog Mixed Signal Career

I remember it like it was yesterday. I was sitting at lunch with good friend Scott Santandrea, explaining my struggles to get traction with the sales channel for the Analog to Digital Converter product line I was managing. My business line had been spending a lot of resources developing high-performance 24-bit delta sigma and 20-bit SAR ADCs. I was frustrated with being aced out by microcontrollers with crummy integrated ADCs. As we kicked around ways to gain mindshare with the Maxim and distributor sales forces, Scott dropped a line on me that I’ve never forgotten:

“Do you care about what you’re measuring?”

That’s it! Because if you care about what you’re measuring for your analog to digital conversion, you should clearly choose my product line. I loved it. I started using the tagline with the field immediately. If you care about what you’re measuring, why would you use an ADC inside a microcontroller? One that was specified as 12 bits but with 8 actual bits. Or listed at 16 bits and providing 10 or 11 bits.

 

Now, in fairness, the year was 2011 and microcontroller ADCs have come a long way since then. As have discrete ADCs. More on that later.

On a personal level, I look back and it’s a sentence that has defined my career. From my years of marketing ADCs and DACs, to my current role as an account manager, “do you care about what you’re measuring?” has guided me (and many others in the measurement field, I’m certain). If you’re an industrial company measuring eddy currents on turbines, you care about what you’re measuring. If you’re making weigh scales for trucks, you care about what you’re measuring. If you’re detecting particulates in blood or other fluids and need a high degree of accuracy, you definitely care about what you’re measuring. If you’re developing a MIMO WLAN transceiver and need to upgrade from 1024 QAM to 4096, you care about what you’re measuring.

The beauty of the question is that it applies for so many different applications.

Having spent the majority of my career in the analog mixed signal space, I’ve loved countering the notion that “everything is going digital” with “the real world is analog and always will be.” In order go get those measurements into the digital domain, or from digital back to analog, you need ADCs and DACs. The truth is that not every ADC or DAC conversion needs to be high quality. Sometimes, you just need to know your battery voltage is 3.3V and not 2.5V. Or that a temperature reading across a thermistor equates to 25C and not 50C. In those cases, a micro’s ADC will work just fine – and the cost is essentially free in 2020. But when you care about the difference between 3.31V, 3.30V and 3.29V, or the difference between 24.9C and 25.0C, that’s when you care about what you’re measuring.

For the next few weeks, I’ll be writing a series of posts centered around the question of “Do you care about what you’re measuring?” I’ll cover ground sensing in server applications. Vibration analysis in turbines and windmills. Error vector magnitude for QAM modulation. Accurately measuring sleep state currents in CPUs and GPUs.

What’s the toughest thing you’ve had to measure? What’s your favorite data converter and why? I welcome your feedback on your experiences working in the analog mixed signal domain.

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Apple’s Priority On Improved OLED Encapsulation For Foldable Smartphones Will Impact Applied Materials

Apple’s Priority On Improved OLED Encapsulation For Foldable Smartphones Will Impact Applied Materials
by Robert Castellano on 01-21-2021 at 6:00 am
Categories: Information Network, Semiconductor Services
4 Comments

Apple Ion beam t6

Smartphone shipments have been dropping over the past few years, as shown in Chart 1, as a result of several factors, but primarily the slowdown in smartphone innovation while at the same time prices have kept increasing. Even with the much anticipated 5G in 2020, unimpressive speed gains coupled with a Covid-19 backdrop, smartphones unit shipments may drop another 4% in 2020.

Chart 1

Smartphone manufacturers continue to add features to smartphones, such as multiple cameras or more memory, even though these have not been able to incentivize subscribers to shorten upgrade cycles. One feature that smartphone manufacturers have changed is the type of display, migrating from LCDs to rigid OLED displays to Flexible OLED displays to Foldable OLED displays.

Table 1 illustrates this transition in display type. While global smartphone shipments will exhibit a CAGR (Compound Annual Growth Rate) of -0.4% between 2017 and 2022, LCD display shipments will exhibit a CAGR of -6.7% while OLED displays will exhibit a CAGR of 11.9%.

In addition, within the OLED display sector, rigid OLED displays will exhibit a CAGR of 0.2%, while flexible OLED displays will exhibit a CAGR of 26.9%, according to The Information Network’s report entitled “OLED and LCD Markets: Technology, Directions and Market Analysis.”

I expect stronger growth in flexible OLED displays in 2021 coming from Apple (AAPL), which in 2020 its iPhone 12 models all have flexible OLEDs, as sales of these models, which shipped late in 2020 will continue in 2021, along with iPhone 13 models.

Foldable smartphones will grow from just 500,000 units in 2019 to 19.9 million in 2022. A total of 2.8 million foldable smartphones were sold in 2020, as Samsung’s Galaxy Z Flip smartphone Galaxy Z Fold 2 accounted for 73% of them.

Strong Growth in Flexible and Need for Encapsulation

A major problem with OLEDs is that the organic layers in the devices are extremely thin, and most of them are based on chemically active materials, which are easily damaged by exposure to moisture or oxygen in the air.

To prevent rapid device degradation, rigid OLEDs are encapsulated with a glass lid, which provides an acceptable level of WVTR (water vapor transmission rate). The brittle nature of glass, however, limits its application to rigid OLEDs, and the process is illustrated in Chart 2.

Chart 2

For flexible OLEDs, a glass seal is not suitable, and a thin-film encapsulation (TFE) is required that is flexible yet provides a robust hermetic seal. Chart 3 illustrates the utilization of TFE for a flexible OLED display. Since it uses a thin film instead of glass for encapsulation, the overall thickness of a display panel is also decreased.

Chart 3

I refer readers to a comprehensive analysis of OLED encapsulation in my May 24, 2016 Seeking Alpha article entitled “Applied Materials Stock Bounced On Display Orders – But Is It Sustainable?”

Since that article was written, the utilization of flexible OLEDs into smartphones has increased from less than 25% to more than 35% (Table 1). As a result, the structure and deposition processes for the TFE are increasingly being scrutinized. Microscopic pinholes or microcracks that may form during deposition of the TFE or when bending the device result in rapid device failure.

The increasing number of foldable smartphones adds another level of complexity in the design of the OLED and TFE due to the extreme strain and stresses placed on the OLED structure. Add to that the plethora of applications such as automotive, tablets, smart home, and TVs, and the number of TFE applications substantially increases.

Remember that foldable smartphones are made with modified flexible OLEDs. There are numerous OLED manufacturers with flexible OLED facilities located in Asia with a total capacity of 675,000 Gen 6 panels per month with a motherglass measuring 1500mm ×1850mm, as shown in Table 2.

To put things in perspective,

  • 212 iPhone 12 or comparable sized smartphones with a display measuring 146.7 x 71.5 mm can be cut from aGen 6 motherglass panel
  • A plant with a capacity of 15,000 motherglass panels per month can produce 38 million iPhone 12 smartphone or comparable sized displays per year.
  • The total capacity of 675,000 Gen 6 motherglass panels per month (Table 2) can produce 1.7 billion iPhone 12 or comparable sized smartphones per year.
  • 106 foldable smartphones with a display measuring 146.7 x 143 mm can be cut from a Gen 6 motherglass panel

This total capacity of 1.7 billion flexible smartphone displays is 7X the 246 million flexible smartphones made in 2020 (Table 1), in which 212 iPhone 12 display panels can be cut from each motherglass or 106 foldable smartphones can be cut. If a 10-inch tablet is demanded, just 78 panels can be cut.

Problem in Apple’s OLED Supply Chain

Apple has accelerated its innovative drive in its products in the past year or so:

  • It moved to OLED displays for all its new model smartphones in 2020 versus top of the line only models in previous years.
  • Apple moved from a CISC to an ARM architecture (named M1) as the CPU for its Mac laptops in 2020.
  • Apple is looking to release an iPad with a mini-LED display in H1 2021. Now we hear that Cupertino is also planning an OLED iPad Pro release sometime in the second half of 2021 with panels procured from Samsung and LG Display.
  • Apple has been known to be working on foldable display technology for some time, filing multiple patents regarding the technology. Samsung is rumored to be providing foldable display samples to Apple for a future foldable iPhone back in September 2020. Samsung is reportedly providing Apple with samples for one year, suggesting that Apple is ramping up work on a foldable iPhone.

But based on my sources, Apple is finding problems with encapsulation technology from Samsung Display (OTC:SSNLF) and BOE Technology, both display suppliers to Apple.

First, Samsung’s TFE processing is undergoing some upheavals:

  • Samsung Display has been preparing to separate TFE equipment suppliers in its supply network. Samsung Display is currently only using Applied Materials’ (AMAT) CVD systems for its Gen 6 OLED production lines. However, it had been looking for a change for its Gen 6 QD display. Wonik IPS, which is one of Samsung Display’s key partners, had participated in R&D process of QD Display and had hoped on developing a system that can replace Applied Materials’ systems. Samsung changed its mind and stayed with AMAT.
  • My sources in Korea tell me that Samsung is concerned because the takt time (rate at which you need to complete a product to meet customer demand) to put the glass through AMAT PECVD and Korean ALD (atomic layer deposition) is too long.

Second, there are problems at Chinese display supplier BOE Technology. According to a November 19, 2020 article in MacRumors,

  • Chinese display maker BOE has reportedly failed yet again to secure a supply order from Apple for OLED panels for iPhones. BOE is still facing manufacturing issues at its Chengdu plant in Sichuan province, meaning the display maker has failed to secure Apple’s validation for the OLED screens for the second time this year.
  • BOE’s plant in Mianyang – in the same province – suffered the same fate in June 2020, due to a low production yield rate of around 20 percent.
  • BOE failed to pass Apple’s quality tests and did not become a supplier to the iPhone 12 series (BOE also failed to pass Samsung Electronics’s display quality test).

According to a new report from Korea, Apple has tested BOE’s AMOLEDs for next year’s iPhones, but again BOE’s OLED production quality is not good enough for Apple, which means that in 2021 Samsung Display and LG Display will remain the exclusive OLED suppliers to Apple’s phones.

But then we learned in late https://www.gizchina.com/2020/12/24/finally-boe-has-passed-apples-certification-to-supply-iphone-12-oled-this-month/, that recent reports out of China claim that BOE has finally passed Apple’s certification and will start supplying OLED panels to iPhone 12 products in the near future.

Finally, Apple is advertising for job OLED encapsulation technologist positions:

Come work for the Apple’s OLED Encapsulation team comprising of amazing engineers who make the best OLED displays in the world including the Apple Watch and the iPhone. We make the world’s most reliable thin film encapsulation for OLEDs with worlds best electrical, optical and mechanical characteristics while achieving the small display bezels.

In this position, you will play a critical role in pushing the boundaries of OLED encapsulation for next generation of products. To do so, you’ll be working on core-technologies behind Thin Films deposited though Low temperature ALD, PECVD. With this core know how as a springboard, you will be creating next generation OLED displays with unique product design and the best optical and mechanical characteristics. You will be working on these technologies with Apple’s OLED display vendors across the globe to bring them from prototyping to mass production.

Depending on whether BOE is accepted as a supplier for the iPhone 12, the three suppliers are:

  • Samsung Display will produce the flexible OLED panels in its A3 fab in South Korea because it is equipped with the Y-OCTA technology.
  • LG Display will produce the flexible OLED panels in its E6 fab in South Korea
  • BOE will make the iPhone 12’s flexible OLED in its B7 and B11 fabs in China;

The 5.42-inch and 6.68-inch models are adopting the touch sensor panel on thin-film encapsulation (TSP on TFE), which Samsung Display refers to as Y-OCTA. Samsung Display will supply these two models. However, LG Display and BOE are not yet ready with the TSP-on-TFE technology. Therefore, the 6.06-inch, which LG Display is the main supplier of and possibly BOE, is equipped with the add-on touch panel.

Table 3 shows the four iPhone 12 models, and the display details and supplier.

TFE Process and Equipment

Table 4 shows a comparison between ALD, CVD and PVD deposition techniques

The PVD films exhibit relatively low film quality, with many defects and pinholes in the film, and the PECVD films can cause plasma damage and high process temperature issues. In contrast, ALD enables the thin film to be stably deposited at a low temperature in a vacuum chamber, and to be almost defect-free, but is 1000 times slower than the other processes.

Single-layer TFE has been attractive because it has a simple fabrication process compared to other encapsulation methods. But multilayer technologies address the aforementioned issues by inserting an interlayer. This can improve the WVTR by increasing the lag time. The flexibility can also be improved by the newly inserted layer. The inorganic layers (such as SiNx, SiOx, Al2O3) serve as the main barriers to block the moisture. Since defects such as pinholes and other particles unavoidably occur, organic layers (such as epoxy resin, phenolic resin, PET, PBT) effectively block the moisture infiltration paths.

Applied Materials, as mentioned above, is used for TFE for Samsung’s Gen 6 flexible OLEDs. It’s Enflexor Gen 6H PECVD deposits a range of buffer barrier films. AMAT’s TFE process is proprietary, but we can learn a bit from its patentfiled in July 2018. The encapsulant can include a first barrier layer, a buffer layer, and a second barrier layer.

The first barrier layer can include a dielectric film, such as SiN (silicon nitride). The buffer layer can be an organic layer, such as a hexamethyldisiloxane (HMDSO) layer. A second barrier layer comprising SiN is then deposited over the buffer layer.

AMAT’s Enflexor Gen 6H system is shown in Chart 4, showing the size and complexity of the cluster tool. This description of multiple layers using multiple process chambers explains the need for such a large and complex AMAT system, and can be explained in further details in the patent:

Chart 4

“A method of encapsulating an organic light emitting diode OLED device, comprising: generating a first plasma comprising silicon and nitrogen in a first process chamber; depositing a first portion of a first barrier layer comprising silicon and nitrogen over the OLED with the first plasma; generating a second plasma comprising silicon and nitrogen in a second process chamber; depositing a second portion of the first barrier layer comprising silicon and nitrogen over the first portion of the first barrier layer with the second plasma, wherein a density of the first plasma and the second plasma differ by a factor of at least 100; depositing a buffer layer over the first barrier layer in a third process chamber; and depositing a second barrier layer over the buffer layer in a fourth process chamber, wherein the first process chamber, the second process chamber, the third process chamber, and the fourth process chamber are arranged around a single transfer chamber.”

Using a unique technology for the display market, privately held Denton Vacuum (Cherry Hill, NJ) uses ion beam technology to deposit a Diamond-like nanocomposite organic layer sandwiched between two SiOxNy dielectric layers to form the encapsulant. But the equipment is priced at $3 million compared to an estimated $25 million for AMAT’s Enflexor.

To achieve a throughput of 1 Gen 6 motherglass panel per minute, the Phoenix In-Line PIB-CVD Deposition System is configured with 6 chambers with 2 linear sources in each chamber. Three chambers for each of two materials (inorganic and organic), PIB-CVD of Inorganic SiOxNy and Organic a-C:H DLN

  • Stress Control: 0 to 10MPa
  • Water Vapor Transmission Rate <1E-6 g/m2-day
  • Deposition Rate > 2500A/min
  • Good Adhesion
  • Deposition Temperature < 100C

Table 5 compares the commercially available techniques.

TFE Equipment Market for Flexible and Foldable Smartphones

Applied Materials is the market leader in TFE equipment, primarily because of its established history of deposition equipment in displays, starting with the 1993 formation of AKT (Applied Komatsu Technology) with Japan’s Komatsu, and the acquisition of the remaining 50% from Komatsu in 1999.

Table 6 presents an analysis of the total available market for competitor Denton Vacuum using its PIB-CVD Systems, which I chose based on price/performance of the systems. My analysis is based on a model for displays using Gen 6 Glass (1500mm x 1850mm), coating 212 6.1” flexible displays/motherboard and 106 foldable displays/motherboard at one time, and a throughput of 1 motherglass per minute for the deposition of the TFE. Based on an 80% yield and the system operating 24 hours per day, 365 days per year, system revenue per year is shown.

But based on my analysis, Apple’s scrutiny of Samsung’s encapsulation, which uses AMAT TFE equipment, and BOE Technology, which also uses AMAT TFE equipment, is a headwind for AMAT from two standpoints:

  • High-Priced Equipment, estimated at $25 million
  • Better Technology at significantly lower equipment price from competitors

If we compare the Yielded Total Available Market in Table 6 at $5 million and $8 million for Denton’s equipment in 2019 and 2020, AMAT registered, at 8X the selling price of the system) revenues of $40 million in 2019 and $64 million in 2020. Going forward, the revenue growth for Denton’s $3 million system would mean lost AMAT revenue multiplied by eight.

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Samtec Lets You Learn from Home with a Great Webinar Lineup

Samtec Lets You Learn from Home with a Great Webinar Lineup
by Mike Gianfagna on 01-20-2021 at 10:00 am
Categories: Events, Samtec, Semiconductor Services

Samtec Lets You Learn from Home with a Great Webinar Lineup

Work from home (WFH) has become a normal occurrence this past year. “Do you work from home?”  “Of course, where else?” Samtec is taking the whole work from home thing up a notch with a new webinar lineup for 2021. Back by popular demand, they are launching a new series of educational webinars. Started last year, the gEEk SpEEk Webinar Series brings a team of exceptional lecturers and signal integrity (SI) experts into your home (virtually) to discuss relevant and useful topics about system design and the associated signal integrity challenges. Enter the era of LFH (learn from home).  If you struggle with signal integrity challenges, you’ll definitely want to check this out. The links are listed below. So, let’s take a look at what’s in store from gEEk SpEEk to see how Samtec lets you learn from home with a great webinar lineup.

January 21, 2021, 11:15 AM PST: S and Z Parameters for PDN Measurements and Simulations. Presented by Istvan Novak, Principal SI-PI Engineer at Samtec. Learn about the techniques to model power distribution networks (PDNs). These systems are different than passive devices and channels, so the techniques you know may not apply.

February 18, 2021, 11:15 AM PST: Bending EM Simulation Tools to Your Will. Presented by Scott McMorrow, CTO, Signal Integrity Group at Samtec. Learn how to “trick” an electromagnetic modeling tool into providing the most accurate insight possible for a design.

March 18, 2021, 11:15 AM PST: Mechanics of Using the Public COM Code. Presented by Richard Mellitz, Distinguished Engineer at Samtec. The channel operating margin (COM) is an electrical figure of merit for a channel derived from measurement of its scattering parameters and a table of configuration parameters. Learn how to use the Matlab® script on this data to get the information you need for your design.

April 15, 2021, 11:15 AM PST: Successful PCIe Interconnect Guidelines for 8, 16, and 32 GT/s. Presented by Steve Krooswyk, Signal Integrity Engineer at Samtec. Learn how to get the best implementation of a PCI Express channel at a given data rate. Guidelines for length and loss, the penalty from trace separation and via stubs, connectors and cables, and interpretation of channel simulation results are all discussed.

May 20, 2021, 11:15 AM PST: Causality Enforcement or No Causality Enforcement? That is the Question. Presented by Stefaan Sercu, Principal Signal Integrity Engineer at Samtec. The quality of time domain simulation results using Fourier transformations (e.g., COM simulations) depends on the quality of the S–parameter models used. Causality is shown to be an important parameter limiting the usefulness of a model. Causality problems can be classified as mathematical and physical in origin and this webinar explores what techniques to apply to get the best results.

June 17, 2021,11:15 AM PST: Advanced SI Fixture Design: Why it’s Important to your Program’s Success. Presented by Travis Ellis, Problem Solver at Samtec. At advanced speeds (e.g., 112G) complex 3D simulations are required and these models must be correlated to measured data. The test fixtures used in this process must be transparent and deliver high fidelity information. This webinar explores how to achieve these goals. See a prior post to learn more about achieving 112G speeds.

July 15, 2021, 11:15 AM PST: Common Mode Conundrums. Presented by Richard Mellitz. Details on this webinar TBA.

August 19, 2021, 11:15 AM PST: How to Read the ESR Curve of Capacitors. Presented by Istvan Novak. Details on this webinar TBA.

September 16, 2021, 11:15 AM PST: Advanced High Density Breakout Design & Cross Talk Mitigation Strategies. Presented by Travis Ellis. Today’s high density connector arrays face significant challenges at the board attach region. Insertion loss and return loss impairments can be mitigated with careful design and simulation. This webinar explores the physical effects at work here and how to address them to achieve a successful design.

All prior gEEk spEEk webinars are also available for viewing here. Check out this great lineup of webinars and speakers today. Get on the LFH bandwagon because Samtec lets you learn from home with a great webinar lineup.

 

 

 

 

 

 

 

 

 

 

 

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2020 Retrospective. Innovation in Verification

2020 Retrospective. Innovation in Verification
by Bernard Murphy on 01-20-2021 at 6:00 am
Categories: AI, Cadence, EDA

innovation min

Paul Cunningham (GM, Verification at Cadence), Jim Hogan and I launched our series on Innovation in Verification at the beginning of last year. We wanted to explore basic innovations and new directions researchers are taking for hardware and system verification. Even we were surprised to find how rich a seam we had tapped. We plan to continue the series, first starting with a retrospective on what we found last year and how that might direct our discovery this year.

The 2020 Picks

These are the blogs in order, January to December. All did well in views but the first one and the last two really blew the roof off. We’d be curious to know which were your favorites.

Optimizing Random Test Constraints Using ML

Learning to Produce Direct Tests for Security Verification using Constrained Process Discovery

End-to-End Concolic Testing for Hardware/Software Co-Validation

Metamorphic Relations for Detection of Performance Anomalies

Is Mutation Testing Worth the Effort?

Predicting Bugs. ML and Static Team Up

Using AI to Locate a Fault

Quick Error Detection

Bug Trace Minimization

Covering Configurable Systems

ML Plus Formal for Analog

More on Bug Localization

Paul’s view

It has been such fun reading all these papers and discussing them with Jim and Bernard. I have been so impressed by the quality of work from the various authors and it is wonderful to see that innovation in verification is truly thriving. A very big thank you to all the universities and governments that are sponsoring and funding this research!

Probably the biggest theme that shone through from our cogitations last year is fault localization – helping engineers quickly and efficiently work out why tests fail and where the bugs are in their designs. There are a lot of ideas that are gaining traction in the software verification world that have not yet fully permeated to hardware verification. Also, it’s clear that ML is a key enabler behind this wave of innovation in fault localization.

Another theme which stands out is how great results nearly always come from combining multiple techniques together – simulation with formal, mutation with static, ML with deductive.  As a computer scientist and lover of algorithms, this has made for wonderfully enjoyable reading throughout the year.

A very happy new year to all our readers.

Jim’s view

First, I have to agree that there are a lot of creative people out there, imagining new ways to improve verification. Some are immediately interesting. Factors that always attract me here are:

  • Innovations directed at big market transitions. In semiconductor we think of new process nodes, but it could equally be in OpenRAN for 5G, car electrification, improvements to public health infrastructure, big return AI applications – you get the idea.
  • I’m not looking for incremental advances. I want disruptive ideas, unique, enough IP to be patentable, to preserve an advantage for ~5 years until the product is established in its market.
  • It’s important to realize that most investors these days are pretty seasoned, even a little cynical. They know what big ideas look like. Anything else will be a really tough sell.

I see metamorphic testing in this class, bug prediction using ML, and using AI or other methods to localize faults. I see ML/AI as an extension of statistics. A way of improving and speeding up our guessing. Potential applications here have been barely touched. I’m always a fan for anything to do with analog, a a market underserved by automation. I’d want to get my experts to do more due diligence on that paper, but it is immediately intriguing.

I’m not suggesting the other topics are unworthy. Among the other papers are several advances which could be very valuable incremental enhancements to existing verification flows. Perhaps these could be self-funded startups to prove a prototype then slip straight into acquisition?

My view

As the screener of candidate papers for our little group, you might be interested in my methods for selection. I bias to fundamental research which tends to be posted in a great variety of national and international conferences, best consolidated through platforms like the ACM and IEEE digital libraries. The ACM library provided more help initially because the IEEE didn’t yet support personal accounts for the library – now they do.

I still like to look in both libraries, because they provide a lot of complementary coverage. Also we have a lot to learn from our software brothers and sisters. Beyond that, I’m looking for anything topical and relevant to verification. I like to look at fairly recent papers, though Paul (rightly) prods me now and again to look towards the start the millennium. Sometimes I find hidden gems! We’re all eager to get feedback. If you think we should look harder at some problem or research area, please let us know!

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The Spartan flow for custom silicon: when losing is NOT an option.

The Spartan flow for custom silicon: when losing is NOT an option.
by Raul Perez on 01-19-2021 at 10:00 am
Categories: Custom Silicon, Semiconductor Services

iStock 1204288358

Every so often a custom silicon socket comes up at a system company that you simply cannot afford to lose if you’re a silicon supplier. These are the types of custom silicon sockets that last for generations of a product, in huge and predictable volumes, and for whatever reason they may become available. It’s not easy to predict when a strategic change by a system company will force this to happen, or when your silicon supplier competitor simply screws up. But when it does happen you have to throw every possible tactic and strategy so you earn that spot.

There is no single “spartan flow” because there is no single type of silicon product. There is also no single type of system product. So what I want to do in this article is not to prescribe an exact formula for what a spartan flow is, but to communicate a mentality of how to create a spartan flow for your engagement.

The ancient Spartans were famous for having laws in their society configured to maximize military proficiency at all costs, focusing all social institutions on military training and physical development. The Spartans were willing to make the sacrifices needed to excel in battle, and break the will of their opponent. Just thinking about going against them was a burden on the minds of their enemies.

While there is no single spartan flow, there are areas of focus to any spartan flow plan.

These are the following:

  • Communication.

You need to establish effective lines of communication ASAP. It is critical that from day zero the silicon supplier develops the best communication systems possible between its own teams. Also communication needs to be strong with the system company. This enables the teams to focus on quick and effective action and reaction. The classic sales force engagement with the customer communicating through the sales channel with an FAE is usually nowhere near enough if you want to win like a Spartan. You need to go all the way possible, and provide a ticket system hosted by you, or suggest the system company starts their ticket system component early if they are willing to do it. The latter is more common since the system company usually wants to retain records of the tickets in their servers. You need to identify as soon as possible who are the stakeholders on the system company side that are critical to design in your silicon product, and you need to get them in touch with your stakeholders/engineers. This usually means who is the EE, the SW engineer, the FW engineer, etc… who needs to be in close collaboration with your engineers. Then make sure there is a ticket system, collaboration tools setup (like Google docs and Google sheets, etc…) for both teams to collaborate easily. You want their system engineers to get to know your engineers, and invest time with them working on issues and ideas.

  • Pre-silicon engagement.

The silicon supplier needs to find ways to help the system company engineers integrate their silicon product into the system as soon as possible. Right away the silicon supplier needs to engage the system company to come up with a plan of what types of deliverables the system company engineers would like to receive to get system development started even while the silicon is being designed. You need to enable the software and firmware engineers to start writing and debugging code so when your silicon shows up they have made good progress towards getting a good image they can use for a build. The silicon supplier needs to evaluate if building an FPGA board with analog peripherals would be beneficial for this opportunity. Propose delivering development boards, manually built prototype parts, etc… Bottom-line is this; get them working on your solution and investing time in it early.

  • Ensure to have a process to manage the custom silicon engagement.

CustomSilicon.com implements a process, and manages both the system and silicon companies such that there is a really strong connection between all teams, the deliverables are clearly communicated, and the development phases are signed off by all stakeholders. The intent is that there is cross functional and intra company alignment at every stage of the project. It is vital that this is implemented to avoid issues that could mean the silicon supplier loses the opportunity due to some miscommunication about a spec, or bug, etc…

  • Verification.

In most integration projects, you need to specialize the verification function into dedicated AMS and DV engineers that start writing models, test benches and tests as soon as the spec is started. Companies that try to re-use designers as they come off the design of their portions of the chip will not be able to beat a spartan flow company that has those functions specialized and working in parallel to the designers.

  • Quality of first samples, and timing.

The quality of first silicon samples is literally a matter of life or death. If two or more silicon suppliers are competing for a socket, there will be a strong preference to focus system company engineers on who delivers samples first. Then the next selector is who has the least amount of bugs or the least severe ones. If you submit silicon samples later than the other supplier, unless the other supplier has some major bugs in their silicon, you may have already lost the race. So you need to think about how you can deliver samples early and with good quality. This usually means you need to think about how to bring up your ATE quickly. One thing you could do is do a “functional only silicon” tape out; this is a tape out of the chip when it is functionally good but not meeting all specs, and then use this silicon to bring up your ATE earlier. Of course this means that your design team needs to be larger so that you can split the development at some point in time, and keep working on the fully spec compliant silicon tape out while the “functional only silicon” is being taped out. This also means that your mask set cost may double or at least you’ll usually need a full extra metal mask set. Other things to keep in mind are paralleling your verification (see previous point) to speed up the development process and increase your capability of catching bugs before silicon. You could try and develop ways to wafer probe without bumping to get data quicker and start debugging your silicon sooner, etc… You could also hold wafers at various stages of processing so you can quickly release new masks to fix bugs you find at the wafer probe and provide those samples quickly to replace previous versions. You can use OTP/MTP to develop clever ways to quickly spin new samples that fix issues. The types of tactics used are going to depend on the silicon product, but you get the idea, you need to shorten the design and test time while also increasing the quality of samples all at once.

  • Validation.

The quicker you can validate your silicon and find the bugs, the quicker you can start working on ECOs to fix them or on work arounds, and the quicker you can tape out to converge on final silicon. So automating bench testing, using ATE, developing FPGA test platforms, stress testing units with asynchronous combinations of inputs, validating samples from process corner wafers and testing those to check any weakness over process, etc… are all critical things to do to ensure you have the highest chance of success and don’t fall off the horse mid-race when some critical bug is found that is not present in your competitor’s silicon. Team specialization is key here to be able to have setups running regardless of the availability of the designers.

There are many ways to optimize your processes, and come up with a spartan flow. This is certainly not the type of development that would be usually economically desirable for standard opportunities. But when you get an opportunity to get into a huge volume system, and the revenue stream from that is likely to continue coming generation after generation, deploying this spartan flow mentality is certainly worth the money. However, it’s hard to switch teams from normal mentality to spartan mentality. So you probably need to create a team that will always work in spartan mode and find them opportunities to execute. It would be wise to perhaps rotate some or all of the people in the spartan team periodically so that others in your company can learn this spartan methodology without burning out.

About CustomSilicon.com by Digital Papaya Inc.

CustomSilicon.com is the leading consulting firm in the custom silicon strategy and project management space for AR/VR, automotive, mobile, server, crypto, sensors, security, medical, space and more.

Raul has 20 years of combined experience in the system electronics and silicon industries. He is currently responsible for major system company’s custom silicon and sensor projects with projects approaching 30 total chips. Raul was the directly responsible silicon manager for 18 chips ramped to mass production at Apple for iPhone and iPad, and 23 total chips ramped to mass production counting projects where he was an expert reviewer. Raul was directly responsible for the development of mobile processor System PMICs for the iPad2, New iPad, iPad mini, iPad 4 and iPhone 5s. Other silicon included, backlight/display power for iPhone 5 and iPhone 5s, lightning connector silicon and video buffers. He managed supplier teams across the Globe.

Our network of experts provide our clients with an A+ silicon management team from day one.

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Automotive SoCs Need Reset Domain Crossing Checks

Automotive SoCs Need Reset Domain Crossing Checks
by Tom Simon on 01-19-2021 at 6:00 am
Categories: Automotive, EDA, Siemens EDA

reset domain crossing verification

When the number of clock domain crossings (CDCs) in SoCs proliferated it readily became apparent that traditional verification methods were not well suited to ensuring that they were properly handled in the design. This led to the creation of new methods and tools to check for correct interfaces between domains. Now, in automotive designs a similar issue is arising. Due to functional safety requirements, such as ISO 26262, automotive ICs need to be able to recover from faults and failures while continuing operation. This has led to the use of reset domains, which can be reset selectively as necessary while the surrounding blocks or the top level continue operation.

There are a number of cases where Reset Domain Crossings (RDCs) can be problematic and lead to functional issues. Siemens EDA in conjunction with NXP has a white paper titled “Systematic Methodology to Solve Reset Challenges in Automotive SOCs” that focuses the topic of finding and fixing issues with RDCs. It’s worth mentioning that Siemens EDA is the new name for Mentor.

Reset domain crossing verification

The white paper starts out by describing the problem generally and discussing the prominent techniques used to ensure proper behavior. The first is reset sequencing, where the receiver’s flop is reset before the asynchronous reset in the transmitter’s domain. The second technique is to use isolation on the data or clock of the receiver’s flop prior to the occurrence of a reset in the transmitter’s domain. This can be done with a reset-gating signal that isolates either the data or clock.

Yet, the real challenge is to find where there are specific issues that can cause problems. The second part of the white paper covers several examples that cause reset domain crossing issues. Specifically, in automotive designs the authors cite some common real-world problems that can occur.

In many designs there are configuration registers that need to hold values during warm resets. The registers are loaded at power on reset (POR), but if a warm reset occurs simultaneously with POR, the values in the POR registers can become corrupted. Another case they mention is where a clock gating signal can glitch due to a reset on the controlling flop. If this happens to a flop in another reset domain that is active, it can cause failures. They also include several examples where there is combinational logic on the reset path. There are legitimate reasons for wanting this, but it complicates RDCs.

The authors outline a methodology that employs Siemens EDA’s Questa to formally, and exhaustively, verify RDCs. Designers identify the primary reset signals to help the tool better understand the reset structure of the design. Then the RDC tool generates a digital model of the reset structure, including locating local reset signals. Each reset is categorized according to its type. This model is elaborated with information such as reset polarity, reset source and output value of the sequential element upon reset.

This model allows structural checks that can reveal problems such as polarity usage mismatch or always asserted registers driving reset signals. Then there is a user aided step that involves grouping reset domains according to their asynchronous relationships and specifying information about reset sequencing.

The white paper closes with a summary of a case study. Here they explain how the tool classified each of the resets and identified inferred resets. Possible structural issues in RTL coding are identified at this point. Of the 90k RDCs the tool helped narrow down the list of potential issues to ~1.6% of those that needed a closer look. The outstanding issues were easily fixed using the methods presented in the white paper.

Questa RDC appears to offer a high value, low pain methodology for adding RDC checks to the verification process. Because it is built on the Questa platform it shares a common language front-end and uses the same formal based algorithms for its analysis. With the added reliability requirements of the automotive space, designers will probably be glad to have a tool like this to ensure that the now necessary reset domains are implemented properly. The full white paper is available for reading here.

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Siemens EDA is Applying Machine Learning to Back-End Wafer Processing Simulation

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Siemens EDA is Applying Machine Learning to Back-End Wafer Processing Simulation

Siemens EDA is Applying Machine Learning to Back-End Wafer Processing Simulation
by Mike Gianfagna on 01-18-2021 at 6:00 am
Categories: AI, EDA, Siemens EDA

Siemens EDA is Applying Machine Learning to Back End Wafer Processing Simulation

There’s a lot to unpack in the title of this post. First, Siemens EDA is the new name for Mentor, a Siemens Business. The organization continues to operate as part of Siemens Digital Industries Software.  The organization has released a white paper that describes research done with the American University of Armenia. The work examines how to use machine learning (ML) modeling techniques to predict wafer surface topography after a back-end-of-line metal deposition step. It’s critical to get these predictions right so chemical mechanical polishing (CMP) can do its job effectively. Read on to see how Siemens EDA is applying machine learning to back-end wafer processing simulation.

Smoothing Out the Bumps

This is a story about smoothing out the bumps in wafer processing. Many of the process steps in chip manufacturing need a smooth surface on the wafer to ensure patterns are printed correctly during photolithography. These patterns form the devices for the chip and they’re very sensitive to distortion that can be caused by a non-planar (bumpy) surface. I’ll get into where these bumps come from in a moment. The method to smooth the surface is accomplished by the previously mentioned CMP step, which is quite complex.

During CMP, a polishing pad is pressed against a rotating wafer and a mixture containing abrasive particles and chemicals is injected between the pad and the wafer. Mechanical and chemical interactions occur at the wafer pad contact area, removing material from the wafer surface to smooth out the bumps. If you’re thinking this sounds like polishing your car, it’s a whole lot more complex than that. The pressure applied by the pad and the makeup of the chemicals injected all influence the quality of the result. Material is being manipulated at a microscopic level across the wafer surface to achieve maximum planarity (i.e., smoothness).

Back to the bumps. Where do they come from? This part of the story is about metallization, that is, creating the interconnect for the chip. Copper is deposited on the wafer surface using an electrochemical deposition process (ECD). This is another highly complex process that uses a variety of chemicals to minimize bumps, based on the underlying surface that the metallization is being deposited on. While these approaches can help, bumps happen, and the CMP step is required. The figure below illustrates a typical profile after ECD and before CMP.

Schematic plot of post ECD surface profile

For all this to work, an accurate prediction (through simulation) of the post-ECD surface is needed to drive the simulation that is used to set up the CMP process. During the first part, i.e., the simulation of the post-ECD surface, machine learning finds useful application.

How Machine Learning Helps

To model and simulate the ECD process, the design is first divided into fixed-size tiles. For each tile, average values of geometrical characteristics like width, space, pattern density, and perimeter are extracted. A series of complex mathematical models is then applied to each tile. After the analysis completes, the surface profile data for each tile are used as input for the CMP model. This is a long and complex process, and this is where neural networks from the field of machine learning find application.

A fully connected neural network-based full-chip deposition model for predicting the post- deposition surface profile is described in the white paper. Multiple ML algorithms are used to address the complicated surface variation that is typically seen. A key part of ML is applying large data sets of known results to “train” the neural networks. The white paper describes a series of experiments using Calibre® CMP ModelBuilder and CMPAnalyzer tools. First, physics-based models using data collected at the factories are created. These physics-based models are then used to generate the training, validation, and test data for ML model building.

The white paper then describes the application of various methods to find the best combination of run time and accuracy. The best methods exhibited a much shorter training time (a couple of hours) compared to other methods (several hours or several days). The ultimate results showed improved accuracy with lower run times compared to more traditional approaches. The post-ECD surface is also influenced by shapes that are not close by and ML approaches helped to model these longer-range effects as well.

ML is clearly finding its way into many applications. This is another example. You can access the full white paper, entitled MODELING ECD WITH MACHINE LEARNING FOR CMP SIMULATION here. Check it out to see how Siemens EDA is applying machine learning to back-end wafer processing simulation.

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Uber v Alto Ride Hail Streetfight

Uber v Alto Ride Hail Streetfight
by Roger C. Lanctot on 01-17-2021 at 10:00 am
Categories: Automotive
2 Comments

Uber v. Alto Ride Hail Streetfight

Uber, Lyft, Postmates, Instacart and Doordash were successful in their nearly $200M effort to pass California’s Proposition 22 in November – to allow gig operators to avoid treating their drivers as full-time employees with all of the associated employee benefits and legal protections. In the midst of a devastating pandemic that has placed a premium on safety and driven away both passengers and driver/contractors, a new threat to these operators is arriving in the shape of Alto to contest the juicy L.A. market opportunity.

Uber and Lyft have taken on ride hailing competition before, but Alto is an entirely new kind of rival offering a reasonably priced, premium level of service enabled by an employee-based platform using company-owned and outfitted vehicles with partitions. All of Alto’s vehicles are five-star crash rated SUVs piloted by a team of vetted and trained uniformed drivers.

While Uber and Lyft have hemorrhaged both drivers and passengers – to the tune of more than a third of their revenue – during the COVID-19 pandemic, Alto is pursuing its slightly delayed plans to expand to Los Angeles, California, and Austin and Houston, Texas. The key for Alto is its intense commitment to quality control and safety – something that makes a difference during a pandemic that has devastated the ad hoc transportation sector including everything from ride hailing to rental cars.

Uber and Lyft have both groped for a solution to the revenue crisis by leveraging micromobility and delivery services – but both have either resisted a shift toward deploying partitions in their vehicles or have made only half-hearted efforts to do so. Lyft, at least, has made partitions available – but has not required them.  Uber has done nothing.

To its credit, Alto recognized from the beginning that the fundamental value proposition of ride hailing was delivering a luxury service. As such, during a pandemic, it was no longer sufficient to offer convenience and an inexpensive ride. True luxury during COVID time requires a powerful statement regarding driver and passenger safety.

Uber and Lyft both require masks for drivers and passengers. But we all know, by now, that enforcing mask wearing on passengers is a dicey and difficult proposition for drivers. And masks alone in the confined space of an automobile cabin is insufficient protection.

Alto has removed this concern by installing partitions in all of its cars. This is also easier to do for Alto because it acquires and owns all its cars and can therefore deliver a predictable, reliable, guaranteed quality of service. With Uber and Lyft both the driver and the passenger get no such guarantees – particularly as regards safety. (We all know that ride hailing with Uber and Lyft, to quote Forrest Gump, is like a box of chocolates – “you never know what you’re going to get.”)

Alto says each driver is a “W2-employee and undergoes an extensive background check in addition to a thorough safety and defensive driving training program. Drivers are empowered with the tools needed for a successful ride every time, with technical support embedded into Alto’s dashboard including destination confirmation, navigation preferences and more. Riders can feel confident knowing that any time they request an Alto, it will be the same experience down to the vehicle model, amenities, and even the scent.”

Alto says its drivers are available for “corporate or personal courier service, customer or employee courtesy rides, and food pickup and delivery. Alto’s uniformed employee drivers are available to shop, purchase, and deliver a variety of needs from anywhere.”

Alto’s L.A. market entry press release states:  “In addition to the daily cleaning and maintenance procedures, each vehicle’s high-touch surfaces such as the interior and exterior door handles and headrests are disinfected between every trip. To ensure maximum safety for its drivers and riders in the midst of COVID-19, Alto has double-downed on its safety efforts by equipping each vehicle with custom plexiglass barriers between the driver and passenger compartments while also installing HEPA cabin air filters that remove 99.9% of airborne particles.”

Alto is not alone in adopting in-vehicle partitions. Bolt, DiDi Chuxing, Yandex, and Cabify have either fully or partially equipped their fleets with partitions.

With operations in Spain, Portugal, and Latin America, Cabify has taken some unique pandemic-related measures including installing partitions in 7,000 of its vehicles in Columbia and administering COVID-19 tests to some drivers. Cabify has reported increases in business during the pandemic, which may in part be due to its safety measures.

Cabify says it has been able to support safe mobility with more than 38,000 taxis in Columbia that have been operating since the beginning of the quarantine, complying with all government safety protocols.

The company noted in a report that most of the new users of its service are people who previously used mass public transport (40%), their private car (15%) or took taxi services on the street (15%). A company spokesman said: “During the pandemic, 60% of new users said that the reason they used the app was due to the good availability of vehicles and the high safety standards. The three main reasons why they needed to mobilize were: work 50%, health 10% and family visits 9%.”

Partitions are seeing wider adoption throughout the transportation sector including new partitions in public busses throughout the world. It’s worth noting that partitions are likely to become a permanent aspect of public, shared, and semi-private transportation services.

While most ride hail operators have added partitions without waiting for regulations, it is possible that regulatory pressure may grow for requiring partitions for taxis and other ad hoc transportation service providers. The next step is likely to include regular driver testing – though funding and reporting will have to be addressed.

It will be interesting to see how Uber responds to competitors adopting superior pandemic-related safety and sanitation measures like Alto in L.A. and Cabify in Latin America.  Alto is a particularly serious threat, though, in offering both a safer operating proposition for drivers and passengers – while also offering full employment and benefits. There is no doubt that hundreds of former Uber and Lyft drivers in L.A. will be lining up to join the Alto platform.

Alto is currently recruiting driver employees in L.A. and making the necessary arrangements to serve area airports.  Alto’s value proposition for both drivers and passengers is tailor-made to capitalize on the negative industry impacts from COVID-19.  L.A. is about to see a ride hailing street fight capable of restoring broader consumer confidence in the ride hailing sector. If the terms of engagement are safety, Alto will win hands down – and partitions up.