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Semiconductor Expert Forum

Podcast EP15: The Birth of Dynamically Reconfigurable Computing

Podcast EP15: The Birth of Dynamically Reconfigurable Computing
by Daniel Nenni on 04-09-2021 at 10:00 am
2 Comments

Dan and Mike are joined by Geoff Tate, founding CEO of Flex Logix. Geoff has a storied career in semiconductors that includes over ten years at AMD, ending as senior VP, microprocessors and logic. Following AMD, Geoff was founding CEO of Rambus, growing the company from four people to IPO with a $2 billion market cap.

As co-founder and CEO of Flex Logix, Geoff is leading the creation of a new category, dynamically reconfigurable computing. Geoff explains what the impact of this new category is today and in the future. He touches on inference applications as well as others and details what unique technology requirements are needed to make dynamically reconfigurable computing a reality.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

Flex Logix

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CEO Interview: Kush Gulati of Omni Design Technologies

CEO Interview: Kush Gulati of Omni Design Technologies
by Daniel Nenni on 04-09-2021 at 6:00 am
Categories: 5G, CEO Interviews, FinFET, IoT, IP, Omni Design

Kush Gulati

Kush Gulati is the CEO of Omni Design Technologies, a company he co-founded in 2015 to lead a transformation in how high-performance analog IP is developed and integrated into SoCs in advanced process nodes. With a PhD from MIT, he is a renowned expert in data converters, and a serial entrepreneur. His first startup was a detective agency he started when he was in middle school — Omni Design is his fifth business. Kush’s previous startup – Cambridge Analog Technologies – was acquired by Maxim Integrated in 2011 and, after a few years leading the Advanced IP Solutions group at Maxim, he founded Omni Design in 2015. Speaking to Kush, I am immediately struck by his innovative thought process, clear vision of the future of the semiconductor industry and for how Omni Design is enabling highly differentiated SoCs across a wide range of emerging applications, including 5G, wireline and optical communications, automotive/ADAS, AI, and IoT.

Please tell us about Omni Design?

Omni Design was founded to meet an industry need. The world we live in is analog, and virtually all the data processing is digital. So… you need to translate the analog data into digital, process it, and then transform it back to analog to operate in the real world. Technologies such as 5G, autonomous vehicles, optical computing, and image processing are driving exponential growth in the requirements to receive and transmit data at ever-increasing speeds and dynamic range using ever lower energy.

Traditional suppliers of analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) have been selling discrete devices that are incorporated onto a printed circuit board with the rest of the systems. As systems have become both more integrated and more powerful, there is a tremendous and growing industry demand for these ADCs and DACs in the form of embedded IP cores.

Omni Design is helping meet this demand by offering a portfolio of ADCs and DACs at various resolutions (from 6-bits to 14-bits) and sampling rates (5 Mega samples per second to 20+ Giga samples per second) in 28nm and advanced FinFET process technologies.

Omni Design has a tremendously creative team – this is at the very heart of our ability to build complex circuitry that expands the state of the art while simultaneously achieving a very high rate of first silicon success.

What makes Omni Design unique?

First of all, Omni Design has invented techniques that not only improve the power efficiency and the performance of data converters and analog circuits but also those that enable analog designs that are extremely compatible with FinFET design. This makes our products easier to integrate with digital circuits in advanced FinFET processes which is of course key to enabling complex SoCs for applications such as 5G and LiDAR.

Second, we take a systems approach to analog design – focusing not only on the specific IP we are developing, but also on how it will fit into the customer’s overall system specification. Our optimization process enables customers to get the maximum value from the IP we deliver to them. In LiDAR applications, for example, we focus not just on one block of the signal chain, but the entire solution from the optical sensor interface to the digital interface.

Third, we are developing our analog IP using a platform-based approach. From each of these platforms we can deliver data converters that are closer in spec to the customers’ requirements without needing to develop them as custom IP from ground up. The benefit to the customer, of course, is that once the architecture of one of our platforms is silicon validated, the derivatives of that platform can be deployed quickly and with high confidence in their products — without requiring additional test chips and silicon measurements.

What keeps system designers up at night?

The real-world demands of emerging technologies such as self-driving cars, 5G, IoT, etc. are clearly pushing the envelope when it comes to analog design and the integration of high-speed analog IP into an SoC.  Discrete components are simply not able to provide the required performance, especially at a cost and with the power efficiency necessary to move these technologies into the mainstream.  Consequently, these system designers must look for novel techniques to integrate complex analog functionality into their SoCs to get their next-generation products to market.

How can Omni Design help?

Omni Design works in close partnership with its customers to ensure that they get highly complex analog IP that, when incorporated into their SoCs, works the first time with performance that meets or exceeds the original design specifications.  We use our proprietary SWIFT™ technology, so customers can be confident that the data converter IP will meet or exceed their power and performance requirements – at a competitive cost.

Which markets is Omni Design targeting?

Omni Design is focused on the leading edge of the market – delivering state-of-the-art analog IP in process nodes from 28nm to advanced FinFET nodes. Our customers are razor-focused on product differentiation in their end markets and come to us with challenging requirements in sampling rates, power, resolution, and many other specifications tied to the quality of the data converter operation. We work closely with them – as a consultative partner – to design the final data converters and analog front-end modules so that these customers can optimize their system and derive the maximum benefit from our IP.

Final thoughts on the semiconductor IP business?

We are in the midst of another major transformation of the semiconductor industry.  The move to the fabless model that dominated the 1990s was the first transformation.  The emergence of foundries eliminated the need for companies to pour huge amounts of capital into increasingly expensive manufacturing facilities.  Although that hurdle was eliminated, another gradually emerged as those foundries advanced to increasingly sophisticated process nodes.  In FinFET process nodes, the concept of a complex system on a chip has become a reality.  When tens of billions of transistors are available, it is possible to create extraordinarily powerful and differentiated solutions.  The design challenge, however, is daunting.  It would require hundreds of man-years to take advantage of those transistors using a full-custom design methodology.

This challenge will be solved by IP and design reuse.  Omni Design and other IP companies are creating complex building-block circuits that were once discrete chips but are now being integrated by skilled systems developers using sophisticated design tools to quickly and efficiently create highly capable SoCs.  By enabling the integration of high-performance, reusable analog IP in complex SoCs designed in FinFET processes, we will see the same sort of semiconductor industry explosion in innovation that occurred when the fabless model initially emerged.

Also Read:

Executive Interview: Casper van Oosten of Intermolecular, Inc.

CEO Interview: R.K. Patil of Vayavya Labs

CEO Interview: Dr. Shafy Eltoukhy of OpenFive 

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SPIE 2021 – Applied Materials – DRAM Scaling

SPIE 2021 – Applied Materials – DRAM Scaling
by Scotten Jones on 04-08-2021 at 10:00 am
Categories: Events, Semiconductor Services, TechInsights

Slide1

At the SPIE Advanced Lithography Conference in February 2021, Regina Freed of Applied Materials gave a paper: “Module-Level Material Engineering for Continued DRAM Scaling”. Applied Materials provided me with the presentation and was kind enough to set up an interview for me with Regina Freed.

I also spoke to Regina Freed last year after SPIE and wrote up her presentation on material enabled pattering available here. This work is an extension of that work specific to DRAM.

DRAM scaling is slowing, and new solutions are needed to continue to provide density improvements, see figure 1.

Figure 1. DRAM Nodes and Bit Density Trend.

 DRAM scaling presents multiple challenges:

  1. Patterning – how to create the increasingly dense patterns.
  2. Capacitors – evolving from a cylinder to a pillar structure, need to pattern high aspect ratios.
  3. Resistance/Capacitance – bit lines and word lines resistance/capacitance improvements are needed for access speed.
  4. Peripheral (Peri) Transistor – evolution from polysilicon gate with SiON oxide to High-K Metal Gate (HKMG).

Figure 2. DRAM Scaling Challenges.

This article will focus on 1. Patterning, and 2. Capacitors.

 Capacitor patterning has been recently done with cross self-aligned double patterning (XSADP) but is now evolving to even more complex cross self-aligned quadruple patterning (XSAQP). Another option has been spacer assisted patterning as disclosed by Samsung that can increase the hole density on a mask by 3x but needs an etch that equalizes the hole size. Recently EUV has entered use.

Authors note, Samsung is using EUV for one layer on 1z DRAM and expected using EUV for multiple layers for the 1α generation ramping now, SK Hynix is also expected to introduce EUV for their 1 α generation due this year.

There are several challenges when implementing EUV for DRAM:

  1. Local Critical Dimension Uniformity (LCDU) – variations change electrical performance and etch aspect ratio.
  2. Hole size – EUV is sensitive to hole size and has a narrow process window.
  3. Thin resist – EUV photoresist is very thin and needs to be hardened.

The use of a thin deposition can harden the resist and a thick deposition can be used to shrink Critical Dimensions (CD). Spatially selective deposition on the top of the pattern can improve Line Edge Roughness (LER)/Line Width Roughness (LWR), notable weaknesses in EUV patterning. See figure 3.

Figure 3. Photoresist Improvements Using Deposition.

 For active area scaling EUV has defect issues at large CDs, instead you can etch small holes and then use precision lateral etch to open the feature in one direction shrinking the tip-to-tip distance. This technique eliminates the CD versus yield trade-off and enables ovals with larger contact landing areas, see figure 4.

Figure 4. Precision Lateral Etch for Active Patterning.

 A major problem with EUV is narrow process windows for acceptable stochastic defects. Directional etching gives you an additional knob for process design, if the middle of your process windows has opens and bridge, you can shift towards the side of the window that has bridges and then remove the bridges with directional etch, see figure 5.

Figure 5. Directional Etch to Remove Stochastic Defects.

Today’s capacitor pitch limits are >40nm which is also the current EUV limits for capacitor patterning. In the future smaller pitches will be required and process variability needs to be improved by >30% to enable scaling, see figure 6.

Figure 6. Capacitor Scaling Limited by Variation.

Reduced hard mask thickness and improved etch uniformity are both needed to enable this.

Today amorphous silicon (a-Si) is used for a hard mask, in the future doped silicon can provide better selectivity enabling thinner hard masks but creates hard to remove by-products, see figure 7.

Figure 7. Improved Hard Mask for Capacitor Scaling.

The issue with doped silicon for hard masks is it requires a special etch, the next generation process uses a high temperature etch. Photoresist is used to pattern an oxide hard mask; the oxide hard mask is then used in a high temperature etcher to pattern the doped polysilicon hard mask and finally the doped polysilicon hard mask is used to etch the capacitor. A level-to-level pulsing etch switching between etching and deposition steps allows aggressive chemistry usage for high-speed etching of the capacitor, see figure 8.

Figure 8. Improved Performance and Productivity.

The process innovations described above are expected to enable continued scaling of the current DRAM architecture.

Beyond 3 to 5 years a new DRAM architecture will be needed.

One interesting option we touched on briefly is a 3D approach where the capacitor changes from a vertical structure to a stacked horizontal structure.

In conclusion, Applied Materials continues to provide innovative integrated solutions for key patterning challenges to enable continued scaling, in this case for DRAM.

Also Read:

Kioxia and Western Digital and the current Kioxia IPO/Sale rumors

Intel Node Names

ISS 2021 – Scotten W. Jones – Logic Leadership in the PPAC era

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Cadence Dynamic Duo Upgrade Debuts

Cadence Dynamic Duo Upgrade Debuts
by Bernard Murphy on 04-08-2021 at 6:00 am
Categories: Cadence, EDA

Dynamic Duo min

Cadence calls their hardware acceleration platforms, Palladium Z2 for fast pre-silicon hardware debug and Protium X2 for fast pre-silicon software validation, their Dynamic Duo. With good reason. Hardware acceleration is now fundamental to managing the complexity of verification and validation for large systems, hardware and software. What makes these platforms stand out in the market is raw capability (2X capacity, 1.5X performance over the earlier models) and also close interoperability. Hence, the Dynamic Duo. That interoperability proves to be very important in real-world applications.

Reinforcing the Strategy

The Cadence System & Verification Group strategy builds on the wider corporate strategy of excelling in computational software and enabling design excellence. The Cadence team meets this objective through a 3-layer solution. At the bottom, they lean on a wide range of compute hardware options, above that the fastest, most scalable verification engines they can build running on that hardware, and above that, a verification management tier to accelerate verification setup, debug and results gathering.

Palladium is their emulation engine, built on their own custom processor. The latest Palladium Z2 release is a redesign fabricated on a more advanced process. Protium X2 is also a redesign, built on the latest Xilinx UltraScale+ VU19P FPGA. Paul Cunningham, Sr. VP/GM of the System & Verification Group, tells me excelling in computational software means Cadence doesn’t compromise on individual engine throughput. For each verification objective, they’re using the best available hardware platform, which he sees as a parallel to the more general trend in fusion between hardware and software (such as we see in AI), using special purpose hardware to accelerate computation.

Interoperability

The Dynamic Duo name comes through the tight use-model correspondence between Palladium and Protium. There’s an important reason for that correspondence. Verifying or validating large systems, multi-billion gate SoCs together with software, maybe sitting in a larger in-circuit emulation (ICE) environment, can be quite iterative in practice. You want to regress a software stack on the hardware at fast as possible, so you run on Protium X2 (faster than Palladium in throughput). A hardware bug crops up. You switch over to Palladium Z2 for hardware debug (not quite as fast but better than Protium for hardware debug), find and fix the bug, then switch back to Protium to continue software regressions.

Making this switch back and forth as simple and as fast as possible can only be achieved through identical compile, identical testbench links, transactors, bridges, hardware, connectors. None of your carefully crafted setup has to change.

Optimizing ROI

Hardware acceleration platforms are more expensive than new copies of a software simulator, no surprise. You don’t want expensive hardware sitting idle during debug or chip projects because it can only run one job at a time. Both Palladium and Protium can operate as virtualizable resources in a data center. You can load up one giant job or many smaller jobs, which a dedicated hypervisor will pack as efficiently as possible onto the machine. Meaning you can run around-the clock SoC and sub-system verification jobs.

The rubber meets the road

All sounds good, who has signed up? AMD and NVIDIA have publicly endorsed both platforms and Arm has publicly endorsed Palladium Z2.

More generally on the mix between Palladium and Protium, Paul tells me that some customers use Protium almost exclusively. These design teams tend to be using a lot of pre-validated IP. Their verification leans to more emphasis on the software stack. Others are doing a lot of their own RTL design and require hardware debug access so lean more to Palladium. He added that a growing segment of Cadence’s hardware business last year came from customers buying a mix of both platforms. Reinforcing that customers are seeing significant value in the Dynamic Duo.

You can learn more HERE.

Also Read

Reducing Compile Time in Emulation. Innovation in Verification

Cadence Underlines Verification Throughput at DVCon

TECHTALK: Hierarchical PI Analysis of Large Designs with Voltus Solution

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Is E-Waste Declining ? The rest of the story

Is E-Waste Declining ? The rest of the story
by rahulrazdan on 04-07-2021 at 10:00 am
Categories: Semiconductor Services

Picture1

Recently,  there have been a number of articles with titles such as “Study shows residential electronic scrap generation is declining”  or “E-scrap generation on the decline, study finds.”  or “E-Waste Is Declining, Government Needs To Change Laws To Keep Up – And Get Out Of The Recycling Business.”    

As a veteran of the semiconductor industry, these articles are quite counterintuitive and surprising. 

How can e-waste be going down when electronics is seemingly becoming integrated into nearly every facet of the world?  

The basis of the story is a study “ The evolution of consumer electronic waste in the United States”  by Shanana Althaf, Callie W. Babbitt, and Roger Chen.  This study, sponsored by the Consumer Technology Association (CTA), conceptually has the following thought process:

  1. Sales: Track consumer sales of popular consumer devices such as phones, tablets, printers, desktops, displays, and more. Basically, the stuff you buy at stores such as Best Buy.
  2. Device Breakdown:  Break down each device into component parts.
  3.  Lifetime Analysis:  For each device, build a model of lifetime, and thus when the product is likely to enter the waste stream. 

Based on this model, the accumulated tonnage of waste product is generated and the very surprising result presented is that e-waste generated in US households peaked in 2015 and has been declining after this point. Is this decline “real?”   The correlation of the model with actual tonnage seen at retail electronics waste facilities was not discussed in the paper. 

However, the basic model and methodology seem reasonable.  According to the authors and the supporting data, the major underlying drivers of this reduction of e-waste were:

  1. Display Technology Shift:  A large amount of the reduction of e-waste was the shift from CRTs to Flat Panel Displays. Remember we are talking about weight/mass.
  2. System Device Integration:  Dominant consumer devices such as cell-phones and laptops absorbing function which were previously fulfilled by multiple devices (ex mapping devices).

Accepting the rationale and staying within the lane of the study (retail consumer devices), the natural conclusion would be that while e-waste is declining temporarily, it is likely to rise again.  Why?  The dominant consumer devices are still growing rapidly. As an example,  global cell phones grew 9.1% Year over Year last year. Further, the basic form factor for these fundamental devices is not changing dramatically. Cell phones have actually gotten bigger in the last few years.  At some point, the e-waste flows from CRTs and older single function electronics devices will be exhausted or be so small that it is no longer material.  

Interestingly, the bigger picture is that outside the lane of retail consumer devices,  electronics usage is rising rapidly in major consumer devices such as automobiles (moving to 40% of cost), home appliances, and cable boxes. Further, commercial infrastructure such as cloud, telecommunications(5G), and transportation infrastructure are consuming electronics at an accelerated pace.   

How does all of this net out ?   

The summation of all of this usage can be seen by the total semiconductor unit volume shipped (Figure Below) from World Semiconductor Trade Statistics Data. Overall,  the unit volume of semiconductors has been increasing at a 15+% compounded rate.  This is despite the fact that during this time Moore’s law has enabled the doubling of functionality several times over the decade.  

 

So.. what is the “rest of the story” ?

  1. Retail Consumer: Technology shifts such as display technology or system absorption into dominant platforms can indeed cause e-waste tonnage to decline temporarily.  However, as these major platforms proliferate more deeply worldwide, the growth of e-waste will likely follow.  If another dominant platform becomes viable, the situation may shift even more dramatically. 
  2. Non_Retail Consumer: Larger form-factor devices such as appliances, home energy systems (ex..solar), and especially automobiles have an increasing amount of electronics and the resulting e-waste must be handled gracefully.
  3. Centralized Infrastructure:  Services such as cloud, transportation control, and communications are all accelerating their use of electronics.  
  4. Distributed Infrastructure:  With Internet-of-things (IOT) technology, electronics is increasingly embedded in a distributed context in the environment.  Because of the large distributed embedded nature, gracefully handling e-waste will become an important factor.

Each of these streams have different characteristics for e-waste collection and disposal.   

Overall, electronics usage continues to accelerate and this acceleration adds an enormous amount of value to society.  However, the other side of this acceleration is a need to handle the e-waste gracefully.

 

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Webinar: Annapurna Labs and Altair Team up for Rapid Chip Design in the Cloud

Webinar: Annapurna Labs and Altair Team up for Rapid Chip Design in the Cloud
by Mike Gianfagna on 04-07-2021 at 6:00 am
Categories: Altair, EDA, Events

Annapurna Labs and Altair Team up for Rapid Chip Design in the Cloud
David Pellerin

This is a story of strategic recursion. Yes, a fancy term. I just made up. If you’re not into algorithm development you can Google recursion, but the simple explanation is we’re talking about using the cloud to design the cloud. The story begins with Annapurna Labs, a fabless chip company focused on bringing innovation to cloud infrastructure, now part of Amazon.  To more effectively utilize the vast resources of Amazon Web Services (AWS) to build their advanced designs, Annapurna Labs turned to Altair. Altair’s solutions made a substantial impact on these projects and the details of this successful collaboration is the subject of an upcoming webinar. Read on to learn how Annapurna Labs and Altair team up for rapid chip design in the cloud.

First, a little about the presenters. David Pellerin, head of worldwide business development for semiconductor at AWS presents the chip design side of the story. Dave has a long history in EDA, embedded software, chip design and cloud enablement. He is also an author, with several books on FPGA usage and design. Dave has the perfect background to tell the chip design side of this story.

Andrea Casotto

Presenting for Altair is Andrea Casotto, chief scientist, enterprise computing core development there. I’ve known Andrea for a long time. He’s well known to a lot of folks in Silicon Valley. Andrea led Runtime Design Automation for 22 years before being acquired by Altair almost four years ago. Before that he was a researcher at Siemens. Andrea holds a Ph.D. in electrical engineering from UC Berkeley. He has forgotten more about chip design methodology than most people know. He is the perfect person to tell the cloud enablement story. I wrote about a cloud enablement presentation from Andrea here.

Now to the story told during the webinar. There are two key items covered in this event:

  • An explanation of Altair Accelerator™ Rapid Scaling technology and how it delivers on the promise of efficient chip design on AWS.
  • A demonstration of how Rapid Scaling works in the Annapurna Labs chip design workflow and a discussion the business merits of this approach

The Annapurna Labs design team was managing workloads on a number of dedicated Amazon Elastic Compute Cloud (EC2) instances and they could occasionally scale up by manually adding new On-Demand instances. However, the process was not automated and led to high touch, forgotten unused compute resources, and either under-scaling or excessive scaling. When you’re dealing with essentially infinite compute resources, inefficiency can get out of hand quickly.  The team at Annapurna Labs is designing some very sophisticated technology including AWS Nitro, Inferentia custom machine learning chips, and AWS Graviton2 processors, based on the 64-bit Arm Neoverse architecture purpose-built cloud server.  With this kind of complexity, inefficiency can get very expensive.

By deploying a technology from Altair called Rapid Scaling, the efficiency of the design workflow at Annapurna Labs increased by a spectacular margin. You’ll need to attend the webinar to get the exact statistics and how the solution was implemented. A key part of the strategy is something called a license-first approach. The webinar shares details about how Altair’s technology was deployed and what the impact was on the Annapurna Labs design workflow. You’ll be impressed with the results.

The webinar will take place in two time zones, 11:00am CET and 2:00pm EST on April 28. You can choose your preferred time zone and register for the event here.  If you’re considering a move to the cloud and are concerned about how to manage costs, I strongly recommend you attend this webinar to see how Annapurna Labs and Altair team up for rapid chip design in the cloud.

Also Read

Altair Expands Its Technology Footprint with I/O Profiling from Ellexus

Altair HPC Virtual Summit 2020 – The Latest in Enterprise Computing

High-throughput Workloads Get a Boost from Altair

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Kioxia and Western Digital and the current Kioxia IPO/Sale rumors

Kioxia and Western Digital and the current Kioxia IPO/Sale rumors
by Scotten Jones on 04-06-2021 at 10:00 am
Categories: Semiconductor Services, TechInsights
8 Comments

Slide2

There are a lot of articles out right now discussing a possible IPO for Kioxia or sale of the company with Western Digital (WD) and Micron Technology (MT) mentioned as possible acquirers. Kioxia and WD have a partnership for Flash Memory and on March 18th WD gave a presentation on the state of their partnership and what they see as their competitive advantage. With all the recent discussion I though it would be useful to look at Kioxia, how they got to where they are, how the partnership with WD works and what their competitive position is.

Early Flash History

At the 1984 International Electron Devices Meeting, Masuoka, et.al., of Toshiba disclosed the idea of an electrically programable – non-volatile memory that could be rapidly erased in blocks (Flash is for flash erase). The architecture only required a single transistor per memory cell rather than 2 transistors per cell the way standard EEPROM did. This was the beginning of Flash memory technology.

Early Flash memory was weighted towards NOR Flash that was used primarily for code storage. In 1986 Intel invented ETOX Flash and even as late as 2000 Intel was the leading producer of Flash memory with NOR Flash although Intel eventually exited the Flash business before returning to make 3D NAND Flash with Micron.

Around 2005 NAND Flash passed NOR Flash in revenue finding applications in digital cameras, mp3 players, USB memory sticks and other data storage applications. By 2010 NAND Flash represented over 80% of Flash memory revenue and that percentage has continued to grow with increasing use for disk drives and in cell phones.

Up until the mid 2010’s 2D NAND Flash production grew rapidly and led the semiconductor industry with the smallest linewidths, for example 2D NAND was the first application to make use of Self Aligned Quadruple Pattering (SAQP). Eventually 2D NAND Flash cells became so small that a variety of issues drove the need for a new solution, see figure 1.

Figure 1. 2D NAND Scaling Issues.

During this time Toshiba became a leading producer of 2D NAND.

3D NAND

In 2007 at the VLSI Technology Symposium, Toshiba disclosed Bit Cost Scalable Technology (BiCS) for 3D NAND. The BiCS process that was disclosed created a memory stack by depositing alternating layers of silicon oxide and polysilicon and then etching down through the stack to form multiple memory cells in a vertical array. This was a gate first technology and is illustrated in figure 2.

Figure 2. Toshiba BiCS Process.

In 2009 at the VLSI Technology Symposium Samsung disclosed their Vertical Cell Array using TCAT (Terabit Cell Array Transistor) Technology for 3D NAND. TCAT memory array fabrication begins with alternating layers of silicon oxide and silicon nitride and then etching down through the stack to form multiple memory cells in a vertical array. The nitride is eventually removed and replaced with metal layers for the gate and word line (replacement gate).

The TCAT process is illustrated in figure 3.

Figure 3. Samsung TCAT Process.

The basic idea of 3D NAND is to turn the 2D NAND string on end into the vertical direction, see figure 4.

Figure 4. 3D NAND Structure.

The key differences between BiCS and TCAT are:

  1. A BiCS memory array stack is oxide and poly layers and TCAT memory stack is oxide and nitride layers.
  2. In a BICS memory array the poly is left in place and becomes the gates and word lines (gate first). In a TCAT memory array the nitride is removed and replaced with gate metals and tungsten for the gate and word line (replacement gate).

As 3D NAND was being developed there were rumors in the industry that Toshiba could not get BiCS to yield and in fact in around 2014/2015 when the first commercial parts began to filter out, construction analysis done by our strategic partner Tech Insights showed that Toshiba had essentially copied Samsung’s TCAT process. Interestingly Toshiba continued to refer to their process as BiCS even though BiCS and TCAT are fundamentally different processes. I suppose what Toshiba was doing was still “punch and plug” as discussed in the original BiCS paper but in my opinion the process Toshiba took to production is clearly not BiCS.

Kioxia/Western Digital

Due to large losses in their Westinghouse nuclear power division, Toshiba spun out their NAND Flash business into Toshiba Memory and eventually Toshiba Memory was further spun out to an investment consortium led by Bain Capital becoming Kioxia. The approximate ownership shares in Kioxia are Bain at 50%, Toshiba at 40% and Hoya at 10%.

Back when Kioxia was a Toshiba division, Toshiba and SanDisk formed a partnership for Flash memory. Eventually WD bought SanDisk, Toshiba Memory became Kioxia, and Kioxia and WD became partners in Flash memory in a joint venture known as Flash Ventures (FV). FV is owned ~50/50 by WD/Kioxia and the wafer output is split ~50/50.

As I understand the joint venture, Kioxia builds the fabs, Kioxia and WD share the capital expense of equipping the fabs and they share the fabs output with both companies selling Flash memory. In a recent note, Well Fargo noted that the joint venture currently extends to 2034+ presenting a complication to any attempt to acquire Kioxia. The Japanese government also played a role in Kioxia’s formation vetoing too much foreign ownership.

Western Digital Presentation

On March 18, 2021, Dr. Siva Sivaram of WD gave a Flash Technology Overview of the Kioxia/WD partnership. I thought it would be interesting to examine some of the statements that were made in the presentation.

WD and Kioxia have invested a combined $18 billion dollars in Flash R&D in the last ten years, they believe this is the largest investment specific to Flash in the industry. I do not have any data to compare this to.

WD and Kioxia claim >34% of worldwide NAND bits shipped versus 33% for Samsung making the combined entity the world’s largest producer of NAND Flash. I reached out to Bill McClean at IC Insight’s and he provided the NAND revenue breakout shown in figure 5, Samsung has slightly more revenue share than Kioxia/WD. It is entirely possible Kioxia/WD ship slightly more bits and Samsung has slightly higher revenue, overall, I would say that Kioxia/WD is neck and neck with Samsung.

Figure 5. Worldwide NAND Revenue by Company. Figure provided by IC Insight’s.

 And interesting note on this, Samsung has revenue of $18.2 billion dollars growing at 21%, Kioxia/WD have combined revenue of $17.6 billion dollars growing at 23% and SK Hynix/Intel has revenue of $11.8 billion dollars growing at 45% (SK Hynix is acquiring the Intel Flash business).

The Yokkaichi fab complex has seen $40 billion dollars in total investment and has over 550 thousand wafers per month capacity (kwpm) making it the second largest capacity fab complex in the world. The reported >550kwpm capacity was somewhat surprising to me, Kioxia has been shedding 2D NAND capacity and a few years ago that number would have made sense to me, but I thought their capacity was closer to 500kwpm in Yokkaichi (Kioxia has another Fab in Kitakami City, Iwate prefecture).

Figure 6 illustrates our estimates for 2D NAND and 3D NAND capacity by company and wafers run.

Figure 6. 2D and 3D NAND Wafer Capacity and Total NAND Wafers Run by Company for 2020.

From figure 6, Kioxia has the highest total NAND capacity but they appear to have more 2D NAND capacity than their competitors and their Fabs are the least utilized. We believe they are shedding 2D NAND capacity currently while also building new 3D NAND capacity. I should note, that getting good visibility on actual 2D versus 3D NAND capacity for Samsung and Kioxia is challenging, and these are best estimate numbers.

During the presentation, several times WD claimed that Kioxia/WD have the best 3D memory cell in the business, I am not sure how they determine this. The physical analysis I have seen from Tech Insights shows identical material sets for the memory cell from Kioxia and Samsung with the only difference being film thicknesses, see figure 7.

Figure 7. Kioxia Versus Samsung Memory Cell.

 The thicknesses differences could result in different performance or something about deposition and clean conditions could possibly give Kioxia an advantage in their cell, but it is not clear to me what it actually is or what they are measuring to claim leadership.

WD also claimed multibit leadership and they may have been first for 3 bits per cell – triple level cell (TLC) flash but I believe Intel-Micron was first to 4 bits per cell – quadruple level cell (QLC).

WD claimed that they scale laterally more than the other players and therefore have more bits with fewer layers saving cost. There are multiple elements that go into bit density:

  1. Within the memory array area, bits scale up with number of layers.
  2. Horizontal scaling can increase number of bits per unit area of memory array and could give an advantage in bits per unit area per layer.
  3. Whether CMOS is fabricated next to the memory array or partially under the memory array is a determining factor in what percentage of a die is memory array.

Figure 8. presents an analysis of several generations of 3D Flash parts for layers, bits per millimeter squared, and bit per millimeter squared per layer.

Figure 8. Memory Density.

 For each company, Kioxia, Micron (charge trap only), Samsung and SKH there are three columns. The first column is number of layers for the generation, the second column is the bit capacity of the die divided by the die area, the third column is the second column divided by the first column to get bits per millimeter squared per layer.

Black numbers are measured on production parts or conference disclosed numbers, red is our estimates based on layers scaling and forecast for CMOS on the side or under the array. Bold numbers are the leaders for each generation.

Another side note, in their ISSCC 2021 presentation, Kioxia presents 3.88Gb/mm2 for 64L versus our measured density of 3.40Gb/mm2. The ISSCC presentation is for a 512Gb part and the part Tech Insights measured is 256Gb. Similarly, at 96L the ISSCC value is 5.95Gb/mm2 for a 512Gb part and the part Tech Insights measured is once again a 256Gb part. Interestingly the presentation lists a 128L part with 7.8 Gb/mm2 when Kioxia went into production with a 112L part, and they also list 10.45Gb/mm2 for a 170L+ part when their production announcement is 162L. So, there is some disconnect between their presentation and production practices.

Our analysis has SK Hynix leading for bit density and bits per layer at 48 layers, SK Hynix leading for bit density at 64/72 layers but Samsung and Kioxia tied for the bits per layer lead. At 92/96 layers SK Hynix once again leads for both categories. At 112/128 layers we expect Micron to lead for bit density but Kioxia to have the best bits per layers and finally at 160/162/176 layer we expect Micron to lead in both categories. Of course, the Micron values at 112/128 layers and 162/176 are only as good as our forecast and we should note we have not seen any Micron charge trap part analysis yet, so these forecasts are scaled from Micron’s Floating Gate work with Intel. The bottom line is Kioxia appears to be competitive but not be a consistent leader.

The bottom line is who delivers the lowest bit cost, IC Knowledge is the world leader in cost modeling of semiconductor and MEMS. Using our Strategic Cost and Price Model – 2021 – revision 00a we have evaluated wafer cost and bit cost for three generations of 3D NAND by company. Figure 9 presents relative wafer cost, density, and bit cost.

Figure 9. Cost Leadership.

 In figure 9 we did not analyze beyond the 112L/128L generation because we are currently updating the model to the latest announced layer counts.

Samsung is the wafer cost leader at all layer counts, this is due to Samsung being the last company to string stack and the last company to put CMOS partially under the memory array. This results in lower wafer cost but eventually the density is not competitive, and Samsung loses out on cost per bit.

The bit cost leadership changes from Samsung at 64L/72L, to SK Hynix at 92L/96L, to Micron at 112L/128L. As mentioned on the figure Micron is the least certain part of the analysis and is subject to change once we see actual measured parts.

In terms of Kioxia, we do not see them the leader in any of the three factors at any layer count analyzed. The Kioxia bit cost is competitive for their 64L process and 112L processes but not at 96L.

In summary we believe Kioxia is a competitive 3D NAND player and particularly strong in bits per millimeter squared per layer, but we would question whether they have the level of leadership represented in the WD presentation.

IPO or Acquisition

This is outside of my specific expertise; it does seem to me that an acquisition by Micron would be difficult with the FV JV in place until 2034+. We estimate WD/SanDisk has invested over $18 billion dollars in equipment located in the Kioxia fabs, how that would be handled in an acquisition and the supply commitments, strikes us as problematic. WD would be the most obvious acquirer, WD did try to acquire Kioxia when they were spun out but lost out to the consortium led by Bain. In a Wells Fargo analysis note they have raised concerns about WD ability to handle an acquisition of the size of Kioxia with a $30 billion price tag mentioned. There may also be issues with the Japanese government blocking the sale of Kioxia to a non-Japanese entity. It seems to me that the most likely outcome is an IPO when the time is right.

Also Read:

Intel Node Names

ISS 2021 – Scotten W. Jones – Logic Leadership in the PPAC era

IEDM 2020 – Imec Plenary talk

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VC Formal SIG Virtually Conferences in Europe

VC Formal SIG Virtually Conferences in Europe
by Bernard Murphy on 04-06-2021 at 6:00 am
Categories: EDA, Synopsys

VC Formal graphic min

Pratik Mahajan, Synopsys VC Formal R&D Group Director, kicked off an absorbing event featuring talks from multiple customers in Europe. He spent some time on formal signoff, an important topic that I’m still not sure is fully understood. Answering the questions “OK, we did a bunch of formal checking but how does that affect total design signoff? And how does this complement dynamic signoff?” A lot of progress has been made here, in areas like formal core coverage, combining formal and dynamic coverage together and accelerating debug through ML-assisted bug triage. Also using formal to accelerate and strengthen low power and safety verification. Lots of meat in this VC Formal SIG.

Keynote on formal today in production verification

Mirella Negra Marcigaglia, Verification Manager at ST Micro Catania, gave the opening keynote on how formal fits into today’s verification challenges. She pushes formal first in development because it’s faster (no TB needed), simpler to use through apps, easier to reuse and of course exhaustive. It’s not perfect: we still need to wrestle with convergence challenges, size constraints, how comprehensive are our properties and whether anything is over-constrained. Mirella makes a very interesting point in her closing slide, that formal skills should be taught much more broadly across design groups. She’s responsible for both, yet in her view formal is easier to pick up than UVM, so should not be limited to a formal-only group. Times are changing.

Modern formal applied to the FDIV bug

In the ‘90s, the Intel FDIV bug catapulted formal from an academic curiosity to a commercial reality. Max Freiburghaus of Imagination Technology shows how this bug would have been caught by modern formal equivalence checking, here in VC Formal DPV (datapath verifier). He goes into detail on the SRT algorithm, showing how approximations inherent in the method can lead to hard-to-reach corner case bugs. And how DPV can find these. You’ll have to concentrate carefully to follow the argument, but worth the effort for a nice demonstration.

When is a bounded proof good enough?

Anthony Wood of GraphCore presented on this topic, which always trips us up. Answering this question isn’t trivial. Perhaps you should increase the proof depth. But that may not be the smart option. Some elements, like counters and memories are between hard and impossible to test exhaustively. And not worth the effort because the great majority of states differ insignificantly from others. You want to cover boundary conditions, unique combinations where bugs may lurk. Anthony talks about a few examples and how formal testbench analysis can help navigate the possibilities. He also throws in a couple of teasers on how formal can help in continuous integration and continuous delivery flows. Nice! Disruptive changes often create new opportunities.

Ultra-low power verification

Another popular topic. Karine Avagian, R&D Formal Verification Engineer and Joakim Urdahl, Sr. Engineer in Verification Methodologies, both at Nordic Semiconductor talked about their work in this area. Joakim has strong background in formal, however adoption in Nordic is relatively recent, so this section covers their first steps to a foundation for ULP checking. Emphasis is on complete property checking, defining properties to describe the complete input/output behavior of a block.

This is an interesting study of first steps into using serious property checking (as opposed to apps). They start with the spec for a block (a UART), define a conceptual state machine for the behavior, then write properties they expect to apply based on that description. Even though this was a learning exercise, they found bugs in the implementation and opportunities for further ultra-low power optimization. For a part that has been in production for quite a while. (Note to self – already in production for years doesn’t mean it’s bug-free.)

Formal versus simulation

Finally, Paul Stravers from the Synopsys Solutions Group presented on eliminating block level sims using formal signoff. This is an eternal quest in formal, their ‘impossible dream’. Which might attract derision, but I like this thinking. We wouldn’t get anywhere interesting without moonshots. Even if/when these projects fail to reach their hoped-for goal, they still make important new discoveries. More power to them. Incidentally, an HSCA is a cluster adapter, commonly used in Ethernet logic. Took me quite a while to figure this out.

You can register to watch the complete VC Formal SIG HERE.

Also Read:

Key Requirements for Effective SoC Verification Management

Techniques and Tools for Accelerating Low Power Design Simulations

A New ML Application, in Formal Regressions

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RISC-V is Building Momentum

RISC-V is Building Momentum
by Adrienne Downey on 04-05-2021 at 10:00 am
Categories: IP, RISC-V, Semico Research, Semiconductor Services

RISC V END MKTS

The semiconductor intellectual property (SIP) market is an integral part of the semiconductor industry. Third-party IP has propelled the industry, opening the door for many new products from start-ups to established IDMs. Enabling increasingly complex devices, reducing the cost of product development and reducing the time to market for both leading-edge and mature products are just a few of the benefits of third-party IP.

For the most part, third-party IP has used a business model that employed licensing and royalty fees. This payment arrangement has been successfully adopted by most market players and has matured with the IP market. Over time, we have seen a wide range of licensing and royalty fees depending on the supplier, the volume that is associated with the use of the IP and the complexity inherent to the IP itself. In general, IP users have been constrained by the rules and regulations of closed architectures, even though some of this IP has allowed the market to be highly successful. Over the years, some users of IP have been disgruntled with the lack of design flexibility and the high licensing fees and royalties associated with closed architectures.

Open architecture IP allows users to customize and adapt cores to their own specific applications and provide the opportunity for unique differentiation. RISC-V is an open-architecture Instruction Set Architecture (ISA) that is garnering industrywide attention.

The RISC-V Foundation was established to promote industry adoption and ecosystem collaboration of the RISC-V ISA. In order to gain a better perspective on the current situation, industry perception and future outlook, Semico Research surveyed industry players. Questions revolved around the use and adoption of the RISC-V ISA and its implementation. Semico Research then analyzed the data to develop a forecast for the number of RISC-V cores that will be consumed by the market.

Semico Research conducted a survey (RISC-V Market: Momentum Building) in November 2020 of RISC-V users. This follows an initial survey and report published by Semico in 2019. With this study, we wanted to quantify the total available market (TAM) for IP cores and estimate the served available market (SAM) for RISC-V IP cores. We surveyed and interviewed a cross section of the semiconductor industry to gather information related to the type of devices that are being designed with RISC-V and their target markets.

Semico, in conjunction with the RISC-V Foundation, identified 35 markets and developed both a TAM and a SAM for each of these markets. Utilizing Semico’s extensive end-market databases, we developed a forecast out to 2025. This report focuses on four semiconductor devices which have a high value opportunity to use RISC-V cores. These devices are:

  • Advanced Performance Multicore SoC
  • Value Multicore SoC
  • Basic SoCs, and
  • FPGAs

Semico’s survey results, RISC-V Market: Momentum Building, indicated increasing interest and significant ongoing developments for RISC-V products in all major end applications. RISC-V devices are also targeted at a broad range of performance levels. The compound annual growth rate for RISC-V cores between 2020 and 2025 is nearly 160%. The fastest growing served available market is automotive which is projected to achieve a 217.7% CAGR.

By 2025, Semico Research predicts that RISC-V cores will capture over 14% of the overall CPU core business. We also expect this trend to continue beyond 2025 as RISC-V gains market share and the ecosystem continues to evolve and mature.

RISC-V’s flexible, open-source strategy provides a competitive advantage which is changing the landscape of the CPU IP market. Other IP vendors have or will expand their architecture to provide an open-source option to maintain a competitive position in the market.

For more information on  RISC-V Market: Momentum Building.

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How Mentor became Siemens EDA

How Mentor became Siemens EDA
by Daniel Nenni on 04-05-2021 at 6:00 am
Categories: EDA
7 Comments

Messy dog food

When I started in EDA the big three were Daisy, Mentor and Valid (DMV as we called them). Then came Synopsys in 1986 followed by Cadence, which was a clever merger between ECAD (Dracula DRC) and Solomon Design. Daisy and Valid were pushed aside and then there were, “Three dogs hovering over one bowl of dog food, not a pretty site.” said Joe Costello, former CEO of Cadence, June 1995, CEO Panel discussion, Design Automation Conference.

The fourth comer was Avanti which of course was undone by a “minor” legal problem. I worked for Avanti so I can tell you from personal experience that acquisitions made that company a shooting star and a lazy outside consultant brought it back down to earth. As a result Synopsys acquired Avanti in 2002 then there were three again.

Just a quick note on the Avanti acquisition, Cadence sued Avanti into submission and to save the company from annihilation there was a handshake merger deal with Mentor. Avanti then took that handshake deal to Synopsys and a better deal was made which included extra money for “key” executives meaning the Avanti CEO and his son. Handshake deals meant nothing to Avanti.

Twenty years later the big three EDA dogs are Synopsys, Cadence, and Siemens EDA and the big three have never been bigger. So, how did Mentor become Siemens EDA?

Back in 2011 Mentor attracted the interest of stock activists. In fact, one of the most notorious stock activists, Carl Ichahn, made an unsolicited $1.9B bid saying Mentor must be sold to appease disenfranchised investors. As it turns out Carl was right but his timing was off and so was his price. In 2016 Siemens made a $4.5B offer for Mentor which was accepted but the question is why?

Siemens made the call to Mentor at the right time. The stock was down and activists were again starting to rattle sabers. The real issue was a change in customers: EDA was transitioning from chip companies as the majority of customers to systems companies, and systems companies do business differently.

EDA was really founded on the point tool concept. Point tool companies would bring innovation to EDA with the ultimate goal of being acquired. Chip companies used point tools to get better chips and better pricing from the big EDA companies. Selling just chips is a much smaller margin proposition than systems so EDA budgets were always tight. I remember routinely being told by big chip companies that they were cutting budgets but they wanted more tools.

Systems companies however look for a complete vendor solution covering as many steps in the systems development process as possible. Apple is a perfect example of a systems chip company and now there are many others.

Unfortunately, Mentor had fewer pieces of the systems puzzle than Synopsys and Cadence so they were at a disadvantage. Synopsys and Cadence also had a much more aggressive acquisition strategy than Mentor so the lead was widening.

Now comes Siemens which is the largest engineering solutions company that sells more than $60B to systems companies around the world every year (Synopsys and Cadence combined revenue is around $6B). Definitely a game changer for EDA. And having been with quite a few EDA/IP companies that have been acquired (including by Siemens) I can tell you by experience, Siemens is in this to win this.

So, now we again have three big dogs eating from a larger bowl of dog food, which is much more interesting to watch, absolutely.

Podcast EP10: The M&A Landscape for Semis and EDA