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Solve Embedded Development Challenges With IP-Centric Planning

Solve Embedded Development Challenges With IP-Centric Planning
by Kalar Rajendiran on 07-18-2022 at 10:00 am
Categories: EDA, Events, Perforce

Requirements and Planning Stuck in the Past

At least once if not more, many of us may have faced the following situation. We download the latest software driver for a device only to find out after installing that it doesn’t work for your hardware. As per the release notes, it should work for your hardware but in reality it does not. We have no choice but to revert back to the earlier version of the driver. In some other cases, it may not be such a straightforward case of completely not working. And these situations are tricky as the bugs may manifest in subtle ways.

Though the above scenarios involve hardware/software interactions, such mismatches between requirements and solutions could be either solely hardware related or solely software related too. In this context, hardware assets and software assets together make up a company’s intellectual property (IP). While there is a lot of attention paid to reusability of IP assets, is there enough being done to keep requirements changes and design/implementation changes in-sync through the development and release cycles? This is the focus of a webinar that was hosted by Perforce a few weeks ago. Vishal Moondhra, Vice President of Semiconductor Solutions at Perforce presented some insights. The following are some salient points from his talk.

Challenges Faced During Embedded Development Cycle

Development teams are usually organized along project-basis with limited visibility into all of the available IPs within an organization. The software and hardware teams track requirements and IP using independent spreadsheets and other documents.

Hardware-led waterfall approaches are in style-opposition to typical agile-development software methodologies. The embedded software stack is often tracked using multiple spreadsheets, separating developers from the final design. These ad-hoc, peer-to-peer, untracked dependencies are the source of many issues faced further down the line.  Even with the collaborative spirit in the context of hardware/software co-design/co-development requirements, connectivity between the groups is usually broken.  The disconnect between the teams causes issues, delays, and compatibility problems.

During the development cycle, the requirements changes and planning quickly get out of sync and keeping them aligned is a usually a tedious process.

In addition, internally developed and 3rd party hardware IP are often used for a specific project, with limited visibility offered to outside of the immediate project team. Once a project is complete, the team’s collective knowledge dissipates as the team members move on to other tasks.

Streamlining for Overcoming the Above Challenges

Hardware and software teams need to collaborate through a single system that can seamlessly handle the complexities of both hardware and software development. This approach would allow all teams to share applicable IP across projects and bring software teams into the design process.

While the requirements management can still be managed on a per-project basis, having this unified IP-centric approach helps in the following manner.

  • Status and availability of each component of their design is accessible to all teams
  • Traceability of IP is improved (a requirement for many end-markets)
  • Time-to-market for the end-product is improved
  • Errors and incompatibility issues are reduced

Embedded Development IP-Centric Platform

The idea behind such a platform is to attach requirement dependencies to the IP blocks as meta data. Under this approach, the IP becomes an abstraction of data files that define its implementation with the meta data defining its state. Such a platform can be used to plan and execute the IP Bill of Materials (BoM) from the very start of a project.

The key features of this platform should include:

  • Interfacing with ERM and manufacturing focused PLM tools to provide high level data on IP that matches your requirements
  • Enabling hierarchical planning on all IPs, 3rd party and internal, that can be used across an organization.
  • Generating the Component & IP BoM (CIPB)
  • Providing a holistic view of your software and hardware IP to deliver a single, unified BoM to manufacturing

With the above features, consistency can be maintained throughout the embedded development process. And, as the development evolves, everything can be tracked and traced back to the original requirements/IP.

 

 

Perforce Solutions

Perforce’s Methodics IPLM provides a scalable IP lifecycle management platform that tracks IP and its metadata across projects, providing end-to-end traceability and enabling effortless IP reuse. The Perforce Helix Core is a high performance data management system that can be used to support global teams with storage, access, and management of design assets for analog, digital, infrastructure, and software development. Together, these tools provide a single source of truth for a whole project.  Perforce Planning and Collaboration Suite for Semiconductor integrates with hardware tools using a flexible REST API.

Also Read:

WEBINAR: How to Improve IP Quality for Compliance

Future of Semiconductor Design: 2022 Predictions and Trends

Webinar – SoC Planning for a Modern, Component-Based Approach

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Clocking for High-Speed SerDes

Clocking for High-Speed SerDes
by Tom Dillinger on 07-18-2022 at 6:00 am
Categories: Cadence, EDA, Events

SerDes architecture

The incessant demand for faster data rates across a wide range of end applications has led to the development of the most recent generation of SerDes hardware, achieving 112Gbps.  For example, network switches in datacenter architectures are starting to provide 51T throughput utilizing these new 112Gbps implementations (51.2Tbps with 512 lanes).

The 112Gbps SerDes designs will be adopted in a variety of configurations, based on the application.  The figure below illustrates Long Reach (LR), Medium Reach (MR), Very Short Reach (VSR), and Extra Short Reach (XSR) topologies, where the 112G signaling path is highlighted in each.

The insertion loss, power per bit, and bit error rate (BER) requirements for these configurations vary considerably – the constraints on the SerDes design to satisfy all these usage cases are considerable.

Yet, there is another consideration to the design of high-speed SerDes IP – namely, the need to support multiple communications protocols, across the gamut of data rates associated with these standards.  In other words, the network architect needs the flexibility to program the switch to support legacy data rates within the protocol, as well as enabling the latest generation systems.  The figure below provides examples of the multiple protocols and data rates to be supported by a general-purpose high-speed SerDes:

    • Ethernet
    • PCIe
    • Common Public Radio Interface (CPRI, between a radio receiver in a tower and a baseband station)
    • Fibre Channel.

As a result, it is necessary that each lane of the protocol have independent rate programmability with individual speed settings.

At the recent VLSI Symposium on Technology and Circuits, Aida Varzaghani from the High-Speed SerDes design team at Cadence Design Systems presented a thorough description of Cadence’s 112Gbps design, recently fabricated in a 5nm technology node.  This article will highlight only a portion of Aida’s presentation, to illustrate the unique clocking design incorporated into the SerDes IP for broadest applicability.

The general architecture of their 112G SerDes is shown in the figure below.

The fundamental macro design is a set of four lanes with an embedded global clock generation unit.  (Additional lanes can be added to the macro.)  The figure below provides an example of the unique protocol data rates (and signal modulation) that could be programmed for individual lanes sharing the global clock distribution.

As shown in the figure below, the global PLL distributes three (single-ended) clocks to the adjacent Tx/Rx lanes.  The table in the figure illustrates examples of the global PLL internal voltage-controlled oscillator (VCO) frequency, and the clocks from the “global dividers” which are output to the lanes.  The VCO frequency of the lane PLLs and the final lane clock frequency are also shown.

Note that a Tx PLL and an Rx PLL are integrated in each lane.  The Tx lane PLL synthesizes the target frequency (at 1/4th of the data rate, as described shortly).  The dedicated Rx PLL is used to recover/track the clock from the incoming SerDes data.

The circuitry for the clock input to the lane Tx/Rx PLLs is shown in the figure below.

The three input clocks to the lane from the global PLL dividers are multiplexed to the lane PLLs by dotting three driver outputs, with programmable tri-state enables.  (A buffer sends the clock to the next lane.)  Each driver is sourced by a unique low drop-out regulated supply voltage.  This configuration reduces power supply noise-induced jitter in the lane PLL clock input.

The Tx and Rx PLLs are identical, as shown below.

The Ring VCO in each PLL provides four phase-shifted (quadrature) clocks from the base frequency, which defines the unit interval for the data rate transmission, as depicted below.

Low data rates are enabled by digital bit stuffing.  Aida also presented details on the methods for continuously correcting the duty cycle and minimizing the arrival skews of the (quadrature) clocks to reduce output jitter.

The Rx clock data recovery functionality is supported by a phase interpolator, which adjusts the Rx clock phase to the feedback divider and input phase-frequency detector.  The individual phase edges in the interpolator are extracted from the phase-shifted signals within the oscillator, as shown above.

The IP testsite die in the 5nm process node and the loopback test configuration used to characterize the circuitry are shown below.

The figure below shows the Rx characteristics from the loopback test – specifically, the power per bit and the BER for different data rates.

Summary

The design of the latest generation high-speed SerDes IP needs to provide maximum flexibility, capable of supporting different protocol standards and a wide range of data rates.  Per-lane programmability is an important feature to network architects.

At the recent VLSI Symposium on Technology and Circuits, the Cadence SerDes team recently highlighted their 112G IP macro approach, specifically the unique global and Tx/Rx lane clocking architecture to support these varied protocol and data rate requirements.

For more information on the Cadence 112G SerDes offering, please follow this link.

-chipguy

Also read:

Using AI in EDA for Multidisciplinary Design Analysis and Optimization

Cadence Execs Look to the Future

Stalling to Uncover Timing Bugs. Innovation in Verification

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IEDM 2022 is shaping up

IEDM 2022 is shaping up
by Scotten Jones on 07-17-2022 at 10:00 am
Categories: Events, Semiconductor Services, TechInsights

68th iedm color

IEDM is one of the premiere conferences for the latest information on leading edge semiconductor technology. The 68th annual International Electron Devices Meeting will be held December 3rd through 7th at the San Francisco Hilton.

The paper submission deadline is July 14, 2022, and the late-news deadline is August 22, 2022. The conference will be an in-person event, with on-demand access to recorded presentations afterward for those who cannot travel due to COVID-19 restrictions.

“Our conference began just a few years after the transistor was invented, in recognition of its revolutionary potential,” said Srabanti Chowdhury, IEEE IEDM 2022 Publicity Chair, and Associate Professor of Electrical Engineering at Stanford University. “The breakthroughs described at the IEEE-IEDM every year since then have pushed transistor and related technologies forward, enabling the ongoing digital transformation of society. That is why our theme this year is, ‘The 75th Anniversary of the Transistor and the Next Transformative Devices to Address Global Challenges.’”

“In a way, the broad reach, interdisciplinary nature and technical depth of the topics that are featured at the IEEE IEDM serve as a kind of crystal ball showing where the industry is headed,” said Jungwoo Joh, IEEE IEDM 2022 Publicity Vice Chair and Process Development Manager at Texas Instruments. “This year will be no different, with an anticipated technical program of more than 220 presentations, plus many educational opportunities, supplier exhibits, award presentations and other events highlighting the industry’s best work.”

The 2022 Plenary Speakers have been announced:

  • Anne Kelleher, Executive Vice President/General Manager of Technology Development, Intel
  • Yusuke Oike, General Manager, Sony Semiconductor Solutions
  • Maud Vinet, Quantum Hardware Program Manager, CEA-Leti

The special focus session will be held on:

  • Advanced Heterogeneous Integration: Chiplets and System-in-Packaging
  • DNA Digital Data Storage, Transistor-Based DNA Sequencing, and Bio-Computing
  • Emerging Implantable-Device Technology
  • Quantum Information and Sensing
  • Special Topics in Non-Von Neumann Computing

The Sunday short courses will be:

  • ‘High-Performance Technologies for Datacenter and Graphics to Enable Zetta-Scale Computing,’ organized by Ruth Brain, Intel
  • ‘Next-Generation High-Speed Memory,’ organized by Yih Wang, TSMC

The Saturday tutorials will be:

  • ‘Device Innovations to Extend CMOS Scaling for the 2nm Node and Beyond,’ Tenko Yamashita, IBM
  • ‘Sensors for IoT, Automobile, Health and Other,’ Carlotta Guiducci, EPFL
  • ‘Resistive Memories-based Concepts for Neuromorphic Computing,’ Elisa Vianello, CEA-Leti
  • ‘The Era of Advanced Packaging and Hybrid Bonding,’ Sitaram Arkalgud, Tokyo Electron Ltd.
  • ‘FEOL Reliability: from Essentials to Advanced and Emerging Devices and Circuits,’ Ben Kaczer, Imec
  • ‘Fabrication and Three-Dimensional Integration Technologies,’ Qiangfei Xia, University of Massachusetts

For more information, please go to: www.ieee-iedm.org

Follow the IEEE IEDM via social media

About IEEE & EDS

IEEE is the world’s largest technical professional organization dedicated to advancing technology for the benefit of humanity. Through its highly cited publications, conferences, technology standards, and professional and educational activities, IEEE is the trusted voice in a wide variety of areas ranging from aerospace systems, computers, and telecommunications to biomedical engineering, electric power, and consumer electronics. The IEEE Electron Devices Society is dedicated to promoting excellence in the field of electron devices and sponsors the IEDM.

Also read:

3D Device Technology Development

A Crisis in Engineering Education – Where are the Microelectronics Engineers?

Supply Chain Verification: Critical Enabler for Next-Generation Medtech Innovations

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SEMICON West the Calm Before Storm? CHIPS Act Hail Mary? Old China Embargo New Again?

SEMICON West the Calm Before Storm? CHIPS Act Hail Mary? Old China Embargo New Again?
by Robert Maire on 07-17-2022 at 6:00 am
Categories: Events, Semiconductor Advisors, Semiconductor Services
3 Comments

SEMICON West 2022

-SEMICON good conference -No news but perceptibly nervous
-Memory chip warnings & memories of cycles past haunt us
-Can we turn the clock back 20+ years on China Chip Policy?
-Last ditch efforts on Chips for America before government vacation

SEMICON West Conference

Attendance at the show was good, better than last Decembers attempt at a Covid make -up event. We saw fewer people from Asia, except vendors, as well as fewer people from US companies like Intel, Micron or GloFo.

The show floor remains the domain of small companies selling bits and pieces of technology with a couple of exceptions. The vast majority of the real show goes on in nearby hotels with meeting rooms for private one on ones with customers. The big three US companies Applied Materials, Lam and KLA had little to no real presence and neither did ASML.

Nervous anticipation – The calm before the storm?

Most every company we spoke to reacted the same way….rather than saying “business is great” they almost all said that “we haven’t seen any evidence of a downturn yet, no cancelations, business remains strong”.

That response certainly gives away everyone’s fears that we are on the precipice of the down cycle hitting equipment makers. When asked about Micron or LG warnings the response was “we haven’t seen any push outs or cancelations yet”. Adding the word “yet” says a lot.

Everyone is still reporting huge backlog and lead times, but in the same breath admit that those orders could easily vaporize as they have in the past.

This would certainly lead us to believe that the second quarter that is about to be reported by most companies should be more or less in line with expectations and normal “beats”. We got no wind of any misses, no pre-announcements etc; , its still business as usual….very strong…..for now.

CHIPS Act, last ditch, Hail Mary- slimmed down version Is is small enough to squeeze through before vacation?

As the desperation to get anything passed before congress leaves on summer recess the sponsors of CHIPS for America Act are taking hatchet to all the extra stuff attached to it to try to get down to a simple version that has a chance of getting past all the political nonsense.

This week, Mitch McConnel ( Doctor No) let it drop that he might be willing to think about a slimmed down version of the bill he previously voted for then rejected. Raimondo quickly picked up on that sentiment, seeing an opening and said she would “cleave off” all the extraneous stuff.

Link to Raimondo on “Cleave off” CHIPS Act

It now looks like Schumer may want to bring the slimmed down version to the table next week. Time is running out and we are at the 11th hour before congress turns into a pumpkin and goes on summer vacation. As congress will be in full blown election mode when they are back from vacation its now or never

Scare tactics are now being employed. We have been talking about the risk to the semiconductor industry from China for at least 7 years now, and no one paid attention, and finally, at the last minute, when CHIPS Act backers are getting desperate, people are finally waking up to the risk.

Legislators should have been smart enough to be aware of these issues a long time ago and it shouldn’t have taken an 11th hour panic before everyone woke up.

NY Times- Chips “a very dangerous situation”

We certainly hope the CHIPS Act gets passed but it should not have been this hard nor long. This should have been a “no brainer” but the problem is that politics and politicians got in the way and had “no brains”…..

Back to the future and the Chip equipment China Embargo of the past

We have mentioned several times in our newsletters that we have been in the industry long enough to remember things from the 1990’s.

Back then, we were working on the SMIC IPO which was in itself revolutionary as it was the first IPO of a foundry in China and the company that put China on the map in semiconductors.

Way back then SMIC was restricted to only buying semiconductor equipment and technology from the US that was at least 3 generations behind or older (N minus 3). Export licenses and restrictions were in place and the defense and commerce areas of the government enforced things., China got the equipment as was happy to make chips for watches, dishwashers & TVs. It seemed to work fine for a while until the restrictions faded away.

“N minus 3” We seem to be back in a 1990’s position and may codify it

N minus 3 means 3 nodes behind the leading edge node. Today, the industry is more or less at 5NM (in production) and in China, 14NM, which SMIC is running at (more or less) is about 3 nodes behind, 7NM and 10NM being in between.

So in effect we are still where we were back in the 1990’s which had strict rules to keep China 3 nodes behind. We have heard rumor that there is thought and motion to go back to codifying and enforcing N minus 3 restrictions (embargoes) on China. This would essentially enforce where we are today, in law.

Certainly not the worst thing in the world except from China’s position. It could stop some equipment sales but not a whole lot as most of China is trailing edge that is N-3 or older….in some cases much older. China’s semiconductor industry could happily make chips for toys, appliances and cars just not leading edge for military or 5G or AI or processors.

Maybes the 1990’s weren’t so bad after all

The Stocks
The stocks will likely see a bump up if CHIPS act passes. The Hail Mary pass being contemplated looks potentially viable (unless Dr No has another change of heart).

We think the actual dollars are less important than the tax credits and the signal it sends.

If the US couples that with some further restrictions on China that would be positive for chip companies and slightly negative (in the short term) for equipment companies, but likely not much near term impact as any restrictions would not likely apply to orders in the pipeline or may be phased in.

The bigger issue leaning on the stocks is the macro economic issues and concerns and how that will impact demand (obviously negatively but how negative).

We don’t know if we are going to get more warnings like Micron….we nay not, but the fear has already taken root. We could see a bit of a bounce as good earnings come in without warnings but one or two warnings from and Intel or AMD or similar could trash things again.

We would get involved on a short term basis on some of those stocks that had an overly negative reaction or haven’t seen any bounce but we still see the second half of the year as being cloudy at best.

About Semiconductor Advisors LLC
Semiconductor Advisors is an RIA (a Registered Investment Advisor), specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space.

We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors.

We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also Read:

ASML- US Seeks to Halt DUV China Sales

Micron kicks off the down cycle – Chops 2023 capex – Holding inventory off street

Semiconductor Hard or Soft Landing? CHIPS Act?

Podcast EP94: Wally Rhines Comments on the latest SEMI Electronic Design Market Data Report

Podcast EP94: Wally Rhines Comments on the latest SEMI Electronic Design Market Data Report
by Daniel Nenni on 07-15-2022 at 10:00 am

Dan is joined by Dr. Walden Rhines, former CEO of Mentor Graphics, which is now Siemens EDA, and current CEO of Cornami. Wally is also the Executive Sponsor of the SEMI Electronic Design Market Data Report, which is the topic of this podcast.

Wally reviews the latest report, including the backstory of how the report is generated and how it can be used. Spoiler alert: it’s another positive growth quarter overall.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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CEO Interview: Shai Cohen of proteanTecs

CEO Interview: Shai Cohen of proteanTecs
by Daniel Nenni on 07-15-2022 at 6:00 am
Categories: Analytics, CEO Interviews, proteanTecs

proteanTecs Image

Shai Cohen is an entrepreneur and industry veteran, with vast experience in building technology companies from the ground up. He is a co-founder and CEO of proteanTecs, which develops revolutionary Universal Chip Telemetry™ for electronic systems throughout their entire lifecycle. Prior to founding proteanTecs, Shai co-founded Mellanox (acquired by NVIDIA), a global leader of end-to-end InfiniBand and Ethernet interconnect solutions for servers and storage. He served as Mellanox’s Chief Operations Officer from 2011 and before that as VP of Operations and Engineering, from 1999. While at Mellanox, Shai oversaw all internal operations and production, and co-led the company’s research and development activities. He served as a member of the Mellanox Board of Directors from 2015 to 2018. From 1989 to 1999, Shai worked at Intel Corporation, where he was a senior staff member in the Pentium processors department and a circuit design manager in the cache controllers group. Shai holds a B.Sc cum laude in Electrical Engineering from the Israel Institute of Technology, Technion.

Can you tell us a little about proteanTecs?
proteanTecs was founded with a mission to enable the electronics industry to continue to scale. We’ve developed deep data analytics for advanced electronics in the Datacenter, Automotive, Communications and Mobile markets.

The company provides solutions for health and performance monitoring, in production and during lifetime operation, based on Universal Chip Telemetry™ (UCT). By applying machine learning to novel data created by on-chip UCT agents, our customers gain visibility and actionable insights on the cloud or edge – leading to new levels of performance, quality and reliability at scale.

How do you provide deep data insights on chips and systems?
The technology is comprised of several key pillars. First and foremost is the deep data generation. We’ve developed Universal Chip Telemetry (or UCT) which provides on-chip monitoring, based on agents that are built for analytics. These UCT agents operate in both test and mission modes and provide extremely high coverage of key parameters at every stage. They are strategically placed during design, using automated insertion tools, after a thorough analysis of the design and process technology.

Measurements from the agents are extracted and uploaded to a software platform, for data fusion and domain-infused machine learning inference. At the end of the day, our customers get advanced analytics, with actionable insights and alerts, on a cloud-based platform, for continuous health and performance monitoring. We also provide applications that are deployed at the edge: whether on the tester during production, or on-board when the system is in the field.

How essential is electronics analytics and predictability?
We are addressing application markets that are mission-critical, uptime-critical and safety-critical. Datacenters, automotive and communications – all of these markets are transitioning to as-a-service business models. They have zero tolerance for unplanned downtime or errors, and require extremely high performance, low power and increasing functionality.

So, manufacturers are introducing highly advanced technologies to enable this. We’re talking about sophisticated architectures, complex designs, shrinking process technologies, heterogeneous packaging, and more.

All of these create new challenges in the industry. Quality and reliability are harder to achieve, especially without giving up performance or competitiveness. Costs are rising, and mainly there is a lack of visibility throughout the lifecycle. Add to this a very fragmented value chain, with data siloes in and between the different stages, and what we’re seeing, are new problems.

We see very long development cycles, a huge dependency on product warranty, and if something does go wrong – an extremely high rate of “No Problem Found” with inconclusive and long root cause analysis. And at the end of the day, we also see problems and reliability issues in the field.

What types of challenges can this solve?
We’re hearing more and more from hyperscalers and OEMs about new issues that they encounter in the field, all stemming from undetected or latent manufacturing defects or issues that manifest in the field and are hard to predict and prevent.

In the case of advanced electronics, system performance becomes a sensitive matter. Add to this the fact that certain parameters will change after extended use, especially given application stress and environmental effects, and you have the recipe for issues that can be as difficult to pinpoint as they are costly to endure.

In some cases, these errors happen in a way that cannot immediately be detected or flagged.  Sometimes a calculation will give the wrong result.  Other times an instruction doesn’t behave exactly as it should. In certain cases, the error is inconsistent, making it even more difficult to find.

These service providers want for their systems to be able to recognize these errors and report them. It would be even better if they could be predicted. Imagine that you could see the actual performance margins of the electronics while the application is running, and act on it.

What are the benefits of your platform and how is it different from what others are doing in the industry?
We’re introducing a new approach. proteanTecs has developed a way to provide end-to-end visibility, based on deep data analytics. With this new technology, manufacturers and service providers gain a new understanding of design, production, system, applications, and environmental issues, throughout the lifecycle of the system.

Since the same agent-based technology is applied at every stage, starting from chip characterization, qualification and volume production, through to system integration and optimization, and then to in-field operation – it creates a baseline of common datasets throughout the industry. This provides backward-and-forward correlations, insights and predictions, and for the first time creates a common ‘data’ language for the value chain.

What are the use cases for proteanTecs’ technology?
We’re giving chips the ability to report on their own health and performance so that at every stage, from production to the field, users gain significant insights and benefits.

During production, chip and system vendors can reduce Defect Parts Per Million (DPPM) by 10x, optimize power-performance per application, improve performance yields, optimize and track reliability margins and significantly shorten time to market.

Once deployed in the field, service providers can be alerted on faults before failures, significantly lowering maintenance costs, optimize system performance, and extend product lifetime.

Who are some of your current customers/users?
We serve leading electronics vendors across multiple industries, including Datacenter, Cloud Computing, Automotive, AI and Communications. Our customers include first tier customers for chips that include AI, switches, servers, storage, HPC, communications, and ECUs.

How much funding have you raised in total to date?
Nearly $200M. We are backed by some of the leading investors in the electronics and SaaS industries. I am happy to share that we’ve recently closed two extensions to our Growth Equity round, with the addition of Porsche-SE, MediaTek and Advantest to our investor portfolio – each one being a market leader in their own industry vertical.

Are there any previous or upcoming milestone you’d like to talk about?
We recently expanded into mobile and have launched solutions for supply chain security and real-time power-performance management.

Also read:

CEO Interview: Vaysh Kewada of Salience Labs

CEO Interview: Chuck Gershman of Owl AI

CEO Interviews: Dr Ali El Kaafarani of PQShield

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Alchip Technologies Offers 3nm ASIC Design Services

Alchip Technologies Offers 3nm ASIC Design Services
by Kalar Rajendiran on 07-14-2022 at 10:00 am
Categories: Alchip, Semiconductor Services

Alchip Design Technology Roadmap

Throughout its history, the ASIC industry has had its ups and downs. With feast and famine cycles, the ASIC business model is not for the faint of heart. Some companies tread boldly while others dread the cycles and stay away from this business model. Those who are consistently successful have to overcome many challenges thrown at them. This in turn requires focused dedication to the model and ongoing strategic investments to stay on top. ASIC companies stay consistently successful by judiciously overcoming the many challenges thrown at them.

ASIC Business Model Challenges

Supply Chain

In a sense, it was easier when ASIC companies were vertically integrated with their own foundries. Not only did they gain early access to the latest process technology details, all their customers’ wafer volume aggregated to the same foundry as well. This is no longer the case, with ASIC companies having to tap third party foundries. And this points extends to other parts of the supply chain too.

Customers

In addition to the PPA benefits of an ASIC, customers go the ASIC route for advantageous pricing compared to choosing an ASSP. It is interesting to highlight that the term ASIC itself is a misnomer. The product is a customer-specific product targeted toward an application.  Naturally, every customer is likely going to aggressively push the ASIC provider in non-overlapping ways on both technical and commercial aspects.

Alternate Solutions

While technically many products could benefit from an ASIC implementation, depending on the end market and the commercial terms for an ASIC, customers may choose an alternate non-ASIC solution. For example, customers may be willing to go an ASSP, FPGA or a GPU route to save on the upfront NRE investment and/or design cycle time and time to market. This is one of the things that happens on a regular basis and certainly when the ASIC market goes through the famine part of the feast-famine cycle.

Strategic Investments

Significant design capabilities and infrastructure investments are expected off of ASIC providers to support HPC, cloud computing, edge computing, AI, automotive and other applications. With the slowing down of Moore’s law benefits on advanced process nodes, large monolithic chips are giving way to chiplet based implementations. With chiplets, one can have the best of both worlds. Leading edge process for some chiplets and main stream/trailing edge process for others. An ASIC provider will be faced with supporting heterogeneous chiplets integration. Investments in developing capabilities and methodologies to support 2.5/3D packaging and high-speed Die-to-Die interfacing are critical to keep up with the trends. Being involved in standardization efforts such as the Universal Chiplet Interface Express (UCIe) is critical.

Design Technology and Infrastructure

Whether an ASIC or an ASSP, PPA, cost, and time to market are the lowest common denominator requirements. Accordingly, design service organizations hone their design technology, methodology and infrastructure on an ongoing basis. The added challenge for ASIC design service organizations is that different customers are going to stress their infrastructure differently. For example, clock methodology that may yield optimal results on one customer’s chip may yield sub-optimally on another customer’s chip, impacting performance. The P&R methodology may run into different issues depending on the chip and thereby impacting die size. And so on. All of these impact time to market for the customer and revenue and profitability impact for both the customer and the ASIC provider.

Consistently successful ASIC providers have top-notch infrastructure and methodologies that can accommodate varied demands from multitude of customers.

Success Requires Focused Dedication

For overcoming the challenges described in the above section and the business model challenges section, a successful ASIC company needs:

  • Robust yet flexible design methodology
  • Flexible engagement model (both commercial and technical)
  • Best-in-class IP portfolio (access to third-party IP and in-house IP/customization)
  • Heterogenous chiplet integration capability
  • Advanced packaging and test capabilities

In order to deliver all of the above in a viable manner, one needs to pick a focus in terms of what markets they serve.

Alchip Treads Boldly

Alchip picked the high-performance markets as their dedicated focus many years ago and stayed the course. They have made strategic investments to stay with the trends and developed design technology and infrastructure to service their customers. Their dedication has yield everything that is identified in the above section. Alchip has consistently stayed on top of supporting the latest process nodes from TSMC, the leading foundry. Not only have they developed capability to support 2.5D/3D packaging in general but also been qualified to support TSMC’s CoWoS packaging technology. They had developed APLink family of Die-to-Die interface IP to support chiplets integration well before the UCIe efforts began. And now they have joined the UCIe consortium as a contributing member to drive the evolution of the chiplet interface standard.

Alchip Profile and Scorecard

The following slide provides a succinct profile of Alchip. An 81% slice of revenue coming from HPC markets is proof of their dedicated high-performance market focus.

Recently, Alchip announced that its high-performance computing ASIC services are now taking 3nm designs and targeting their first test chip for Q1 2023. The new service targets TSMC’s latest N3E process technology. With this announcement, Alchip becomes the first dedicated high-performance ASIC company to announce total design readiness of their design and production ecosystem for 3nm process. Their press announcement mentioned the other assets in place include a complete library of best-in-class 3rd party IP covering DDR5, GDDR6, HBM2E, HBM3, PCIe5, and 112G SERDES IP from Tier 1 providers.

You can learn more at www.alchip.com. You will find a compendium of Alchip related articles and press releases on SemiWiki here.

Also read:

The ASIC Business is Surging!

Alchip Reveals How to Extend Moore’s Law at TSMC OIP Ecosystem Forum

Alchip is Painting a Bright Future for the ASIC Market

 

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Arm Aims at Mobile Gaming

Arm Aims at Mobile Gaming
by Bernard Murphy on 07-14-2022 at 6:00 am
Categories: Arm, IP
1 Comment

ARM gaming min

Clearly unfazed by the collapse of the proposed merger with Nvidia, Arm just announced products in support of, what else, mobile gaming. Nvidia turf. Of course Nvidia’s gaming strength is in tethered platforms or laptops. However, understand that 50% of video gaming revenue in 2020 came from smartphone games and that growth is accelerating. Arm is clearly happy to grab for themselves what Nvidia maybe hoped to corral in the merger. A question came up in a recent briefing, “Won’t streaming make all but simple local graphics irrelevant on the phone?” Paul Williamson (SVP and GM at Arm) disagreed, and I’m 100% with him. Even with 5G (or 6G) bandwidths, power demand in streaming communication will kill effective gaming time. And latency overhead from phone to cloud back to phone will kill an interactive gaming experience with immersive pose-responsive 3D. Gaming demand on Android platforms (Apple has their own hardware) is ripe for the picking.

Graphics platforms

The announcement includes a new flagship GPU Arm are calling Immortalis-G715. This springs from Mali, with optimizations for 3D and with hardware-based ray tracing. Ray tracing is a powerful addition to immersive experiences, supporting realistic reflections and lighting which changes as you move through the scene. It’s also computationally very expensive, hence the need for hardware support. Given lack of support in mobile gaming to this point, Arm seems to be making a forward bet. That game developers will come to embrace how this can enhance user experiences.

Mali-G715 includes variable rate shading for improved resolution around user gaze and reduce resolution outside that area, to improve performance and reduce power. And Mali-G615 upgrades the earlier 610 release. Overall, this GPU lineup is adding 15% performance over last year at 15% better efficiency.

Armv9 updates

High performance GPUs must be matched by high performance CPU clusters to deliver an end-to-end gaming experience. This release introduces the Cortex -X3, the highest performance CPU to date in their portfolio, delivering 25% performance over latest Android smartphones and 34% performance advantage over latest laptops. The Cortex-A715 offers only a 5% performance advantage over the earlier 710 but at 20% improved energy efficiency, making this a very effective “little” match to the Cortex-X3 “BIG”. Another nice plus for mobile power/ performance management.

Beyond smartphones

Another interesting question in the briefing Q&A probed Arm plans outside established handset and compute server markets. What about Arm graphics engines in the datacenter or Arm PCs? Paul brushed off the datacenter graphics question as not an area of focus for Arm today but was more open to discussing the other topics.

MediaTek is at least one company that has announced plans to build Arm-based chips for Windows. Microsoft announced earlier this year their project Volterra, an Arm-based desktop PC with additional goodies. Paul said that now developers will now be able to develop on Arm, for Arm in Windows which he sees as a step change in the ecosystem. He added that with Cortex-X it is now possible to bring the performance/power advantages of Arm-based architectures to the PC world. Despite our earlier reservations, they pulled it off in the server space so why not here too? Market motivation for PCs may be a little different – perhaps a “green” advantage could be a major driver.

Finally, what about untethered xR devices? Here Paul was a bit more circumspect. Certainly, power and performance needs should play well to this GPU and CPU lineup. The issue he sees is more around a great diversity of use cases. He sees the market as still nascent. Product can build on these new platforms, helping to drive clarity in where there may be high volume use-cases with more clarity in needs. Until then, we’ll all be watching with interest.

You can learn more about the release HERE.

Also read:

Synopsys Tutorial on Dependable System Design

Arm Shifts Up With SOAFEE

Arm Announces Neoverse Update, Immediately Following V9

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New Mixed-Signal Simulation Features from Siemens EDA at DAC

New Mixed-Signal Simulation Features from Siemens EDA at DAC
by Daniel Payne on 07-13-2022 at 10:00 am
Categories: EDA, Siemens EDA

Symphony Pro for mixed-signal verification

It’s the second day of DAC, and the announcements are coming in at a fast pace, so stay tuned to SemiWiki for all of the latest details. As a long-time SPICE user and industry follower, I’ve witnessed the progression as EDA vendors have connected their SPICE simulators to digital simulators, opening up a bigger world of Analog Mixed-Signal (AMS) verification. Engineers designing chips for automotive, imaging, IoT, 5G, HPC and storage devices all need AMS verification tools. Siemens EDA has a rich history in both the SPICE and digital simulator worlds, so it’s no surprise that their AMS tool would also be offered and updated, especially as design challenges and standards emerge. I was able to view a presentation from Sumit Vishwakarma of Siemens EDA to get an update at DAC of their new mixed-signal verification features.

Accellera has created a UVM-AMS working group, and Tom Fitzpatrick from Siemens EDA is the Chair of the group, so know that they are on top of emerging standards. As the working group prepares and proposes standards, then EDA vendors will start to implement the standards, so that the design community has some common ground and ensure interoperability between EDA vendors.

Symphony

Siemens EDA has been offering the co-simulation of two simulators for awhile now, dubbed Symphony, and it’s well-suited for AMS applications:

Symphony Pro

What’s new for DAC this year is the Symphony Pro has some major new features:

  • Expanded support for the Universal Verification Methodology (UVM-AMS)
  • Expanded support for the Unified Power Format (UPF)
  • Visualizer MS environment – better debug for AMS designs

Here’s a visual on the improvements just launched in Symphony Pro:

The new thing with Symphony Pro is that the mixed-signal (MS) info is now saved in a new database, plus both the analog and digital waveforms can be viewed together in Visualizer MS. Here’s a diagram showing the new MS design database (yellow), and the  MS analog and digital waveforms (red and blue):

The fun part is using the new Visualizer MS, because it pulls together all of the new features of Symphony Pro in an integrated environment:

In one place you now have both the SPICE world and digital world combined, for faster, more efficient analysis, debug and verification. This is the expanded Field of Use. Logic cones allow an engineer to quickly debug to find the source of any waveform, either digital or analog. With the Visualizer MS users can now enjoy:

  • Mixed-signal hierarchy browser
  • Source code viewer, Schematic viewer, support UPF
  • Unified mixed-signal waveform viewer
  • Results annotation
  • Trace connectivity
  • Integration with existing verification and debug infrastructure

Customer Feedback

STMicroelectronics has said that, “We look forward to using Symphony Pro as our sign-off solution for present and future mixed-signal verification projects.

Jayanth Shreedhara, senior CAD manager at Silicon Labs said that Symphony Pro is, “enhancing our verification productivity from days to hours and dramatically improving our coverage closure.”

Summary

The Symphony technology works well with Siemen’s own Questa digital simulator, plus all of the other major EDA vendor simulators, so it’s kind of like Switzerland, playing the neutrality card, but for simulation. The Symphony product lives on, while the Symphony Pro tool is just an expanded version of the tool that works for AMS designs. Right now, Symphony Pro only works with Siemens EDA simulators, so not yet at the simulator agnostic stage.

If you’re at DAC this week, plan to stop by the Siemens EDA booth and ask for Sumit Vishwakarma , or just contact your local team to get deeper insight.

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Silicon Catalyst Angels Turns Three – The Remarkable Backstory of This Semiconductor Focused Investment Group

Silicon Catalyst Angels Turns Three – The Remarkable Backstory of This Semiconductor Focused Investment Group
by Mike Gianfagna on 07-13-2022 at 8:00 am
Categories: Semiconductor Services, Silicon Catalyst

Silicon Catalyst Angels Turns Three – The Remarkable Backstory of This Semiconductor Focused Investment Group

The Silicon Catalyst Angels investment group recently announced the completion of three years of operation. There are great statistics associated with the organization and its financial results.  This includes an over 4X increase in members since inception and an impressive list of investments. One of the noteworthy attributes of the Silicon Catalyst organization is its ability to build a collaborative ecosystem to nurture the startups in the incubator. Silicon Catalyst Angels has a similar DNA, which is quite unique in the investment community. Read on to better understand the remarkable backstory of this semiconductor focused investment group.

The Angel group is a separate corporate entity from Silicon Catalyst, with membership by accredited investors that have deep strategic and operational experience from their many years in the semiconductor industry. You can learn more about Silicon Catalyst on SemiWiki. Recently, I had the opportunity to explore the history and accomplishments of Silicon Catalyst Angels with some of its leadership. I was able to speak with Pete Rodriguez, CEO of Silicon Catalyst, and the board of directors at Silicon Catalyst Angels, a rather impressive team. What follows is a summary of our discussion.

The Beginning

Pete explained that when he joined Silicon Catalyst in 2017 the organization was focused on helping to craft a strong business plan for the early-stage companies in the incubator. Another goal was to provide In-Kind Partner services to remove the immediate use of scarce funds for EDA and TSMC shuttles. As is the case, the need for working capital to cover the operational costs of startups is always front and center – true then and even more so in today’s markets.

Early in the history of Silicon Catalyst, there were 20 investment groups (institutional and corporate VCs) in their ecosystem. Among them was Sand Hill Angels. Laura Swan, one of the partners at Silicon Catalyst, was also part of Sand Hill Angels, as were several other partners at Silicon Catalyst and its advisor network. Building on the procedures developed by the established Silicon Valley investment groups, Sand Hill Angels and Band of Angels, in early 2019 the board of managers at Silicon Catalyst decided to create an angel investment group, based on the plan that was developed by Richard Curtin, one of the managing partners at Silicon Catalyst. Silicon Catalyst Angels (SCA) investment group was then launched in July 2019, as a separate corporate entity, to enable accredited investors to help fund the semiconductor startups.

The SCA board of directors includes Amos Ben-Meir as president, a long-time member of Sand Hill Angels, bringing deep investment experience, with over 200 angel investments under his belt. Additional board members include Raul Camposano and Michael Joehren, along with Laura Swan, as VP of operations. The deal flow was initially targeted to hear pitches from the companies in the Silicon Catalyst Incubator but has now expanded to selectively invite other semiconductor startups not currently in the Incubator. These organizations pitch for seed funding from Silicon Catalyst Angels members. With low membership investment commitments and low annual dues, the Silicon Catalyst Angels investment group was off and running.

Building Momentum

The initial challenge was to attract new members to the investment group. The feeling was that many of the technology investors in the Silicon Catalyst ecosystem didn’t get involved with other angel groups because the fees and investment requirements were too high and, most importantly, they would rarely see a semiconductor company as a candidate, the area that this community knew a lot about. The laser focus of the Silicon Catalyst Angels group on semiconductor investments seems to have paid off. While most of the investments have been for Silicon Catalyst incubator companies, startups outside the organization have approached Silicon Catalyst Angels because of its reputation as being semiconductor savvy. This becomes another avenue for the startups to explore joining the incubator, as well as to pursue seed funding.

As any savvy investor understands, whether in semis or elsewhere, due diligence is key. With the extensive semiconductor industry expertise of the members, the Silicon Catalyst Angel group uniquely offers a level of drill-down to assist in de-risking potential investments.

The syndication of investments by angel groups is a potent strategy that is rare elsewhere, but common for Silicon Catalyst Angels. At present, this group has made multiple rounds of investments in 12 companies, with an above-industry-average IRR. The investments from the syndication of these SCA deals are an even greater dollar amount – heavily leveraging the investor ecosystem to the benefit of the startup.

Laura Swan, VP of business operations at Silicon Catalyst Angels, provided additional perspective on this during her time at Sand Hill Angels, prior to joining Silicon Catalyst. As an “outsider” at that time, there were several reasons to join a deal associated with Silicon Catalyst and its angel investment group:

  • Laser-focus on semiconductors, a complex and difficult subject to master for an investment team who typically looks at software deals
  • Silicon Catalyst’s advisor network further reduces risk
  • The Silicon Catalyst In-Kind Partner program delivers substantial monetary value, reducing the amount of investment capital needed and increasing investment leverage

All members of Silicon Catalyst Angels also get access to the Angel Capital Association, a highly respected and valuable resource to help educate angel investors and to ensure that industry best practices are well understood by its members.

Thanks to the chip shortage and responses at the political level, such as the CHIPS Act, semiconductors have become more mainstream and more widely known. It turns out Silicon Catalyst Angels is at the epicenter of this renewed interest.

What’s Next?

We also touched on the type of deals being looked at by Silicon Catalyst Angel members. To borrow from the Silicon Catalyst tagline, it’s about what’s next. And Silicon Catalyst Angels sees the very newest ideas which suggest what’s next. As an R&D solutions architect at Renesas Electronics, Silicon Catalyst Angels board member Michael Joehren was able to offer an industry view. The group is seeing far more measurement technology that leverages MEMS advances. Generally, the focus is on the blending of biotech and healthcare with a dose of high-performance bandwidth for information delivery.

Michael explained that while there is continued interest in things like glucose meters, semiconductor-assisted measurement is expanding. Chemical analysis for air quality is a good example.  There are many new standards in this area and vast networks of sensors are the only practical way to achieve compliance. Raul Camposano, another board member, explained that materials research is focused on other areas such as battery design. He also offered that the ability to literally print molecules takes massive compute capability that drives a lot of new work as well, with interesting investment opportunities at the intersection of life sciences and semiconductors.

I concluded my discussion with a “crystal ball” question. What impact will the current financial climate have on the future of semis and the associated technology? There was a lot of perspectives offered, but the general feeling was that the semiconductor industry is cyclic in nature. We are just experiencing another cycle. Yes, and now there are geopolitical aspects to also consider. At the end of the day, the growing combination of semiconductors and life sciences will continue to drive innovation, growth and the opportunity for financial and social gain.

So, there’s a bit of the remarkable backstory of this semiconductor focused investment group. There are exciting times ahead. If you’re interested, to learn more about membership details or for startups looking to pitch, contact Silicon Catalyst Angels.