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IC Manage at the 2024 Design Automation Conference

IC Manage at the 2024 Design Automation Conference
by Daniel Nenni on 06-18-2024 at 12:00 pm
Categories: EDA, Events, IC Manage

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DAC in San Francisco will once again be a can’t miss event for semiconductor professionals seeking to discover the latest developments in EDA solutions that address the wide range of issues encountered in delivering high quality IC products and electronics systems to the market. IC Manage will be exhibiting its latest innovations from its Global Design Platform, IP Central and Holodeck products that address the growing complexities of design management and data explosion that come along with advanced technology nodes that are enabling today’s cutting edge designs in AI, SoC and high performance analog products.

In the realm of design data management, the IC Manage applications team will be showing the latest GDP-XL features that deliver high performance configuration and release management that scale to 1000s of users managing and tracking millions of IP components and design variations. Other new developments extend customization features that enable customers to adapt to new workflows and usage models without complex programming or major software upgrades. Additionally, the new Time machine feature allows full traceability of design and configuration changes as well as comparison of any 2 design states & recovery of previous design states.

GDP-XL support for Git based version control has also been extended and IC Manage will be demonstrating integration with popular Git environments like Gitlab and how to reliably manage 1000’s of Git repos and release states in building complex SoCs.

IP Central has also evolved and the IC Manage team will be showing how to capture IP components and manage their lifecycle along with the customization features that enable user-configurable search pages and automatically generated and searchable IP datasheets. Integration methods with external systems like Jira for bug tracking will also be covered that are essential in delivering a full IP Asset management environment that allows data sharing across any number of enterprise reporting systems.

Helping IC design teams to leverage Cloud computing or to accelerate their internal data center performance, the Holodeck team will be showing “how to” demos of instant cloud bursting of popular EDA tools like Ansys Redhawk, Verilog simulation, Cadence Virtuoso and Siemens EDA Calibre. Holodeck’s key benefits for EDA tool performance acceleration and storage cost reduction results will also be discussed. Holodeck can deliver elastic computing which requires a a true scaleout storage I/O architecture to be able to deliver high I/O performance across 1000s of compute nodes without having to pre-copy data to the cloud or remote data centers.

For more information, please visit https://www.icmanage.com or to sign up for a DAC demo session please click HERE.

About IC Manage
IC Manage provides hybrid cloud and high-performance design management solutions for companies to efficiently collaborate on design and verification across their global enterprises, while maximizing their IP reuse. IC Manage customers include AMD, Infineon, Microchip, Qualcomm, NVIDIA, Samsung and other top semiconductor and systems companies. IC Manage is based in Campbell, CA, with additional offices throughout the U.S., Asia, and Europe. For more information visit us at www.icmanage.com.

Also Read:

WEBINAR: How to Accelerate Ansys RedHawk-SC in the Cloud

Effectively Managing Large IP Portfolios For Complex SoC Projects

CEO Interview: Dean Drako of IC Manage

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Mirabilis Design at the 2024 Design Automation Conference

Mirabilis Design at the 2024 Design Automation Conference
by Deepak Shankar on 06-18-2024 at 10:00 am
Categories: AI, Chiplet, Events, IP, Mirabilis Design, RISC-V

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This is the first time in 28 years of my visits to DAC that I have seen so many different technologies arrive at DAC in the same year.  Earlier we would have one or possibly two innovative breakthroughs in semiconductors and embedded systems that emerged at DAC. This year I expect six or may be seven to arrive, and I am not including the innovations in EDA software.

At the system-level, new architectures are propelling the need for a shift-left methodology that integrates system-level analysis and exploration, architecture trade-offs, communication with partners and requirements monitoring. Trending technologies include multi-die and Chiplets, RISC-V and ARM co-habiting, power and thermal challenges leading to more complex power management architectures, AI engines vs. GPU for vector and convolution, common architecture for all EV automobiles, micro-assurance experiments, and latency analysis of analog systems.

In the post-Covid era, Mirabilis Design has recognized the emergence of these trends.  To support these trends, we have introduced the concept of validated system-level IP and capabilities on top of performance models.  System-level IP blocks to support Chiplets/UCIe, PCIe6.0, LPDDR_5X, DDR5, DSP, GPU, AI Engines, NoCs, and DSP have been added to the flagship VisualSim Architect. Requirements can be imported from a variety of database and is fully integrated with the simulator, that provides continuous monitoring.  Other new features include thermal characteristics from the power modeling of a cycle-accurate performance model, AI workloads such as DNN partitioning on to AI/GPU/CPU, failures modeling and generation of UPF/UVM/SystemVerilog files for early verification.

We are witnessing a spurt in interest by semiconductor and automotive design communities in exploring the revamped version of VisualSim.  We strongly believe this trend will expand further as more and more designs require AI engines and devices becoming power hungry leading to an increase in thermal cost.

Chiplets have been recognized as the right choice of solution as a rapid response to new customer requirements.  Building a stock/base of different configurations that can be easily assembled for a new application is essential.  The VisualSim model of the application architecture enables a new market for chiplet IP vendors and semiconductor companies. Both can collaborate to create a solution that is optimized for the target application and workload to meet the Power-Performance-Area.  VisualSim hardware builders have been proven to create a new generation of SoC in about 2 weeks, thus enabling rapid trade-off, and dynamic documentation for distribution to OEMs and suppliers.

Power has become extremely important in both traditional processors and emerging applications such as AI, GPU, automotive architecture.  VisualSim Power Digital Twin has been built on top of the VisualSim performance model.  The design can incorporate power management, large number of states, dynamic and leakage, distribution and attenuation, negative impact of power management, batteries, and power generators such as solar panels. The models provides instantaneous and average power plots, power improvement for a new power management architecture, output thermal characteristics for temperature and heat, power for workloads and individual IP and generate SystemVerilog test benches and UPF files.

Inspite of the fact that the large vendors of the EDA industry are missing, I believe it will still be an important one for both the electronics engineers and the EDA companies supporting them.

Website: https://www.mirabilisdesign.com

Also Read:

A Modeling, Simulation, Exploration and Collaborative Platform to Develop Electronics and SoCs

Chiplets Open Pandora’s Box

Mapping SysML to Hardware Architecture

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PrimisAI at the 2024 Design Automation Conference

PrimisAI at the 2024 Design Automation Conference
by Daniel Nenni on 06-18-2024 at 8:00 am
Categories: AI, EDA, Events

DAC 2024 Banner

PrimisAI is the premier destination for cutting-edge hardware design automation, offering engineers the ultimate companion with advanced Language-to-Code and Language-to-Verification capabilities. Our interactive AI assistant swiftly addresses complex hardware challenges across the entire design stack, from concept to Bitstream/GDSII. With on-premise deployment and an easily extendable knowledge base tailored to client-specific IPs, PrimisAI ensures an unparalleled hardware design experience.

We are excited to announce our participation in DAC 2024, marking our first attendance at this premier event. At DAC, we will showcase the transformative capabilities of our product, RapidGPT, which is revolutionizing AI-driven EDA.

RapidGPT is a groundbreaking generative AI-based tool and a game-changer in the field of hardware engineering. This innovative solution empowers hardware designers with a natural language interface, enhancing productivity, accelerating time-to-market, and transcending traditional automation. Designed specifically for FPGA engineers, RapidGPT offers a more intuitive interaction for the entire design journey, guiding hardware engineers from concept to implementation.

Key Features of RapidGPT:
1. Intelligent Code Assistant: RapidGPT leverages advanced AI algorithms to provide accurate, context-aware code suggestions, allowing FPGA engineers to write Verilog code more efficiently. It understands your intent and converts it into complete HDL code. Simply describe your desired functionality, and RapidGPT delivers the corresponding code, saving time and effort.

2. Conversational Capabilities: RapidGPT features a user-friendly chat panel for easy communication, enabling users to write or improve HDL code conversationally. Whether you need assistance with a specific design element or want to explore different options, RapidGPT is here to help.

3. Contextual Suggestions: RapidGPT provides intelligent, context-aware suggestions as you write code. It analyzes your code snippets and offers helpful suggestions for completion or optimization, considering your specific design requirements and industry best practices.

4. Code Optimization: RapidGPT detects potential errors and inconsistencies in your code, helping you catch and fix issues early in the design process. This feature improves the reliability of your designs and streamlines the development process, reducing time- to-market and enhancing overall productivity.

We invite you to visit us at DAC 2024 to explore the innovative capabilities of RapidGPT and discover how PrimisAI can help drive your success. Meet our experts at booth #1344 to see live demonstrations, discuss your specific needs, and learn about the latest advancements in AI technology. You can also schedule a personalized consultation to delve deeper into how RapidGPT can be tailored to your unique challenges and opportunities.

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EasyLogic at the 2024 Design Automation Conference

Analog Bits at the 2024 Design Automation Conference

WEBINAR: Redefining Security – The challenges of implementing Post-Quantum Cryptography (PQC)

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Silicon Creations at the 2024 Design Automation Conference

Silicon Creations at the 2024 Design Automation Conference
by Daniel Nenni on 06-18-2024 at 6:00 am
Categories: Events, IP, Silicon Creations

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Silicon Creations is a self-funded, leading silicon IP provider with development in the US and Poland, and a sales presence worldwide. The company provides world-class IP for precision and general-purpose timing (PLLs), oscillators, low-power, high-performance multi-protocol and targeted SerDes, and high-speed differential I/Os. Applications include smart phones, wearables, consumer devices, processors, network devices, automotive, IoT, and medical devices.

The majority of the world’s top 50 IC companies work with Silicon Creations. 1,000+ chips contain the company’s IP using over 700 unique IP products. Silicon Creations touches over 150 production tape-outs each year with over 400 customers, with 3nm designs in mass production.

This year they are celebrating surpassing 10 million wafers in production in collaboration with TSMC, the world’s largest dedicated independent semiconductor foundry. This achievement – which includes designs from 180nm through 3nm nodes – underscores the breadth and impact of Silicon Creations’ contributions to the semiconductor industry. There are now approximately 10 billion chips with Silicon Creations IP manufactured by TSMC worldwide.

This year at DAC they will be highlighting a large portfolio of PLLs and supporting clocking IP including our highly digital, jitter optimized LC PLL. Stop by DAC booth #2325 to learn about our full line-up of high-performance IP and pick up a Silicon Creations wafer coaster.

Catch one (or both!) of their presentations at the following partner booths:
Intel Foundry (booth #2337) June 24, Mon, 3-3.20pm Clocking Solutions for Intel Foundry Advanced Process Nodes

Siemens (booth #2521)
June 24, Mon, 4-4.30pm
PLL Design and Simulation using Solido SPICE

You can see the full line of high-performance IP available from Silicon Creations here. If you would like to reach out to the company to learn more, you can do that here.

Also Read:

Creating Analog PLL IP for TSMC 5nm and 3nm

EP217: The Impact and Unique Business Model of Silicon Creations with Randy Caplan

Time is of the Essence for High-Frequency Traders

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Truechip at the 2024 Design Automation Conference

Truechip at the 2024 Design Automation Conference
by Admin on 06-17-2024 at 6:00 pm
Categories: Events, IP, Truechip

DAC 2024 Banner

We are excited to announce that Truechip, a leading provider of Verification IP solutions, will be actively participating at DAC 2024, taking place from June 23-25 at Moscone West, San Francisco, CA. This event is a pivotal gathering for professionals in the verification industry, and Truechip’s presence will be a highlight for attendees interested in state-of-the-art verification technologies.

Visit us at our booth 2343 on Level 2 in the exhibition hall where our team will showcase the latest advancements in Verification IP and the NOC Silicon IP. Explore our comprehensive portfolio of products designed to meet the evolving needs of the industry. Engage with our experts to learn how Truechip’s solutions can enhance your verification processes and improve efficiency.

The VIP protocols that are developed by the company are exhaustive and consist of protocols families like Bus, Interface, MIPI, Automotive, USB, Networking, Storage, AMBA, PCIe, Memory, Display, RISC V, Defense and Avionics with some of the distinguished protocols such as PCIE Gen 6, UCIE,APHY, Ethernet 800G, USB 4, Display Port, CXL 3.0 , TileLink, DDR5, LPDDR5, AXI 5, RI5CY, JESD204 C, AHB, CSI, DSI, CPHY, DPHY, , Spacewire, ARINC among many others. All the Verification IP includes comprehensive test suite, monitors, scoreboard etc. along with support and maintenance.

Truechip will be showcasing demo sessions, providing deep dives into the latest trends and technologies in Verification IP. The Verification IP demo will be for products like USB 4, PCIe, CXL, Ethernet, AMBA, Memory and will also showcase the NOC Silicon IP specially designed for AI and automotive applications.

Attend these sessions to gain valuable insights and practical knowledge from Truechip’s experienced engineers and thought leaders.

We invite you to join us at DAC 2024 and take advantage of the wealth of knowledge and resources Truechip has to offer. Be sure to visit our booth, attend our demo sessions, and participate in our workshop to gain a competitive edge in your verification projects.

**Register Now:**

https://www.truechip.net/dac-us-2024.php

We look forward to meeting you in San Francisco and sharing our passion for innovation in Verification IP!

For any questions or additional information, please contact us at Saurabh.agarwal@truechip.net

See you at the conference!

www.truechip.net

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Mirabilis Design at the 2024 Design Automation Conference

IC Manage at the 2024 Design Automation Conference

Ansys and NVIDIA Collaboration Will Be On Display at DAC 2024

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CircuitSutra Technologies at the 2024 Design Automation Conference

CircuitSutra Technologies at the 2024 Design Automation Conference
by Daniel Nenni on 06-17-2024 at 4:00 pm
Categories: CircuitSutra, Events, Semiconductor Services

DAC 2024 Banner

The Design Automation Conference (DAC) is a premier event that focuses on the design and automation of electronic systems. It is an annual conference that has been held since 1964, making it one of the longest-running and most established events in the field of electronic design automation (EDA).

DAC offers outstanding training, education, exhibits and superb networking opportunities for designers, researchers, tool developers and vendors. The conference is sponsored by the Association for Computing Machinery (ACM) and the Institute of Electrical and Electronics Engineers (IEEE) and is supported by ACM’s Special Interest Group on Design Automation (SIGDA) and IEEE’s Council on Electronic Design Automation (CEDA).

CircuitSutra is one of the many companies supporting this industry-leading event.

CircuitSutra is in the business of developing fast simulation models of the semiconductor chips, SoC, IP, CPU & systems at a higher abstraction level using high level languages – SystemC, C++, Python. Its mission is to accelerate the adoption of advanced shift-left methodologies in the semiconductor industry.

CircuitSutra provides SoC Modelling Services, by setting up a world class modelling team to work as the extension of the customer;s team, either remotely or onsite at the customer;s office. It provides highly specialised SystemC training, which goes beyond the language teaching and covers the modelling techniques for specific abstraction levels. It also provides re-usable modelling methodology that helps the customers to get started quickly with their SystemC endeavours.

Traditional RTL-GDS flow is not sufficient to design the complex and powerful chips of today, and lots of design activities are being performed at an abstraction level above RTL. CircuitSutra augments RTL-GDS SoC design flow with SystemC / C++ based Shift-Left ESL methodologies to perform: HW-SW codesign, Pre-silicon firmware development through Virtual Prototypes, Architecture Analysis & Optimization,  High Level Synthesis.

At the higher abstraction level, simulation speed is very fast compared to the RTL. It is feasible to simulate the complete SoC or even the electronic system, together with the software.  The higher simulation speed is achieved by deploying the concepts like interface abstraction, timing abstraction and functionality abstraction. Interface abstraction is achieved by implementing the functionality at transaction level instead of pin level. For the SoC bus there is a standard TLM2.0, however for the other interfaces – LPDDR, HBM, UCIe, CAN, PCI, Ethernet etc.., the custom TLM has to be defined. Timing abstraction is achieved by removing the clocks and implementing the functionality in the loosely timed or untimed fashion. For every specific use case of the models, it has  to be carefully  analysed what part of the functionality is required to be implemented and what part need not be implemented. For example for the embedded software use case, we model only that much functionality which is visible to the software

Serving the industry since 2005, CircuitSutra is recognized as the de facto leader in SystemC modelling in India, and has now set up a team in Santa Clara to support the customers in North America. CircuitSutra started the India SystemC User Group conference in India in 2012, which was later merged with DVCon India. CircuitSutra was awarded by Accellera design systems to drive the standards in the Indian ecosystem. It is a highly focussed company with 100% focus on SystemC based shift-left methodologies, and having in-depth understanding of the domain.

Circuitutra invites you to meet them on the DAC exhibit floor booth#1328, and to attend their talk at the exhibit forum. You can contact CircuitSutra here to schedule a meeting.

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RAAAM Memory Technologies ay the 2024 Design Automation Conference

Primarius Technologies at the 2024 Design Automation Conference

Agnisys at the 2024 Design Automation Conference

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Arteris at the 2024 Design Automation Conference

Arteris at the 2024 Design Automation Conference
by Daniel Nenni on 06-17-2024 at 2:00 pm
Categories: Arteris, Events, IP

DAC 2024 Banner

Arteris, a leading provider of system IP, will exhibit at DAC 2024, June 23-27, booth #1506. The company will demonstrate its latest technology including network-on-chip interconnect IP and SoC integration automation solutions. The products highlighted include CSRCompiler, Ncore Cache Coherent NoC IP and FlexNoC 5 interconnect IP.

Arteris recently released enhancements to CSRCompiler, a vital software solution in their system-on-chip (SoC) integration automation strategy that also includes Magillem Registers and Magillem Connectivity ( check out the recent SemiWiki blog on the Magillem suite of products here). CSRCompiler reduces manual errors and enhances productivity by streamlining the generation of hardware/software interface (HSI) outputs. CSRCompiler supports rapid, iterative designs and ensures consistency across multiple teams, automating the generation of HSI requirements from high-quality RTL and software to design verification and documentation. This software solution utilizes SystemRDL 2.0, ensuring consistency across various views and organizations without time-consuming manual scripting and editing.

CSRCompiler’s HSI database is essential for architects, RTL designers, verification engineers, software developers, and technical writers, offering centralized and customized HSI information. It compiles thousands of registers within seconds and millions within minutes. The software solution’s adaptable architecture supports various input formats into a single source, ensuring efficient production of all required formats and helping avoid errors in address map deployment. This comprehensive approach reduces the HSI development process by up to one-third.

Recently released, the updated Ncore cache coherent network-on-chip (NoC) IP ensures low latency integration of hardware accelerators into a coherent domain, delivering the speed and efficiency required for cutting-edge applications in complex SoC designs. By using Ncore, SoC design teams can save more than 50 years of engineering effort per project compared to interconnect solutions that are manually generated.

Ncore supports multiple processor IPs, including the recently announced Armv9 Cortex processor and RISC-V. Its multi-protocol support allows seamless integration of IPs connected to the same NoC fabric. It offers flexibility with CHI-E, CHI-B, ACE fully coherent agent interfaces, ACE-Lite IO-coherent interfaces, and AXI for non-coherent sub-systems.

Ncore’s configurability and scalability allow SoC designers to meet specific PPA requirements with flexible fine-tuning of the NoC architecture. It is also certified for use in ISO 26262-compliant from ASIL B to ASIL D for automotive and other mission-critical systems.

Unveiled last year, FlexNoC 5, Arteris’ latest non-coherent NoC interconnect IP, is a game-changer for SoC architecture teams. Its physical awareness eliminates the need for lengthy NoC placement and route iterations, significantly reducing development time. This technology enables 5X faster physical convergence over manual refinements, leading to improved performance, lower power consumption, and reduced die size, all of which are crucial for efficient SoC design. The interconnect enhances compatibility with other SoC IP blocks through the Arteris Magillem connectivity flow.

FlexNoC 5 supports several topologies, as well as Arm AMBA 5 protocols and IEEE 1685 IP-XACT. Additionally, it offers a Functional Safety (FuSa) option compliant with ISO 26262 standards up to ASIL D, enhancing its suitability for safety-critical applications.

Arteris invites you to visit booth #1506 at DAC 2024, to meet their experts and explore how these technologies can benefit your SoC designs. You can also catch the following DAC sessions featuring Arteris:

NoC NoC – Who’s There?
Monday, June 24 from 3:30-5:00 pm
Location: 2012, 2nd Floor

A Single Source Unified Approach to CSR Register Development Poster Presentation
Monday, June 24 from 5:00-6:00 pm
Location: Level 2 Exhibit Hall

Accelerating Timing Closure for Network on Chips (NoCs) using Physical Awareness
Wednesday, June 26 from 1:30-3:00 pm
Location: 2012, 2nd Floor

If you can’t make it DAC, Arteris invites you to learn more at www.arteris.com.

Also Read:

Arteris is Solving SoC Integration Challenges

Arteris Frames Network-On-Chip Topologies in the Car

Arteris is Unleashing Innovation by Breaking Down the Memory Wall

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EasyLogic at the 2024 Design Automation Conference

EasyLogic at the 2024 Design Automation Conference
by Daniel Nenni on 06-17-2024 at 12:00 pm
Categories: Easy-Logic, EDA, Events

DAC 2024 Banner

At booth #2430, the Easylogic technical support team will guide you through the GTECH design flow, offer in-depth product demos, engage in discussions about your ECO applications, and provide tailored recommendations.

Common feedback from customers is that the ECO flow is cumbersome and requires extensive inter-tool compatibility knowledge to function correctly.  ECO tasks typically begin with identifying the need for change, which requires equivalence checking tools to pinpoint all differences.  Formal tools can easily misinterpret certain types of RTL modifications if the environment settings are not specified perfectly. These incorrect mismatches become unnecessary ECO points, leading to unnecessary ECO patches, which increase the difficulty of the ECO task and extend the tool runtime exponentially.

Easylogic ECO’s performance goal has always been to create the smallest ECO patch logics with the least amount of user effort. Smaller patch logics help achieve timing convergence and reduce mask costs if a metal ECO is required. The simplicity of the ECO design flow offers users peace of mind, knowing the flow will work without any help of tool flow experts. Based on these two market demands, Easylogic developed an innovative ECO approach. This year at DAC, Easylogic will demonstrate its groundbreaking GTECH-based ECO optimization methodology (US patent pending), designed to elevate the functional ECO solution to the next level.

GTECH netlist, which is the mapped result of the revised RTL design before performing logic optimizations, represents the genuine RTL behavior without the ambiguity of RTL syntax interpretation. Meanwhile, GTECH sufficiently provides the netlist information for tracing the gate-level optimization results downstream, which is critical in identifying the ECO point at the gate-level netlist.

Easylogic ECO’s innovation is two-folded: a GTECH reader and a built-in equivalence checking engine, specifically engineered for ECO purpose.  The combination not only eliminates false discrepancies created by most commercial formal tools during RTL-to-RTL equivalence checking, but also creates an internal database to enable faster, broader, more precise ECO patch optimizations at the final netlist level, enhancing the robustness of its RTL-based design flow in terms of patch sizes and ease of use.

All the work mentioned above is performed under the hood.  By deploying its own application-specific equivalence checking, Easylogic ECO obtains the required design information for functional ECO optimization first-hand.  The equivalence checking deploys a unique algorithm to automatically filter out unnecessary mismatches.   Users just need to specify the proper input files, and Easylogic ECO takes care of the rest – no need to set sophisticated conditions for 3rd-party equivalence checking tool anymore.

Also Read:

ECO Demo Update from Easy-Logic

Visit with Easy-Logic at #60DAC

CEO Interview: Dr. Sean Wei of Easy-Logic

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S2C Prototyping Solutions at the 2024 Design Automation Conference

S2C Prototyping Solutions at the 2024 Design Automation Conference
by Daniel Nenni on 06-17-2024 at 10:00 am
Categories: EDA, Emulation, Prototyping, S2C EDA

DAC 2024 Banner

As the Design Automation Conference (DAC) approaches, anticipation builds for what promises to be an exceptional event in San Francisco. Attendees can look forward to perfect weather and a plethora of activities beyond the conference, such as sailing on the bay and exploring the city’s iconic landmarks.

Since its inception in 1964, DAC has established itself as a premier event in the electronic design automation (EDA) industry. Sponsored by the Association for Computing Machinery (ACM) and the Institute of Electrical and Electronics Engineers (IEEE), DAC offers a unique blend of training, education, exhibits, and networking opportunities for designers, researchers, tool developers, and vendors.

This year, all eyes will be on booth #1427, where one company will showcase its comprehensive prototyping solution. Known for its unparalleled capacity and performance, the S2C Prototyping solution promises to draw significant attention from attendees.

The latest prototyping logic system boasts a 100M ASIC Gate Capacity and 2.5X I/O Bandwidth. Its flexible I/O architecture and topology are designed to meet diverse design requirements. Moreover, it provides a high-productivity toolchain that supports the scalability of up to 128 FPGAs with the innovative Player Pro-CompileTime software.

What sets this Prototyping Solution apart are several key advantages:

Abundant Peripherals and Reference Designs: With over 90+ ready-to-use daughter cards, PCIe5 Speed Adapters, Memory DFI PHYs, and ChipLink IP solutions, S2C ensures that all aspects of system integration are covered. This extensive range simplifies the design and verification process while delivering exceptional performance.

Extensive Industry Experience: Having accumulated 20+ years of experience, S2C demonstrates a relentless commitment to innovation. Its tools are highly regarded and trusted, providing clients with the competitive edge needed to excel in a rapidly evolving market.

Unmatched Scalability: The integration of the newest compile, runtime, and debugging software suite, PlayerPro, allows for design scales up to an incredible 12.8B gates! This scalability ensures that even the most complex designs can be effectively managed and verified.

In comparison to other leading products, S2C’s latest prototyping solution offers superior flexibility, performance, and usability. Attendees at DAC 2024 will not want to miss the opportunity to see these capabilities in action.

We are encouraged to stop by booth #1427 to meet with the experts behind this cutting-edge Prototyping Solution. To schedule a meeting at the conference, interested parties can contact the company directly to secure a time slot. DAC 2024 promises to be an event to remember, and booth #1427 will undoubtedly be a highlight for those looking to stay at the forefront of EDA technology.

About S2C

S2C is a leading global supplier of FPGA prototyping solutions for today’s innovative SoC and ASIC designs, now with the second largest share of the global prototyping market. S2C has been successfully delivering rapid SoC prototyping solutions since 2003. With over 600 customers, including 6 of the world’s top 15 semiconductor companies, our world-class engineering team and customer-centric sales team are experts at addressing our customer’s SoC and ASIC verification needs. S2C has offices and sales representatives in the US, Europe, mainland China, Hong Kong, Korea and Japan.

Also Read:

Accelerate SoC Design: Addressing Modern Prototyping Challenges with S2C’s Comprehensive Solutions (II)

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Accelerate SoC Design: DIY, FPGA Boards & Commercial Prototyping Solutions (I)

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Keysight EDA at the 2024 Design Automation Conference

Keysight EDA at the 2024 Design Automation Conference
by Daniel Payne on 06-17-2024 at 8:00 am
Categories: EDA, Keysight EDA

DAC 2024 Banner

DAC starts June 24th and I can already feel the buzz of excitement building up as I receive updates from EDA vendors like Keysight EDA. Talking with Scott Seiden, Director Strategic Marketing, Keysight EDA Portfolio, I learned that they have the largest booth on the first floor, now that’s a statement that caught my attention. This year Keysight EDA is a sponsor of “I Love DAC,” a way for anyone to freely attend – Keynotes SKYtalks, TechTalks, DAC Pavilion and Exhibitor Forum, Exhibits, Tuesday Career Development, Hands-on Training, DAC Networking Events.

Here’s what to expect from Keysight EDA at DAC this year as major topics:

  • Engineering Lifecycle Management (ELM)
  • RF/uW Design and Simulation
  • HPC and Workflow Automation

Niels Faché, VP & GM, Keysight EDA will be speaking at two events:

  • Pavilion Panel Session, “Best of Both Worlds: Bridging the Gaps in Engineering Software for Semiconductors and Systems”, Monday, June 24
  • SKYTalk, “New EDA Methodologies are Transforming Engineering Lifecycle Management”, Tuesday, June 25

Simon Rance, Director of Product Management and Strategy, Keysight EDA told me that at DAC they will be showing and talking about SOS for design data management, and Engineering Lifecycle Management (ELM) HUB. With these tools it’s all about managing all of the pieces: IP, knowledge of an IC design, integrating IP blocks, bill-of-materials, traceability, and optimizing workflows from design concept to Tapeout including RTL/IP/ and security signoff, including TSMC flows. Expect an ELM new product introduction at the DAC event, stay tuned.

Daren McClearnon, Product Manager, Keysight EDA shared how they want to elevate your design intelligence by providing three key capabilities in their tools for enterprise EDA:

  • Open and interoperable – OpenAccess, Python-based Aps
  • Tools for high-frequency and high-speed – 3D, RF, UCIe-based support
  • AI-ready platforms – support multi-vendor flows, global optimization

Here’s a diagram of these capabilities:

The suite of Keysight EDA tools shown in the middle of the diagram are for:

Daren explained how these tools are used in open and interoperable design flows with tools from Cadence and Synopsys, plus the recent addition of a Python-based API.  ELM enables co-design, co-optimization and parameterization to be used. They also have a Chiplet PHY Designer to help you model and analyze chiplet interconnect from D2D to D2D PHY at a system level.

Engineers can do electromagnetics plus thermal analysis using the RFPro Circuit tool, starting a design in Virtuoso and interoperating.

Three Keysight EDA specialists will also have engineering track poster presentations at DAC:

  • Back End Design, “Accelerate RF Board BOM Simulation with ADS Design Automation”, by Zhen Zhan, Senior Applications Engineer Scientist
  • Front End Design, “Overcoming Collaboration Hurdles in High-Tech Product Development with Keysight Tool on Azure Infrastructure,” by Amit Varde, Director of Strategy and Solutions
  • Back End Design, “True-Hybrid SaaS Cloud Architectures for EDA Workloads”, by Nupur Bhonge, Senior Solutions Engineer

To get an overview of what Keysight EDA is all about, you should stop by booth #1501 and listen to the theatre presentation, Monday through Wednesday, June 24-26, and stick around to win a prize. Keysight’s customers and partners will also be presenting in the booth theater. Check out the schedule.

Summary

Keysight EDA is attending DAC in 2024 with an expanded presence, so you likely will have to send more than one person to find out what they are up to this year. I plan to stop by booth #1501 and blog about them at DAC, so look for my daily tweets with #61DAC. You can also visit the DAC landing page at Keysight EDA.

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