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Non-EUV Exposures in EUV Lithography Systems Provide the Floor for Stochastic Defects in EUV Lithography

Non-EUV Exposures in EUV Lithography Systems Provide the Floor for Stochastic Defects in EUV Lithography
by Fred Chen on 01-18-2024 at 10:00 am

Defocus flare (small)

EUV lithography is a complicated process with many factors affecting the production of the final image. The EUV light itself doesn’t directly generate the images, but acts through secondary electrons which are released as a result of ionization by incoming EUV photons. Consequently, we need to be aware of the fluctuations of the electron number density as well as the scattering of electrons, leading to blur [1,2].

In fact, these secondary electrons need not be coming from the direct EUV absorption in the resist either. Secondary electrons can come from absorption underneath the resist, which include a certain amount of defocus. Moreover, there is an EUV-induced plasma in the hydrogen ambient above the resist [3]. This plasma can be a source of hydrogen ions, electrons, as well as vacuum ultraviolet (VUV) radiation [4,5]. The VUV radiation, the electrons and even the ions constitute separate blanket resist exposure sources. These outside sources of secondary electrons and other non-EUV radiation all basically lead to non-EUV exposures of resists in EUV lithography systems.

Defocused images have reduced differences between maximum and minimum dose levels, and also add an offset to the minimum dose level (Figure 1). Thus, when incorporated with the EUV-electron dose profile, the overall image is more sensitive to stochastic fluctuations, since the defocused doses are everywhere closer to the printing threshold. The blanket exposures from the EUV-induced plasma further increase sensitivity to stochastic fluctuations at the minimum dose regions.

Figure 1. Defocus reduces the peak-valley difference and adds an offset to the minimum dose level. This tends to increase vulnerability to stochastic fluctuations.

Thus, stochastic defect levels are expected to be worse when including the contributions from these non-EUV sources. The effect is equivalent to adding a reduced incident EUV dose and adding an extra background electron dose.

Figure 2. 30 nm pitch, 30 mJ/cm2 absorbed, 3 nm blur, without non-EUV sources. Pixel-based smoothing (rolling average of 3×3 0.6 nm x 0.6 nm pixels) is applied. Numbers plotted are electrons per 0.6 nm x 0.6 nm pixel.

Figure 3. 30 nm pitch, 40 mJ/cm2 absorbed, 3 nm blur, 33 e/nm^2 from non-EUV sources. Pixel-based smoothing (rolling average of 3×3 0.6 nm x 0.6 nm pixels) is applied. Numbers plotted are electrons per 0.6 nm x 0.6 nm pixel.

Figures 2 and 3 show that including non-EUV exposure sources can lead to prohibitive stochastic defects, regardless of where the printing threshold is set in the resist development process. In particular, the nominally unexposed regions are more vulnerable to the non-EUV exposure sources. The nominally exposed regions, on the other hand, are more sensitive to the dose levels and blur. The non-EUV exposure sources therefore contribute to providing a floor for stochastic defect density.

Thus, it is necessary to include the electrons emitted from underneath the resist as well as the radiation from the EUV-induced plasma as exposure sources in EUV lithography systems.

References

[1] P. Theofanis et al., Proc. SPIE 11323, 113230I (2020).

[2] Z. Belete et al., J. Micro/Nanopattern. Mater. Metrol. 20, 014801 (2021).

[3] J. Beckers et al., Appl. Sci. 9, 2827 (2019).

[4] P. De Schepper et al., J. Micro/Nanolith. MEMS MOEMS 13, 023006 (2014).

[5] P. De Schepper et al., Proc. SPIE 9428, 94280C (2015).

This article first appeared in LinkedIn Pulse: Non-EUV Exposures in EUV Lithography Systems Provide the Floor for Stochastic Defects in EUV Lithography

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Transformative Year for Sondrel

Transformative Year for Sondrel
by Daniel Nenni on 01-18-2024 at 6:00 am

Happy,New,Year,2023,,Keep,Fighting,Together,,Silhouette,Of,2023

This is our third year working with Sondrel and it has been a great experience. I have always been fascinated with the ASIC business and put a full chapter about it in our first book “Fabless: The Transformation of the Semiconductor industry.” Companies like Sondrel enabled our move to the fabless model and now they are enabling systems companies in the transformation to being fabless system companies who own their silicon.

If you have ever walked the exhibits at CES you will see ASIC companies at work bringing ideas to silicon to systems, absolutely.

Founded in 2002, Sondrel  provides a full turnkey ASIC service from architecture through silicon supply using the most advanced tools, IP, process technology, and packaging. This is the low risk way to competitive electronic products for companies big and small. Sondrel is 150+ engineer strong with hundreds of tape-outs under their belts across a wide of market segments.

The folks at Sondrel posted a bit of a brag last month but it is well deserved. The ASIC business is a crucial part of the semiconductor ecosystem and with 21 years of experience they are one to watch:

We have had a transformative year in 2023 now that we are a listed company on the London Stock Exchange (LON:SND). This has enabled us to expand our global reach and forge new partnerships to support our ambitious growth plans. Here are just a few of the many highlights of 2023:

  • Prototypes of the silicon for each of our three major ASIC chip projects have been delivered to the customers and are now progressing through validation and qualification to production.
  • The first of these, a next-generation AI chip from a leading semiconductor company, has already moved into production. Receipt of the production order was a significant milestone for Sondrel and demonstrated the company’s ability to deliver high-performance, complex IC designs.
  • We have continued to constantly innovate with our own methodologies for design and verification for these advanced nodes, which is why our customers continue to engage with us in the most complex designs and advanced nodes down to 3nm. For example, we were part of the engineering team that taped out a 5nm design for a network chip of over 600mm2.
  • We are a Founding Member of Arm Total Design Ecosystem, a collaborative initiative that brings together leading semiconductor companies, design houses, and software developers to accelerate the development and deployment of powerful Arm processors. This will enable us to create ultra-complex ASIC solutions for exciting and rapidly growing applications such as Artificial Intelligence (AI), Machine Learning (ML) and Edge computing.
  • North America has been a focus for significant investment in our US sales organisation, increasing the headcount and opening an office in Santa Clara, CA. As a result, we have just received an order with a new customer in Silicon Valley with several more, new customers in negotiations for our turnkey design and supply service.
  • Our innovative Architecting the Future approach to design with its set of IP frameworks enabled us to close new contracts as customers can see how it reduces risks and speeds time to market. Having two of the SFA frameworks specifically designed for automotive and ISO26262 compliance, enabled us to engage with several exciting new customers in this area.
  • Reflecting continued strong customer demand, our graduate hiring programme has been enlarged for 2024.  We are looking forward to supporting the growth in the semiconductor communities in the UK, Morocco and India, and welcoming these new members to our team.
Looking Ahead

Sondrel is committed to providing its customers with the best possible IC design and manufacturing services. The company’s focus on innovation and its commitment to customer service will ensure that it continues to be a leader in the industry.” Graham Curren, Sondrel’s Founder and CEO.

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Mastering Mixed-Signal Verification with Siemens Symphony Platform

Mastering Mixed-Signal Verification with Siemens Symphony Platform
by Daniel Payne on 01-17-2024 at 10:00 am

verification platform min

Digital design and verification is well understood by EDA vendors and IC designers, however mixed-signal design and verification is more challenging, because the continuous nature of analog signals requires more compute resources and specialized design skills. Siemens EDA has a unique offering in what they call Symphony, as it connects the most popular commercial digital simulators to their Analog Fast SPICE (AFS) circuit simulator to enable mixed-signal simulation quickly and accurately. I attended a webinar on Symphony last month and describe my findings in this blog. If you missed it, you can now view the webinar on-demand:  Symphony for Mixed-Signal Verification.

Symphony is a mixed signal simulator that fits into Siemens EDA Custom IC Verification platform consisting of a design environment, characterization suite, and IP validation.

Symphony

Mixed-signal design accounts for 85% of IC design starts today, per IBS research, and example product categories include: 5G, automotive, AI, HPC, IoT. SPICE circuit simulators provide the highest simulation accuracy at the transistor-level, yet the run times are long. Digital simulators are fast and high capacity, but don’t account for analog. Mixed-signal simulation combines high precision analog blocks with digital blocks, enabling verification.

Speed vs Accuracy

In mixed-signal verification it’s important to detect top-level connectivity specification errors, find electrical behavior errors, and to ultimately verify that performance metrics were met. Mixed-signal designers want verification tools that have golden SPICE accuracy, are easy to use and setup, enable debug and coverage goals, and that reuse verification infrastructure.

The Symphony platform from Siemens EDA uses AFS XT as the analog solver, is scalable up to 16 cores, supports post-layout simulations, and offers advanced verification and debug. First announced 5 years ago, Symphony continues to grow in popularity with over 100+ customers to date. Symphony benchmarks well versus competitors, showing speed improvements of 2X to 8X for mixed-signal circuits like: HF oscillator, PLL, SerDes, Video TxRx, audio ADC and CMOS image sensors.

All the major foundries have certified the silicon accuracy of AFS across process nodes from 0.5u to 2nm: TSMC, ST, Samsung, Intel, Global Foundries, UMC. Symphony works with digital simulators that model VHDL, Verilog and System Verilog: Questa, VCS, Incisive, Xcelium. Engineers can simulate Symphony using batch mode, command line or interactively with a GUI.

When combing a digital HDL netlist to an analog netlist requires a Boundary Element (BE) for unidirectional or bi-directional connections, and with Symphony the BEs are built-in and can be parameterized, so engineers are not writing any code. Analog signals can be accessed in Verilog or System Verilog modules using analog access functions. Hi-Z states are also detected during mixed-signal simulation.

Simulations with Symphony can have a snapshot taken, then restored for subsequent simulations, saving your team valuable simulation resources. To improve debugging there are features in Symphony to browse all the BEs and even control simulation using Tcl code interactively.

NVIDIA shared at the 2018 Siemens user conference on how they used Symphony to perform mixed-signal verification of a high-speed GPU interface PHY, seeing simulation speed improvements between 2X and 12X from previous tools. Invensense reported that Symphony did noise simulation for a multi-slope ADC with a speedup of 2X to 5X compared to other simulators. Analog Value presented at DVCon 2021 how they did an ADC mixed-mode simulation with Monte Carlo results using 6,590 fewer simulations than brute-force.

The final part of the webinar was a live demo from Mina Zaki of Siemens EDA, first using the command line with a digital on top netlist, then another example with analog on top. The Solido Waveform Analyzer results were shown for a PLL example.

PLL example

In the third demo example they showed how BE values could be changed from 2.6V to 1.2V to get the proper simulation results.

Summary

Yes, mixed-signal design and verification is a difficult engineering task, yet with the right tool environment like Symphony and the ability to choose your preferred digital simulator running with AFS, it looks like Siemens EDA has an attractive offer. Their simulation technology is time-tested over the past five years, and has plenty of tier-one adopters, so why not give it a try to improve your mixed-signal turnaround times.

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IEDM 2023 – Imec CFET

IEDM 2023 – Imec CFET
by Scotten Jones on 01-17-2024 at 6:00 am

29 1 Wed Horiguchi 3 final Page 04

At IEDM 2023, Naoto Horiguchi presented on CFETs and Middle of Line integration. I had a chance to speak with Naoto about this work and this write up is based on his presentation at IEDM and our follow up discussion. I always enjoy talking to Naoto, he is one of the leaders in logic technology development, explains the technology in an easy-to-understand way and is responsive and easy to work with.

Why Do We Need CFETs

As CMOS scaling has transitioned from purely pitch based scaling to pitch plus track-based scaling, fin depopulation has become necessary, see figure 1. Each time you reduce the number of fins performance is reduced.

Figure 1. Standard Cell Scaling

By moving from FinFEts to stacked Horizontal NanoSheets (HNS) performance can be improved/recovered by wider nanosheets stacks and stacking multiple nanosheets vertically, see figure 2.

Figure 2. Nanosheet Advantage

But as we have seen with FinFETs nanosheet scaling eventually leads to reduced performance, see figure 3.

Figure 3. Nanosheet Scaling Limitations

CFETs (Complementary FET) stack the nFET and pFET, see figure 4.

Figure 4. CFET

CFETs once again reset the scaling constraints because the nFET and pFET are stacked and the n-p spacing between the devices becomes vertical instead of horizontal, this enables wider sheets, see figure 5.

Figure 5. CFET Improved Scaling

Figure 6 presents a comparison of HNS and CFET performance versus cell height highlighting the CFET advantage.

Figure 6. HNS vs CFET Performance Versus Cell Height
Monolithic Versus Sequential CFET

There are two fundamentally different approaches to CFET fabrication. In a monolithic flow the CFETs are fabricated on a wafer in a continuous process flow. In a sequential flow the bottom device is fabricated on one wafer, then a second wafer is bonded to the first wafer and the top device is fabricated in the second wafer.

In a sequential flow a bonding dielectric is present between the two devices, see figure 7.

Figure 7. Monolithic Versus Sequential CFET

Because of the bonding dielectric the structure is taller and has higher capacitance degrading performance, see figure 8.

Figure 8. Monolithic/Sequential CFET Performance Comparison

Sequential CFETs are more expensive to fabricate than monolithic CFETs and between that and the performance degradation, it appears the industry is focused on monolithic CFETs.

Monolithic CFET Processing

The monolithic CFET process is illustrated in figure 9.

Figure 9. Monolithic CFET Process Flow

The steps in bold are particularly challenging:

  • Horizontal Nanosheet Stacks (fins) are already high aspect ratio, then in order to make a CFET you stack the nFET and pFET stacks on top of each other with a relatively thick layer in between more than doubling the height.
  • The gate formation is also high aspect ratio as described on the previous point.
  • The epitaxial source/drains must be vertically isolated from each other.
  • Not explicitly called out, the bottom device source/drain is fabricated and then the top device top source/drain is fabricated. The thermal processing of the top device and subsequent steps must be done at low enough temperatures to not degrade the bottom device.

One particularly interesting part of this presentation was the Middle Dielectric Isolation (MDI) part, I hadn’t seen this issue before. The MDI proves inner spacer and Work Function Material (WFM) patterning.

Figure 10 illustrates the MDI effect on inner spacer formation (left side) and WFM patterning (right side).

Figure 10. Middle Dielectric Isolation Impact

Figure 11 illustrates the MDI integration flow.

Figure 11. MDI Integration Flow

By integrating MDI the vertical spacing between the nFET and pFET can be increased without impacting the inner spacer formation.

As mentioned previously the bottom device source/drain is fabricated and then the top device source/drain is fabricated. After formation of the bottom source/drain, an isolation dielectric is deposited and etched back to expose the top device for source/drain epitaxial formation. The isolation etch back has to be controlled with the MDI height, see figure 12.

Figure 12. MDI for Vertical Edge Placement Alignment

 In order to minimize thermal degradation of device performance new WFM options with dipole first processing and no anneal and low temperature inter layer formation processes are needed, see figure 13.

Figure 13. Low Temperature Gate Stack Options

Low temperature source/drain growth and low temperature silicides for contact formation are also needed, see figure 14.

Figure 14. Low Temperature Source/Drain and Contact Options

The low temperature silicide will be particularly important for backside direct contact to the bottom device. CFET interconnect requires contacts to the bottom and top device and with the advent of backside power delivery the top device will be contacted from the front side interconnect stack and the bottom device will be contacted from the backside. Molybdenum (Mo) and Niobium (Nb) are promising for pFET and Scandium (Sc) is promising for the nFET, although Sc is hard to deposit with ALD.

Backside and Middle of Line Interconnect

As I have written about previously here Back Side Power Delivery Network (BSPDN) is expected to be introduce this year by Intel and by Samsung and TSMC in 2026. Splitting interconnect into frontside signal connections and backside power connections reduces IR drop (power loss) by an order of magnitude, see figure 15.

Figure 15. BSPDN Reduction in IR Drop

BSPDN also improves track scaling supporting a reduction from a 6-track to 5-track cell, see figure 16.

Figure 16. BSPDN Track Scaling

 The integration of BSPDN with CFET can provide a 20% to 40% power reduction versus Horizontal stacked NanoSheets (HNS), see figure 17.

Figure 17. CFET with BSPDN

In order to go beyond a 5-track cell to a 4-track cell interconnect challenges must be overcome, see figure 18.

Figure 18. 4-track Call Interconnect Challenges

 Vertical-Horizontal-Vertical layout with additional Middle of Line (MOL) layers can enable 4-track cells, see figure 19.

Figure 19. VHV Routing and Second MOL Layer

I have previously written about Imec’s work in this area here so I will not repeat that information.

I asked Naoto what it would take to go beyond a 4-track cell to a 3-track cell, he replied that Imec is working on that optimization now, that it may require addition MOL layers and possibly a top to bottom connection next to the device that would impact standard cell layout.

I also asked Naoto when he thought we might see CFETs implemented and he said possibly the A10 logic generation or A7 generation.

Authors note, Intel, Samsung, and TSMC all published work on CFETs at IEDM this year and both Intel and TSMC have technology option maps showing FinFETs giving way to HNS and then CFETs.

Conclusion

Imec continues to show excellent progress on the development of CFETs as a next generation option after HNS. In this work device integration options as well as BSPDN and MOL options have all been described.

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WEBINAR: Mastering DC-DC Converters: Your Guide to Better Hardware

WEBINAR: Mastering DC-DC Converters: Your Guide to Better Hardware
by Daniel Nenni on 01-16-2024 at 10:00 am

Webinar (2)

Renie Ananthakumar, Principal Engineer at TenXer Labs., invites System Design Engineers globally to a webinar that’s all about practical insights—From Bench to Board: A Comprehensive Guide to DC-DC Converter Selection and Remote Testing.

See the Replay Here

In this session, we are breaking down the complexity of DC-DC converters. Learn the essentials, like how to choose the right one considering efficiency, voltage ranges, form factor, noise, and why reference designs matter. It’s not just theory; we’re throwing in real-world applications to make it stick. Facing hurdles in hardware evaluations? The session has got you covered.

Discover strategies to manage budget limitations, procurement timelines, and the need for expert guidance. We are not just talking about problems; we are talking about solutions. Ever wondered about remote test setups? We will spill the beans on how these setups can fast track your evaluations, providing step by-step guidance. It’s like having your own hardware lab accessible from anywhere.

But here’s the real take away—a hands-on example that ties theory to application. The goal is simple: equip you with practical knowledge to excel in DC-DC converters, testing setups, and remote evaluations.

Join us on for a straightforward journey from the bench to the board, where the focus is on your expertise. Don’t miss out—this webinar is your ticket to mastering DC-DC converters and taking your hardware game to the next level!

See the Replay Here
ABSTRACT

Explore the world of DC-DC converters with Renie Ananthakumar, Principal Engineer at TenXer Labs.

This webinar dives deep into selecting the best converter and building the essential testing environment. Gain a comprehensive understanding of crucial DC-DC converters considering factors like efficiency, voltage ranges, form factor, noise considerations and the significance of reference designs. Learn to identify and overcome obstacles such as — budget limitations, procurement timelines, and the necessity for expert guidance in seamless configuration.

Discover the power of remote test setup, to accelerate the evaluation processes, and enable step-by-step guided evaluation. Dive into a practical example bridging theory and actual application, enriching your expertise in DC-DC converters. Gain exclusive insights to excel in DC-DC converters, testing setups, and remote evaluation capabilities.

SPEAKER

Renie Ananthakumar is a seasoned hardware engineering professional with a decade-long track record in hardware system design. Renie has led the creation of many cutting-edge cloud-based remote testing environments. At TenXer Labs, Renie drives the pioneering initiative of onboarding Hardware Solution or Evaluation Kits (“EVK”) on the “LiveBench – Your Lab on Cloud” platform as a Device Under Test (DUT). The LiveBench platform helps System Designers gain access to an IC Evaluation Kit or a subsystem over the internet from anywhere in the world.

As Principal Engineer, Renie innovates to blend traditional testing methods with real-time virtual environments. Renie excels in the codification of physical hardware, revolutionizing hardware evaluations. Their forward-thinking approach merges practical experience and visionary ideas, shaping a future of seamless remote testing. Renie’s commitment to advancing hardware engineering through technology, positions him as a key influencer in hardware evaluation methodologies and innovation.

See the Replay Here
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Cryogenic Semiconductor Designs for Quantum Computing

Cryogenic Semiconductor Designs for Quantum Computing
by Kalar Rajendiran on 01-16-2024 at 6:00 am

siemens eda quantum crygogenics newsroom 1280x720

Over the last few years, there has been an increase in news about quantum computing. Much of this news coverage has been around computing supremacy, potential threats to information security and quantum cryptography. While the field of quantum computing is still in its early stages, there are several companies who have already developed quantum computers. And these companies often leverage proprietary semiconductor fabrication technologies to build chips for their quantum computers. As such, much information about their semiconductor chips is not publicly disclosed. On top of that, media coverage tends to emphasize practical applications of quantum computing rather than the underlying semiconductor technologies. Achievements like quantum supremacy demonstrations, advancements in quantum algorithms, and industry collaborations often take precedence in news coverage over semiconductor technologies. Nonetheless, quantum computing is not possible without semiconductors that are capable of operating at temperatures near absolute zero. These cryogenic semiconductors are fundamental components of quantum computing systems and a recent announcement by Siemens EDA provides some insights into what is involved in designing these cryogenic chips.

Siemens EDA is collaborating with sureCore and Semiwise to develop quantum computing ready cryogenic CMOS chips. The technologies and solutions developed through this collaboration have the potential to redefine the boundaries of high-performance computing.

Quantum Computing and Cryogenic Chips

Quantum computing relies on quantum bits or qubits, which exhibit quantum mechanical properties such as superposition and entanglement. To maintain the delicate quantum states necessary for computation, qubits must be shielded from external disturbances, such as thermal noise and electromagnetic interference. Operating at cryogenic temperatures helps mitigate these challenges and stabilizes the quantum states, reducing errors and enhancing the reliability of quantum computations. Cryogenic chips are essential for constructing control electronics, enabling the precise manipulation and measurement of qubits.

Semiwise

Semiwise specializes in the development of advanced cryogenic CMOS circuit designs, particularly focusing on technologies that operate at temperatures near absolute zero. The company’s value proposition centers on its expertise in creating cryogenic SPICE models and simulator technology using Siemens’ Analog FastSPICE (AFS) platform. Leveraging these technologies, Semiwise contributes crucial intellectual property (IP) to sureCore, paving the way for the design of CryoCMOS control chips vital for quantum computing.

sureCore

SureCore specializes in low-power memory solutions, with a primary focus on advancing energy-efficient and high-performance integrated circuits. The company’s value proposition lies in its innovative approach to designing and delivering low-power IP cores. In developing its CryoIP product line, sureCore taps into crucial IP from Semiwise. Leveraging cutting-edge technologies, such as Siemens’ Analog FastSPICE platform and Solido™ Design Environment software, SureCore is at the forefront of developing revolutionary CryoCMOS control chips designed to operate in extreme cold conditions. SureCore’s commitment to developing robust cryogenic IP cores tailored for quantum applications positions it as a key player in the race to unlock the full potential of quantum computing while emphasizing energy efficiency and performance in semiconductor design. sureCore is rapidly progressing towards its first CryoIP tapeout, leveraging GlobalFoundries’ 22FDX® PDK.

Siemens EDA

In this announced partnership, Siemens EDA is contributing crucial elements to Semiwise and sureCore to enable the development of cryogenic semiconductor designs. Siemens brings a wealth of expertise to the table, particularly in analog/mixed-signal IC design technology, a cornerstone in the intricate landscape of quantum computing systems. The company’s Analog FastSPICE platform and Solido™ Design Environment software play pivotal roles, providing advanced tools for the design, simulation, and verification of cryogenic CMOS circuits. This enables Semiwise to build accurate and reliable cryogenic transistor models. This in turn is empowering sureCore to construct accurate and reliable analog circuits, standard cell libraries, and memory designs including SRAM, register files, and ROM.

Summary

The collaboration between Siemens, sureCore, and Semiwise marks a significant step forward in the quest for practical quantum computing. By developing cryogenic semiconductor designs capable of operating at near absolute zero temperatures, the partnership aims to overcome critical challenges in realizing the full potential of quantum computing. The technologies developed through this collaboration could reshape the landscape of quantum computing capabilities, opening doors to a broader base of innovators for unprecedented advancements in various industries.

For more information, visit

Analog FastSPICE Platform and Solido Design Environment

Semiwise

sureCore

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How Disruptive will Chiplets be for Intel and TSMC?

How Disruptive will Chiplets be for Intel and TSMC?
by Daniel Nenni on 01-15-2024 at 10:00 am

UCIe Consortium

Chiplets (die stacking) is not new. The origins are deeply rooted in the semiconductor industry and represent a modular approach to designing and manufacturing integrated circuits. The concept of chiplets has been energized as a response to the recent challenges posed by the increasing complexity of semiconductor design. Here are some well documented points about the demand for chiplets:

Complexity of Integrated Circuits (ICs): As semiconductor technology advanced, the complexity of designing and manufacturing large monolithic ICs increased. This led to challenges in terms of yield, cost, skilled resources, and time-to-market.

Moore’s Law: The semiconductor industry has been following Moore’s Law, which suggests that the number of transistors on a microchip doubles approximately every two years. This relentless scaling of transistor density poses challenges for traditional monolithic designs.

Diverse Applications: Different applications require specialized components and features. Instead of creating a monolithic chip that tries to cater to all needs, chiplets allow for the creation of specialized components that can be combined in a mix-and-match fashion.

Cost and Time-to-Market Considerations: Developing a new semiconductor process technology is an expensive and time-consuming endeavor. Chiplets provide a way to leverage existing mature processes for certain components while focusing on innovation for specific functionalities. Chiplets also aid in the ramping of new process technologies since the die sizes and complexity are a fraction of a monolithic chip thus easing manufacturing and yield.

Interconnect Challenges: Traditional monolithic designs faced challenges in terms of interconnectivity as the distance between components increased. Chiplets allow for improved modularity and ease of interconnectivity.

Heterogeneous Integration: Chiplets enable the integration of different technologies, materials, and functionalities on a single package. This approach, known as heterogeneous integration, facilitates the combination of diverse components to achieve better overall performance.

Industry Collaboration: The development of chiplets often involves collaboration between different semiconductor companies and industry players. Standardization efforts, such as those led by organizations like the Universal Chiplet Interconnect Express Consortium (UCIe) for chiplet integration.

Bottom line: Chiplets emerged as a solution to address the challenges posed by the increasing complexity, cost, time-to-market, and staffing pressures in the semiconductor industry. The modular and flexible nature of chiplet-based designs allows for more efficient and customizable integration of chips, contributing to advancements in semiconductor technology, not to mention the ability to multi source die.

Intel

Intel really has capitalized on chiplets which is key to their IDM 2.0 strategy.

There are two major points:

Intel will use chiplets to deliver 5 process nodes in 4 years which is a critical milestone in the IEDM 2.0 strategy (Intel 7, 4, 3, 20A, 18A).

Intel developed the Intel 4 process for internal products using chiplets. Intel developed CPU chiplets which is much easier to do than the historically monolithic CPU chips. Chiplets can be used to ramp a process much quicker and Intel can claim success without having to do a full process for complex CPUs or GPUs. Intel can then release a new process node (Intel 3) for foundry customers which can design monolithic or chiplet based chips. Intel is also doing this for 20A and 18A thus the 5 process nodes in 4 years milestone. This accomplishment is debatable of course but I see no reason to.

Intel will use chiplets in order to outsource manufacturing (TSMC) when business dictates.

Intel signed a historical outsourcing agreement with TSMC for chiplets. This is a clear proof of concept to get us back to the multi sourcing foundry business model that we enjoyed up until the FinFET era. I do not know if Intel will continue to use TSMC beyond the N3 node but the point has been made. We are no longer bound by a single source for chip manufacturing.

Intel can use this proof of concept (using chiplets from multiple foundries and packaging them up) for foundry business opportunities where customers want the freedom of multiple foundries. Intel is the first company to do this.

TSMC

There are two major points:

Using chiplets customers can theoretically multi source where their die comes from. Last I heard TSMC would not package die from other foundries but if a whale like Nvidia asked them to I’m sure they would.

Chiplets will challenge TSMC and TSMC is always up for a challenge because with challenge comes innovation.

TSMC quickly responded to chiplets with their 3D Fabric comprehensive family of 3D Silicon Stacking and Advanced Packaging Technologies. The greatest challenge for chiplets today is the supporting ecosystem and that is what TSMC is all about, ecosystem.

Back to the original question “How Disruptive will Chiplets be for Intel and TSMC?” Very much so. We are in the beginning of a semiconductor manufacturing disruption that we have not seen since FinFETs. All pure-play and IDM foundries now have the opportunity to get a piece of the chips that the world depends on, absolutely.

Also Read:

2024 Big Race is TSMC N2 and Intel 18A

IEDM: What Comes After Silicon?

IEDM: TSMC Ongoing Research on a CFET Process

IEDM Buzz – Intel Previews New Vertical Transistor Scaling Innovation


How Codasip Unleashed CHERI and Created a Paradigm Shift for Secured Innovation

How Codasip Unleashed CHERI and Created a Paradigm Shift for Secured Innovation
by Mike Gianfagna on 01-15-2024 at 6:00 am

How Codasip Unleashed CHERI and Created a Paradigm Shift for Secured Innovation

At the recent RISC-V Summit, Dr. Ron Black, CEO of Codasip unveiled a significant new capability to create a more secure environment for innovation. Rather than re-writing trillions of lines of code to solve the security problem, Ron described a much more practical approach. One that brought a research topic into mainstream deployment. The results could have far-reaching impact. You can learn about the magnitude of the data security problem and the overall approach Codasip is taking in this RISC-V summary piece. In this discussion, I will dig into some of the details that allowed this innovation to happen. The standard that was developed in the lab, and the road to production that Codasip provided.  Read on to learn how Codasip unleashed CHERI and created a paradigm shift for secure innovation.

The Beginnings of CHERI

CHERI (Capability Hardware Enhanced RISC Instructions) is a joint research project of SRI International and the University of Cambridge to revisit fundamental design choices in hardware and software to dramatically improve system security. CHERI has been supported by DARPA programs since 2010, as well as other DARPA research and transition funding.

CHERI extends conventional hardware Instruction-Set Architectures (ISAs) with new architectural features to enable fine-grained memory protection and highly scalable software compartmentalization. The CHERI memory-protection features allow historically memory-unsafe programming languages such as C and C++ to be adapted to provide strong, compatible, and efficient protection against many currently widely exploited vulnerabilities. This ability to retro-fit existing systems with higher security is what makes CHERI so attractive – no need for a major re-write to enhance security.

CHERI is a hybrid capability architecture in that it can blend architectural capabilities with conventional MMU-based architectures and microarchitectures, and with conventional software stacks based on virtual memory and C/C++. This approach allows incremental deployment within existing software ecosystems, which the developers of CHERI have demonstrated through extensive hardware and software prototyping.

CHERI concepts were developed first as a modification to 64-bit MIPS and 64-bit ARMv8-A. All of these projects are of a research nature, with the goal of developing a proof-of-concept. While these efforts represent important steps to a commercial solution to the data security problem, a true “industrial strength” solution was out of reach – until recently.

Codasip Delivers a Production Implementation of CHERI for the RISC-V ISA

In mid-October, 2023, Codasip announced the 700 RISC-V processor family, expanding its offering beyond embedded processor IP to stand-alone application processors. In its own words, “bringing the world of Custom Compute to everyone.” The 700 family is a configurable and customizable set of RISC-V baseline processors. It is intended to complement Codasip’s embedded cores by offering a different starting point to accommodate the need for higher performance. And Codasip Studio delivers a streamlined design process that unleashes the potential of the 700 family.

It was against this backdrop that Codasip fundamentally changed the deployment vector for CHERI. Using Codasip Studio, built-in fine-grained memory protection was added to the 700 processor family by extending the RISC-V ISA with CHERI-based custom instructions. To enable the use of these instructions, Codasip also delivered the software environment to take advantage of CHERI technology, bringing a full software development flow to add memory protection.

And because CHERI technology can be applied selectively to critical functions, it is possible to enhance the security of existing products with a small effort, often through a simple code recompilation. This allows the huge pool of existing C/C++ software to be leveraged to create more secure systems cost-effectively. Codasip demonstrated the new CHERI-based security capability at the recent RISC-V Summit, and lead customers will get early access to the core with CHERI capabilities in the second half of 2024.

These developments hold the promise to fundamentally change the landscape regarding data security. This is clearly one to watch. There are places to learn more about this important development. Before I get to those, I’d like to cite a few examples of how CHERI could change data security. At his RISC-V keynote, Ron Black detailed some epic security breaches that have occurred over the years. You may remember some, or all of these:

  • The Heartbleed bug: Introduced in software in 2012 and disclosed in 2014. Huge impact. more than 90,000 devices still not patched in 2019. Estimated cost is over $500 million. This is one of the worst software vulnerabilities of all time.
  • BMW Telematics Control Unit bugs: In 2017, Tencent’s Keen Security found a memory corruption vulnerability in the Technical Control Unit TCU firmware. The researchers could bypass signature protection and gain root access to the TCU via remote code execution​. They could then send crafted Controller Area Network (CAN bus) messages to affect control of other electronic control units in the vehicle.
  • Netgear router hack: In a recent competition organized by the Zero Day Initiative, Claroty’s Team 82 found and exploited a vulnerability in the Netgear Nighthawk RAX30 router. The routers utilize a software protection technique called stack canaries to secure against buffer overflow attacks. The team could bypass the canary. An attacker may surveil your procedures, highjack connections, send you to malicious sites, or embed malware into your ecosystem.

The goal of this exercise was not to cause panic, but to simply point out that ALL of these vulnerabilities were preventable with Codasip CHERI technology.  And that’s why this is an important development to watch and use.

To Learn More

There is a rich library of information about CHERI here.  A press release, a technical paper, several informative blogs and the ability to request more information. I highly recommend spending some time there.  Especially of you are concerned about data security, and who isn’t?  And that’s how Codasip unleashed CHERI and created a paradigm shift for secure innovation.


Podcast EP203: A Deep Dive on the Growing Impact of Silicon Lifecycle Management with Synopsys’ Randy Fish

Podcast EP203: A Deep Dive on the Growing Impact of Silicon Lifecycle Management with Synopsys’ Randy Fish
by Daniel Nenni on 01-12-2024 at 10:00 am

Dan is joined by Randy Fish, Director of Product Line Management for the Silicon Lifecycle Management (SLM) family at Synopsys. Randy has over 30 years of experience in the EDA, IP and semiconductor industries.

In this broad view of SLM, Randy explains what is special about monitoring and optimizing embedded memories. It turns out there are a huge number of these structures in advanced designs and their performance is of critical importance.

Randy and Dan expand the discussion to include broad markets such as data center and automotive. Randy explains the breadth of the Synopsys strategy for SLM that includes many types of embedded monitoring IP, on-chip analytics and use of the cloud. The goal is to deliver optimal performance over the life of the design – an area of increasing importance.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.


2024 Outlook with Anupam Bakshi of Agnisys

2024 Outlook with Anupam Bakshi of Agnisys
by Daniel Nenni on 01-12-2024 at 6:00 am

Agnisys Company Photo

We have worked with Agnisys for the last two years and it has been a pleasure. Anupam and his team of specification automation experts have pioneered a family of products and solutions for streamlining the generation of the required files for design, software, verification, validation, and documentation for semiconductor development directly from executable specifications. This saves your IP and chip development teams time and effort many times throughout the course of a project. Whenever a specification changes for any reason, all output files are updated, keeping all teams in sync, absolutely.

Tell us a little bit about yourself and your company.
I’m Anupam from Agnisys, a company I formed in 2007, so it’s been 16 years here. Our vision has been to eradicate wastage of time and resources in the
chip design process. Our flagship product suite is called IDesignSpec which
is useful in compiling higher level specifications into highly optimized
code for area, for power, for verification, for firmware, and the list goes
on. The tool helps establish a single source of truth in a company that
keeps everyone in sync from the start. Over the years, we have enabled
hundreds of teams and thousands of engineers to save time and money.

What was the most exciting high point of 2023 for your company?
Its hard to say because there was so much happening in 2023, never a dull
moment! But getting requests for sequences from existing and new customers was the highlight. You see, we had a sequence product in 2019 but it was early for its times. Now we see a renewed interest in sequences thanks to PSS (An Accellera standard that Agnisys helped in creating as well).

What was the biggest challenge your company faced in 2023?
There were several, but two were significant – Power optimization and Clock
Domain Crossings in large circuits. Bigger designs can’t be created with
simple old ways, a concentrated effort has to be made to ensure that power
conformance and CDC handling.

How is your company’s work addressing this biggest challenge?
We solved the challenges by enhancing the functionality of the products.

What do you think the biggest growth area for 2024 will be, and why?
I think it will be the rampant use of AI both in helping create generic
IP/SoC and specialized AI IP/SoC.

How is your company’s work addressing this growth?
We are directly using AI in the core IDesignSpec product as well as in
ancillary areas like Chatbots for help with product usage.

What conferences did you attend in 2023 and how was the traffic?
We exhibited at DAC and almost all DVCon – in US, EU, India, China, Japan.
All were well attended and we had lots of fun. We tried to have a sponsored
event at all these shows.

Will you attend conferences in 2024? Same or more?
We will probably attended more – it’s a great place to meet customers and
show our work. Also it’s a source for new ideas and direction, not to
mention an opportunity to interact with the peers in the industry.

Final comments?
We are just as excited and enthusiastic about our products and services as
we were when we started 16 years ago. We thank our customers for standing by a young startup and seeing it grow into a key EDA player.

Also Read:

An Update on IP-XACT standard 2022

The Inconvenient Truth of Clock Domain Crossings

Can We Auto-Generate Complete RTL, SVA, UVM Testbench, C/C++ Driver Code, and Documentation for Entire IP Blocks?