For more than a decade 2D NAND has been the leading driver of lithography shrinks, for example, Samsung went from 120nm in 2003 to 16nm in 2014 with shrinks on an almost yearly basis, but the shrinks came at a price. At 16nm Self Aligned Quadruple Pattering (SAQP) was required for the most critical layers and patterning related costs… Read More
Tag: imec
Is the Future Finally Here? What a GaAs!
Back in 1983 I was working for Texas Instruments during the beginning of the push to let common electrical engineers develop their own CMOS application specific ICs (ASICs). This would eventually the be the fuel that fed the semiconductor engine to reach over $335 billion in 2015. At that time, I was a young guy and I had a rascally … Read More
Silicon Photonics – Back to the Future – Part Deux?
I cut my teeth in silicon IC design at Texas Instruments during the early 1980’s working on what would eventually become the ASIC and Fabless IC industries that enabled the explosive growth of the electronics industry over the last three decades. Of late I’ve become involved in the silicon photonics space and I am getting an incredible… Read More
SPIE – Interview with Greg Mcintyre of IMEC
One of the things I really like about major technical conferences is the opportunity to meet with people for networking and interviews. On Wednesday at the Advanced Lithography Conference I had the opportunity to interview Greg Mcinttyre, the director of advanced patterning at IMEC.
IMEC researchers are the first author on 32… Read More
ASML and IMEC EUV Progress
Day 1 of the SPIE conference featured a number of customer updates on the status of their EUV programs. On Tuesday morning we got to hear ASML’s update on their work.… Read More
5nm Chips? Yes, but When?
For any invention, technical proof of concept or prototyping happens years ahead of the invention being infused into actual products. When we talk about 5nm chip manufacturing, a test chip was already prototyped in last October, thanks to Cadence and Imec. Details about this chip can be found in a blog at Semiwiki (link is given … Read More
Coventor ASML IMEC: The last half nanometer
On Tuesday evening December 8[SUP]th[/SUP] at IEDM, Coventor held a panel discussion entitled the “The last half nanometer”. Coventor is a leading provider of simulation software used to design processes. This is my third year attending the Coventor panel discussion at IEDM and they are always excellent with very strong panels… Read More
IEDM Blogs – Part 7 – IMEC Technology Forum – Part 2
On Sunday evening December 6[SUP]th[/SUP] before IEDM, IMEC held the IMEC Technology Forum (ITF). In part 1 of this blog I discussed the introduction and the first two presentations given by An Steegen and Mark Rodder. In this blog I will discuss the final two presentations. Part 1 can be accessed here.… Read More
IEDM Blogs – Part 6 – IMEC Technology Forum – Part 1
On Sunday evening December 6[SUP]th[/SUP] before IEDM, IMEC held the IMEC Technology Forum (ITF). The ITF was held at the Belgium ambassador’s residence, a really beautiful setting for a meeting.
The ITF began with a brief welcome by the Belgium ambassador followed by a brief introduction to IMEC. IMEC is a research institute … Read More
IEDM Blogs – Part 4 – IMEC InGaAs Channel for 3D NAND
At IEDM IMEC presented “MOCVD In[SUB]1-x[/SUB]Ga[SUB]x[/SUB]As high mobility channel for 3-D NAND Memory” authored by E. Capogreco, J. G. Lisoni, A. Arreghini, A. Subirats, B. Kunert, W. Guo, T. Maurice, C.-L. Tan, R. Degraeve, K. De Meyer, G. Van den bosch, and J. Van Houdt.
On December 15[SUP]th[/SUP] I had the opportunity … Read More