I had the good fortune to be able to attend a very informative five-day photonic integrated circuit (PIC) training this last week in Santa Clara, CA. The training was organized by Erik Pennings of 7 Pennies consulting and hosted by Tektronix. Several ecosystem partners from the design automation, photonic foundries and photonic packaging and test industries presented to a full room of more than 25 trainees from 15 different companies. The mix of companies was intriguing as there was almost an equal mix of system houses and IC providers with PIC providers outweighing the electrical IC (EIC) providers 2-to-1 and at least one of the system houses that was also doing both PICs and EICs. Of the companies doing EIC design, it was roughly an equal split between IDMs and Fabless component makers.
Training content was rich and started with a general tutorial on different types of passive and active photonic components along with basic principles behind how those components work. This was followed by an overview of the different photonic material platforms being employed for each. It was quite clear that the III-V ad II-VI group materials are here to stay for lasers, optical amplifiers and photonic detectors. There is however a definite shift underway to make use of Si and Si-based materials to enable smaller, denser and in theory lower cost photonic devices. Methods for integrating light sources and amplification to these silicon-based solutions is still up for grabs with lots of competing solutions. For detectors Ge is being grown on the Si to form SiGe based detectors.
In conjunction with the move to use hybrid photonic solutions is the push to move the photonic components closer and closer to the electronics with which they communicate. The biggest impetus for this is the next jump in modulation speed per channel. Most 100G applications are using 25Gbps channel modulation with some form of higher level encoding such as QPSK to increase effective baud rates. As the industry moves to 200G and higher rates there will be a push to move the channel speed up to 50Gbps modulation rates and when that happens there will be a push to reduce or eliminate the metal RF traces on the boards between the electronics and photonics. Flip chip seems to be the method of choice to shorten these leads by using through silicon vias (TSVs) and bump technology between the electronic-based driver chips and the photonics (see picture from Luxtera). This will however will require some help from the design automation industry to put in place more robust CAD for 2.5D and 3D design and verification methodologies.
The training rounded out with hands-on sessions from design automation vendors VPI Photonics, Lumerical Solutions, PhoeniX Software and Cadence Design who covered photonic system-level design and verification through PIC design, verification and implementation. Presentations were also given by photonic MPW aggregator JePPIX, and Si-photonics foundries CEA-Leti, imec, IHP, VTT. Presentations were also given by silicon nitride foundry LioniX as well as InP foundries HHI/Fraunhofer and Smart Photonics. Advanced photonic packaging was covered by Chiral Photonicsand photonic test and measurement were covered by Tektronix and Venista. Lastly, design housesBright Photonics and VLC Photonics each spoke about their photonic design services offerings.
Other key concepts from the training included:
- Integrated photonic solutions may at first need to be sold at the system level. Disruptive change doesn’t happen at a single component level. It tends to impact the entire system which includes software and hardware infrastructure changes that must happen together. Look for these kind of changes from system suppliers that will use photonics to disrupt the current status quo.
- The advent of 100G has provided great momentum for PICs especially with 100GbE (with LR4 and ER4 requiring 4 wavelength channels) and 100Gbps coherent (DP-QPSK). The volumes for these devices will be sufficient to boot up the manufacturing infrastructure to the point that other photonics markets will become cost viable. As a result, the market for PICs is now growing at >35% / year
- MPW services & PDKs have greatly helped to jump start the market by providing a low cost way for fabless startups to prototype their ideas and create components that can be tested in the market. These prototypes have sparked the interest of the bigger players resulting in multiple acquisitions over the last two years. This in turn as motivated major production foundries to start planning for introduction of their own photonics offerings. See previous SemiWiki articles ‘A Peek Inside the Global Foundries Death Star!’ and ‘The Fabless Empire Strikes Back, Global Foundries and Cadence make moves into Integrated Photonics’.
- Package design and 2.5D/3D integration with a mixture of EIC and PIC will become crucial to enable higher speed solutions. Thermal analysis of these modules will be important as the EICs will be generating a considerable amount of heat and designers will need tools to understand and accommodate for inadvertent heating of the photonics.
All-in-all this was a very comprehensive training class that was both wide in breadth but also comprehensive in its depth. I learned a lot and would encourage anyone interested in photonics to look into future classes offered of this nature.Share this post via: