ANSYS Enters the League of 10nm Designs with TSMC

ANSYS Enters the League of 10nm Designs with TSMC
by Pawan Fangaria on 04-09-2015 at 7:00 pm

The way we are seeing technology progression these days is unprecedented. It’s just about six months ago, I had written about the intense collaboration between ANSYSand TSMCon the 16nm FinFET based design flow and TSMC certifying ANSYS tools for TSMC 16nm FF+ technology and also conferring ANSYS with “Partner of the Year” award.… Read More


Variation Alphabet Soup

Variation Alphabet Soup
by Paul McLellan on 04-04-2015 at 1:00 pm

On-chip variation (OCV) is a major issue in timing signoff, especially at low voltages or in 20/16/14nm processes. For example, the graph below shows a 20nm inverter. At 0.6V the inverter has a delay of 2 (nominalized) units. But due to on-chip variation this might be as low as 1.5 units or as high as 3 units, which is a difference from… Read More


The Apple A9 Samsung & TSMC Love Triangle

The Apple A9 Samsung & TSMC Love Triangle
by Robert Maire on 03-25-2015 at 10:00 am

The Apple A9 drama continues to play out with no certainty!
At the end of the day does it matter?
Will the winner be the loser?
A Comedy, Tragedy or Love Story?
Depends on your view…

Act I Scene I…The stage is set….

We are watching an Italian Opera of a standard love triangle….
The object of desire is the rich … Read More


2015, the Year of the Sheep…And the 16nm FPGA

2015, the Year of the Sheep…And the 16nm FPGA
by Paul McLellan on 03-10-2015 at 7:00 am

If you live in California anyway, with its large Asian population, you can’t have helped noticing that it was the Lunar New Year a couple of weeks ago, the start of the year of the sheep. A couple of days after the New Year, Xilinx announced their new families of what they now call FPGAs, 3D ICs and MPSoCs. But which the rest of us … Read More


Xilinx’s 16nm UltraScale+ FPGA is Revolutionary

Xilinx’s 16nm UltraScale+ FPGA is Revolutionary
by Luke Miller on 03-01-2015 at 7:00 am

Well a very belated Happy New Year dear reader. I must admit, it has been a very long winter and it has caused the Miller’s to rethink this vital question. “What in the world are we doing living in NY”. So we are moving, and hopefully this is my last ‘real’ winter as we headed down south. To perhaps alleviate some of the winter blues from … Read More


TSMC’s OIP: Everything You Need for 16FF+ SoCs

TSMC’s OIP: Everything You Need for 16FF+ SoCs
by Paul McLellan on 02-13-2015 at 7:00 am

Doing a modern SoC design is all about assembling IP and adding a small amount of unique IC design for differentiation (plus, usually, lots of software). If you re designing in a mature process then there is not a lot of difficulty finding IP for almost anything. But if you are designing in a process that has not yet reached high-volume… Read More


Altera Back to TSMC at 10nm? Xilinx Staying There

Altera Back to TSMC at 10nm? Xilinx Staying There
by Paul McLellan on 01-28-2015 at 7:00 am

Xilinx announced their quarterly results last week. They slightly missed their number due mainly to a decline in wireless sales. Of course Xilinx parts don’t go in the smartphones since the cost and power are too high, but they are very heavily used in basestation, backhaul etc especially in China. Xilinx’s business… Read More


Apples Versus Zebras

Apples Versus Zebras
by Scotten Jones on 01-06-2015 at 12:00 am

I have seen a couple of posts comparing the density of the Apple A8 to the Intel Core M and concluding that the TSMC 20nm process is denser than the Intel 14nm process. In one of the threads one of the posters likened this to comparing apples to oranges, I agree except I think it is even worse than that, I think it is more like comparing apples… Read More


IEDM Advanced CMOS Technology Platform Session

IEDM Advanced CMOS Technology Platform Session
by Scotten Jones on 01-01-2015 at 7:00 am

First I want recognize that IEDM once again provided all of the attendees with the proceedings as soon as we arrived at the conference, in fact the proceeding included every year of IEDM back to 1955. This is how a conference should be run! Anyone who read my blog about the SPIE Advanced Lithography Conference will know how frustrating… Read More


ANSYS Updates RedHawk for FinFET Nodes

ANSYS Updates RedHawk for FinFET Nodes
by Tom Simon on 12-30-2014 at 7:00 am

Most designers are not using FinFETs yet, however the increased transistor density and power advantages they offer are compelling. Smaller feature sizes have been a consistent driver in semiconductor technology. Eventually the market will move more and more to FinFET processes, increasingly leaving behind planar transistors.… Read More