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IEDM Advanced CMOS Technology Platform Session

IEDM Advanced CMOS Technology Platform Session
by Scotten Jones on 01-01-2015 at 7:00 am

 First I want recognize that IEDM once again provided all of the attendees with the proceedings as soon as we arrived at the conference, in fact the proceeding included every year of IEDM back to 1955. This is how a conference should be run! Anyone who read my blog about the SPIE Advanced Lithography Conference will know how frustrating I found SPIE not making the proceeding available until months after the conference. SPIE really needs to fix that! Being able to read the papers before a session and then review them again after the session is really helpful.

There were three papers in the Advanced CMOS Technology Platform session that really caught my attention this year.


First up was TSMC presenting their 16FF+ technology. The process presented this year provides a 15% speed improvement at the same power or a 30% power improvement at the same speed versus the 16FF process presented at IEDM last year. All of the critical dimensions disclosed for this process are the same as 2013 (48nm fin, 90nm gate and 64nm M1 pitches). The level of performance improvement TSMC has achieved is more in-line with what you would see for a new node and to achieve this level of improvement while maintaining the same critical dimensions is really an achievement. Unfortunately from my perspective the paper only discussed the results and didn’t provide any details on how they were achieved other than to say they focused on reducing capacitance. Still the results are impressive!


The next paper that really caught my attention was the Intel paper on their 14nm technology. Intel’s 14nm technology is the densest 16nm/14nm class process currently available with 42nm fin, 70nm gate and 52nm metal pitches. The gate pitch x metal pitch metric is 0.51x the 22nm technology, IDsat is 15% better for NMOS and 41% better for PMOS. Active power is 30% better than 22nm with 10x better tddb and less Vt variation.

Once again there wasn’t a lot of detail presented about the process but there were a few interesting disclosures:

  • The process uses solid source doping to dope under the fins. My belief is that the STI trenches between the fins are filled with doped glass that is then etched back to the bottom of the fin and then annealed to out-diffuse the dopants. I would expect both p and n doped glasses would be required. I have come up with one integration scheme that does this without additional masks but it would result in topography at the bottom of the wells. I think it is more likely one additional mask would be needed.
  • Air gaps are used on two of the interconnect layers. Data was presented for delay improvements for metal 4 – 17% and metal 6 – 14%. Interestingly my understanding is that analysis of actual Intel products in the field has found the air gaps on layers 5 and 7. During the presentation it was also disclosed that a mask is needed for each air gap. After the paper someone asked how this is done and author declined to comment. Based on cross sections and the one mask per air gap disclosure it seems likely that this is the process Intel described in 2010.
  • I was surprised when it was first disclosed that this process has 13 metal layers. Intel used 6 metal layers at 180nm (aluminum) and 130nm (copper), 7 layers at 90nm, 8 layers at 65nm and 9 layers at 44nm, 32nm and 22nm. I was expecting 10 metal layers at 14nm. I think what has happened here is that Intel has moved to SADP for critical metals layers and SADP really only produces gridded lines and spaces for a 1D layout. This has likely required additional metal layers versus previous 2D metal layers.
  • During the presentation Intel briefly displayed the pitches for all the metal layers. Unfortunately it wasn’t up long enough for me to copy down the numbers and unlike many attendees I respect the no photography rule. The pitches are also not in the paper. I have seen measured pitches on products in the field but I can’t share them yet. I will say that I saw a report on EE Times that the process has 8 layers of 52nm minim pitch metal, it actually has 5 layers of minimum pitch metal.
  • Intel has previously stated that the 14nm process wafer cost is 29% higher than the 22nm wafer cost. I have a really hard time reconciling that number with all the added masks at 14nm. First there are 8 mask layers required for the additional 4 metal layers, then 2 mask layers for the 2 air gap layers and likely 1 mask layer for the under fin doping. Then there are 1 additional cut mask for fins (2 versus 1 for 22nm), 1 cut mask each at contact and M0 and 10 cut masks for metals M1 through M5. In all I see an approximately 50% increase in both masks and process complexity.

    The final paper I wanted to comment on from the session is the IBM paper on their 14nm technology. Where Intel and TSMC produce FinFETs on bulk wafers IBM produces FinFETs on SOI. The use of SOI enables IBM to integrate eDRAM on the same wafer with only 2 masks (my estimate). eDRAM is much more area efficient for cache than SRAM and with the huge cache sizes required for processors and SOCs eDRAM can save a lot of die area. I believe the IBM eDRAM process only requires 1 mask to form the trench DRAM capacitor and 1 additional mask for a thick gate oxide for the access transistors. The IBM process definitely leads in the complexity category with 15 metal layers and the eDRAM. This process is likely targeted at IBMs internal processors used for high end servers where processor cost is really not much of a consideration. The process pitches are 42nm for fin, 80nm for gate and 64nm for metal. IBM gave the most process details of the three papers with a block level process flow, always a favorite of mine. This is a very impressive high performance process.

    Comparison and conclusions

    The following table compares the density for the three processes.

    [TABLE] align=”center” border=”1″
    | style=”width: 133px” |
    | style=”width: 120px; text-align: center” | IBM
    | style=”width: 114px; text-align: center” | Intel
    | style=”width: 108px; text-align: center” | TSMC
    | style=”width: 133px” | Gate (CPP)
    | style=”width: 120px; text-align: center” | 80nm
    | style=”width: 114px; text-align: center” | 70nm
    | style=”width: 108px; text-align: center” | 90nm
    | style=”width: 133px” | Metal
    | style=”width: 120px; text-align: center” | 64nm
    | style=”width: 114px; text-align: center” | 52nm
    | style=”width: 108px; text-align: center” | 64nm
    | style=”width: 133px” | Gate x Metal
    | style=”width: 120px; text-align: center” | 5,120nm2
    | style=”width: 114px; text-align: center” | 3,640nm2
    | style=”width: 108px; text-align: center” | 5,760nm2

    A few final observations from this session:

  • To my mind Moore’s law is alive and well not only technologically but I also believe these processes deliver cost per transistor reductions as well. For some of the foundry processes cost reduction is modest at 16nm/14nm because they maintained the same BEOL as previous generations but moving forward to 10nm I expect to see significant cost reductions with a return to full scaling.
  • Intel has the densest process when measured by the gate x metal pitch metric. What isn’t clear is how an Intel die size would compare to an IBM die size for a die with a large cache. Intel’s SRAM is 0.0588um2 whereas IBM’s eDRAM cell is 0.0174um2 providing a significant potential area saving for cache. Share this post via:

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