First I want recognize that IEDM once again provided all of the attendees with the proceedings as soon as we arrived at the conference, in fact the proceeding included every year of IEDM back to 1955. This is how a conference should be run! Anyone who read my blog about the SPIE Advanced Lithography Conference will know how frustrating I found SPIE not making the proceeding available until months after the conference. SPIE really needs to fix that! Being able to read the papers before a session and then review them again after the session is really helpful.
There were three papers in the Advanced CMOS Technology Platform session that really caught my attention this year.
First up was TSMC presenting their 16FF+ technology. The process presented this year provides a 15% speed improvement at the same power or a 30% power improvement at the same speed versus the 16FF process presented at IEDM last year. All of the critical dimensions disclosed for this process are the same as 2013 (48nm fin, 90nm gate and 64nm M1 pitches). The level of performance improvement TSMC has achieved is more in-line with what you would see for a new node and to achieve this level of improvement while maintaining the same critical dimensions is really an achievement. Unfortunately from my perspective the paper only discussed the results and didn’t provide any details on how they were achieved other than to say they focused on reducing capacitance. Still the results are impressive!
The next paper that really caught my attention was the Intel paper on their 14nm technology. Intel’s 14nm technology is the densest 16nm/14nm class process currently available with 42nm fin, 70nm gate and 52nm metal pitches. The gate pitch x metal pitch metric is 0.51x the 22nm technology, IDsat is 15% better for NMOS and 41% better for PMOS. Active power is 30% better than 22nm with 10x better tddb and less Vt variation.
Once again there wasn’t a lot of detail presented about the process but there were a few interesting disclosures:
The final paper I wanted to comment on from the session is the IBM paper on their 14nm technology. Where Intel and TSMC produce FinFETs on bulk wafers IBM produces FinFETs on SOI. The use of SOI enables IBM to integrate eDRAM on the same wafer with only 2 masks (my estimate). eDRAM is much more area efficient for cache than SRAM and with the huge cache sizes required for processors and SOCs eDRAM can save a lot of die area. I believe the IBM eDRAM process only requires 1 mask to form the trench DRAM capacitor and 1 additional mask for a thick gate oxide for the access transistors. The IBM process definitely leads in the complexity category with 15 metal layers and the eDRAM. This process is likely targeted at IBMs internal processors used for high end servers where processor cost is really not much of a consideration. The process pitches are 42nm for fin, 80nm for gate and 64nm for metal. IBM gave the most process details of the three papers with a block level process flow, always a favorite of mine. This is a very impressive high performance process.
Comparison and conclusions
The following table compares the density for the three processes.
[TABLE] align=”center” border=”1″
| style=”width: 133px” |
| style=”width: 120px; text-align: center” | IBM
| style=”width: 114px; text-align: center” | Intel
| style=”width: 108px; text-align: center” | TSMC
| style=”width: 133px” | Gate (CPP)
| style=”width: 120px; text-align: center” | 80nm
| style=”width: 114px; text-align: center” | 70nm
| style=”width: 108px; text-align: center” | 90nm
| style=”width: 133px” | Metal
| style=”width: 120px; text-align: center” | 64nm
| style=”width: 114px; text-align: center” | 52nm
| style=”width: 108px; text-align: center” | 64nm
| style=”width: 133px” | Gate x Metal
| style=”width: 120px; text-align: center” | 5,120nm2
| style=”width: 114px; text-align: center” | 3,640nm2
| style=”width: 108px; text-align: center” | 5,760nm2
A few final observations from this session: