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2015, the Year of the Sheep…And the 16nm FPGA

2015, the Year of the Sheep…And the 16nm FPGA
by Paul McLellan on 03-10-2015 at 7:00 am

 If you live in California anyway, with its large Asian population, you can’t have helped noticing that it was the Lunar New Year a couple of weeks ago, the start of the year of the sheep. A couple of days after the New Year, Xilinx announced their new families of what they now call FPGAs, 3D ICs and MPSoCs. But which the rest of us will probably still be calling FPGAs until the year of the sheep comes around again in 12 years. These form the UltraScale+ portfolio.

These new products are (or rather will be) built in TSMC’s 16FF+ process. Just like in the TSMC process names, where 16FF and 16FF+ are not at all the same process, that “+” sign after UltraScale is important. The previous UltraScale family was built in TSMC’s 20nm planar process. The 16FF+ process is FinFET (that is what the “FF” stands for) with all the well known performance and power advantages. Since TSMC’s 16nm processes share the BEOL (metal) with their 20nm process, the area savings from the previous generation are likely to be minimal.

This is really a pre-announcement since parts will not be available until Q4. As was said on the last earnings call, the parts should tapeout in Q2, a quarter later than originally planned. Of course the primary competition is Altera who are famously building their first FinFET arrays on Intel’s foundry process. But in their earnings call they said that they might switch back to TSMC for 10nm, which I can only assume means that things are not going all that well. Anyway, Xilinx is continuing to claim to be a generation ahead. They are not actually the first FinFET FPGAs, I think that Tabula actually had some parts in Intel’s 22nm FinFET process and Achronix does too, but they are not volume suppliers (and in Tabula’s case, not suppliers at all since the company is shutting down).

In addition to moving their portfolio to 16nm, Xilinx also announced two new technologies:

UltraRAM which gives you up to 432Mb of memory. This is designed to be a better solution than either distributed RAM (in the FPGA fabric) or on-die block RAM, and with much better performance and power than you can get with external RAM. Of course if you need gigabits of RAM you will need to pay the cost of going external.
 SmartConnect intelligent interconnect optimizes interconnect and matches the interconnect architecture to the performance constraints of your design. It reduces interconnect by about 50% and so leads to an overall reduction of about 20% in power and area for the overall design.

Xilinx announced 3 new families:

At the highest end is Virtex which is their 3rd generation of 3D IC, now with added 3D transistors too. These are the parts that use multiple smaller die on a silicon interposer to build huge arrays that would barely yield at all if manufactured as a single die (assuming they don’t exceed the maximum reticle size).

Next is Zynq, what they call the all-programmable SoC. They have a lot of processors, around 10, on each array: a quad-core ARM Cortex-A53, a Mali GPU, a Cortex-R5 dual-core real-time processor, a power management unit with its own processor, a security processor for key and vault management, hardware H.265 implementation, PCIe, 100G ethernet and more.

Kintex is the low end, smaller arrays intended for mid-range applications. They incorporate the UltraRAM and SmartConnect technologies

The TSMC process delivers a big increase in performance/watt. Xilinx claim 2-5X. Of course you can take that as extra performance for the same power, or lower power for the same performance, or some combination. But note the small print, they compare themselves to their 28nm arrays (since that is what most people are actually using today) and not to the 20nm generation.

Learn more at the Xilinx website here.

Also Read: Altera 14nm and 10nm Update!

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