Open-Silicon SerDes TCoE Enables Successful Delivery of ASICs for Next-generation, High-Speed Systems

With 5G cellular networks just around the corner, there is an ever-increasing number of companies working to bring faster communications chips to the market. Data centers are now deploying 100G to handle the increased bandwidth requirements, typically in the form of four 28Gbps channels and that means ASIC designers are looking to integrate Serializer/Deserializer (SerDes) solutions that can reliably handle these speeds.

Few companies have the experience to do this correctly and they quite often look to outside sources to help with this part of their ASIC design. The hard work you put into your ASIC will be all for naught if you can’t get those high-speed signals on and off the die correctly, through the package and the board.

The choice of package can make or break your ASIC design both in terms of technical system specifications for the SerDes interface, as well as cost and reliability trade-offs. These are tough decisions to make that can largely impact project success, and possibly your career. To mitigate these risks, many customers turn to veteran ASIC design-services companies like Open-Silicon to mitigate their risk and help them make the proper package and board trade-offs that ensure final system success.

Open-Silicon has an impressive amount of experience in this area, having already integrated SerDes interfaces into over 100+ ASIC designs for high-speed systems used in the networking, telecom, computing and storage markets. In addition to their own experienced people, Open-Silicon also works with silicon-qualified SerDes IP providers who offer solutions that range across multiple technology nodes, foundries and communication protocols. Open-Silicon provides design services through their Technology Center of Excellence (TCoE). In the TCoE, Open-Silicon offers ASIC designers services such as: Channel Evaluation: Identifying the right SerDes solution by evaluating the channels and applications intended for the system

PCS and Controller Solutions: Evaluating the PCS and Controller/MAC requirements for the interface to the core and optimizing for interoperability of hard and soft macros

Physical Integration:Evaluating the metal stack compatibility, special layer and threshold voltage requirements, placement of SerDes on chip and bump plan for physical verification and packaging

Package/Board Design: Collaboratively working on packaging and board design including 3D parasitic extraction and crosstalk and simultaneous switching output noise analysis, signal/power integrity along with other system-level considerations

Silicon Bring-up: Close coordination with design-for-test and test teams for final design bring-up and quick assessment on automatic test equipment.

I recently conversed with H. N. Naveen and Abu Eghan of Open Silicon who did a case study integrating high-speed SerDes into an ASIC design. The first thing they pointed out is that interactions between the ASIC and the environment have a tremendous impact on the success of your ASIC within the system. Interactions between die, package, and printed circuit board must be considered and optimized to get a solid, reliable, high-speed interface. Normally these are three very different domains handled by different people but when it comes to a high-speed SerDes interfaces, a company must think differently. All these areas must be co-designed to ensure correct performance at these high frequencies.

In the Open-Silicon case study, a 28nm SerDes IP was chosen for a 4-channel, 28Gbps/channel communications ASIC intended to be used in a 100G Ethernet back-plane. Naveen and Eghan’s task was to focus on ensuring that the package and board design were tuned to work with the chosen SerDes IP.

The first package choice was a high performance Low Temperature Co-Fired Ceramic (LTCC) Flip-chip substrate. Their analysis included examining the return and insertion loss and package crosstalk of this and other packages. Additionally, they also looked at the PCB stack to make trade-offs regarding surface roughness, pin assignments, signal escape and routing, edge conditions and signal loss at the board level.

The final package design was selected and optimized through simulations to meet targets culled from CEI specs including pair to pair isolation and substrate insertion loss. The main drivers for their selection and analysis process included overall performance of the SerDes through to the board connections, cost effectiveness of the package, the ability to handle the high-speed signals over wide bandwidth and consistency for fabricated products to ensure manufacturability.

As part of the analysis they also determined they could meet the system requirements using an alternative High Density Build Up (HDBU) type package that had less capabilities but would be somewhat cheaper. In the end, the LTCC version (HiTCE ceramic) was chosen to take advantage of the extra margins in its loss characteristics.

Signal integrity analysis is one of the most important activities to be performed on SerDes signal lines on a printed circuit board. The PCB materials, via’s, copper surface roughness etc., become very critical when the signal speeds are very high (>10Gbps). A channel model is created which represent the complete channel comprised of transmitter and receiver (die), package, PCB and connectors. The losses and signal quality are analyzed and the various parameters of the channel are fine-tuned to obtain the optimum operating conditions to meet the prescribed standards. Each and every component of the channel is critical and has to be optimized to ensure successful functioning of the system.

The end result of the case study was an optimized high-bandwidth package and board design for 28Gbps that met all of the test requirements without any issues. As said before, these kinds of trade-offs are not easy and Open-Silicon has demonstrated that they have the expertise and experience to help system designers overcome the challenges of choosing and implementing next generation high-speed 56Gbps SerDes for ASIC designs targeted at future networking, telecom, computing and storage applications.

Since completing the case study, Open-Silicon has productized their work into a 28Gbps SerDes evaluation platform for ASIC development enabling rapid deployment of chips and systems for 100G networks. The Open-Silicon SerDes platform includes a full validation board with a packaged 28nm test chip, software and characterization data. The chip integrates a 28Gbps SerDes quad macro, using physical layer (PHY) IP from Rambus, and meets the compliance needs of the CEI-28G-VSR, CEI-25-LR and CEI-28G-SR specifications.

For more details on the case study and the resulting evaluation platform from Open-Silicon I encourage the reader to follow the links at the end of the article.

See Also:
Open-Silicon Case Study
Open-Silicon SerDes TCoE

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