IEDM 2022 – Imec 4 Track Cell

At the IEDM conference in December 2022, Imec presented “Semi-damascene Integration of a 2-layer MOL VHV Scaling Booster to Enable 4-track Standard Cells,” I had a chance to not only read the paper and see it presented, but also to interview one of the authors Zsolt Tokie.

Logic designs are built up by standard cells such as inverters, NAND gates, scanned flip-flips and other cells. The width of a standard cell is some number of contacted poly pitches (CPP) depending on the cell type and whether the cell has a single or double diffusion break, for example a 2-input NAND gate will be 3CPP wide for single diffusion break and 4CPP wide for double diffusion break. The height of a standard cell is characterized by the metal 2 pitch (M2P) multiplied by the tracks (number of M2P).

As it has become increasingly difficult to scale CPP and M2P, design technology co-optimization (DTCO) has become increasingly important in scaling with techniques such as reducing the tracks. Currently minimum cells are generally 6-tracks with some 5-track cells emerging. In this paper Imec discusses routing techniques to enable a 4-track cell.

Figure 1. presents the Imec roadmap from 9-tracks down to 4-tracks.

Figure 1. Imec scaling roadmap.

Before getting into the routing techniques described here, I wanted to touch briefly on other requirements for cell height scaling, simply talking about M2P and tracks ignores the underlying device structure. The cell height must fit the n and p FETs, n-to-p spacing and boundary widths. The transition from FinFETs to Horizontal Nano Sheets (HNS) provides scaling of the n and p FETs by switching from multiple fins taking up horizontal space to a stack of nano sheets in the vertical direction. Techniques such as forksheets (FS) and buried power rails (BPR) are additional options Imec is developing to address the device height, for example BPR can replace wide metal-2 power rails with tall-thin power rials in the substrate reducing boundary widths, and forksheets can reduce n-to-p spacing. Irrespective of the particular techniques employed the devices must be interconnected.

Leading edge processes have seen the introduction of middle-of-line interconnect layers under the metal-1 layer, these additional layers are typically referred to as Metal 0 (M0) or Mint in Imec’s terminology. To get to a 4-track cell a single M0 layer is not sufficient to interconnect the device. In this work an M0A and M0B are added underneath Mint and in a novel process architecture Mint is used as a mask to perform a tip-to-tip cut in M0B.

Mint connects down to M0B through a via VintB and down to the gate contact through VintG. M0B connects to source drains through Via V0A down to M0A.

Figure 2 illustrates the congestion in a 4-track cell with Mint and Figure 3 illustrates the addition of M0B and M0A.

Figure 2. Congested Cell with Mint only.

Figure 3. Congestion Fixed with addition of M0B and M0A.

To achieve the required tight tip-to-tip spacing a self-aligned cut is used for M0B where Mint acts as the mask, this requires a subtractive metallization process. The metallization utilized here is ruthenium (ruthenium can be dry etched unlike copper) deposited using the semi damascene technique, see figure 4.

Figure 4. Semi-Damascene.

The self-aligned M0B cut is illustrated in figure 5.

Figure 5. M0B Self-Aligned Cut.

By adding two layers and using a self-aligned cut and a 4-track cell can be interconnected. Provided the underlying device structure can also achieve the required scaling this interconnect scheme provides a path to 4-track cells and continued scaling.

 Also Read:

IEDM 2022 – TSMC 3nm

IEDM 2022 – Ann Kelleher of Intel – Plenary Talk

IEDM 2022 is shaping up