VLSI Symposium 2020 – Imec Monolithic CFET

The 2020 VLSI Technology Symposium was held as a virtual conference from June 14^th through June 19^th. At the symposium Imec gave an interesting paper on Monolithic CFET and I had a chance to interview one of the authors, Hiroaki Arimura.

It is well known in the industry that FinFETs (FF) are reaching the end of their scaling life. Samsung has already announced that they are moving to Horizontal Nanosheets (HNS) at 3nm. TSMC is staying with FF at 3nm but is expected to move to a new architecture for 2nm. Intel is expected to stay with FF at 7nm and then move to HNS at 5nm, assuming they are still pursuing their own technology at that point.

The most likely roadmap for the industry is FF to HNS with or without Forksheets, and then to transition to Complimentary FETs (CFET), see figure 1.

Figure 1. Imec CMOS Roadmap.

 The forksheet and CFET provide shrinks by improving the n to p spacing with CFETs stacking nFET and pFET devices, see figure 2.

Figure 2. CFET structure.

 In the current work a “monolithic” CFET has been developed by using separate wafers for the nFET and pFET and then bonding them together versus a “sequential” CFET where both FET types are fabricated on the same wafer. Imec claims that the monolithic technique is less expensive than the sequential technique with the sequential technique requiring SOI that adds 1% to the substrate cost, see figure 3.

Figure 3. Monolithic CFET cost advantage.

 Authors note, my company is the leading provider of cost and price models to the industry. I plan to cost model this process versus the sequential process but have not had time yet. I find the ~1% higher starting wafer cost confusing for two reasons, one, I do not believe sequential CFETs requires SOI and two, SOI is a lot more than ~1% more expensive than a standard wafer. The monolithic approach will also require two starting wafers and not just one. In my opinion this cost analysis needs more investigation.

In the monolithic approach the nFET and pFET are fabricated on separate wafers allowing each device fabrication flow to be optimized for that device. The process flows for each wafer is illustrated in figure 4.

Figure 4. Process flows for monolithic CFET.

 As we move to N3 and beyond less n to p separation reduces parasitics and improves performance. Also moving to gate all around (GAA) from FF improves electrostatic control by providing a gate on all four sides instead of three sides.

Monolithic CFET as fabricated in this work provides an alternative to sequential CFET for next generation devices and bear further investigation

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