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Is 7nm Coming to the TSMC OIP Ecosystem Forum?

Is 7nm Coming to the TSMC OIP Ecosystem Forum?
by Daniel Nenni on 08-07-2015 at 4:00 pm

This is the 5[SUP]th[/SUP] TSMC Open Innovation Platform Ecosystem Forum and it is not to be missed. Please note that the location has moved from the San Jose Convention Center to the Santa Clara Convention Center which is literally right across the street from the new Levi’s Stadium. If you haven’t been to the new stadium you really should take a tour and stop by the SF 49ers Museum. Public tours run between 10am and 6pm and yes they have WiFi.

The new location will increase attendance significantly this year (my opinion) so you had better register now because space is limited. In addition to networking with 1,000+ semiconductor professionals you will get to hear from TSMC’s executives on what is new and improved for the different processes and surrounding ecosystem: 28nm, 16nm, 10nm, and I would bet 7nm will also be mentioned if not formally announced.

You may also get to hear from one of TSMC’s leading customers. At the TSMC Technology Symposium last April the guest speaker was Avago CEO Hock Tan. Since then Hock has engineered the acquisition of Broadcom for $37B. Previously he acquired LSI Logic for $6.6B so I would definitely like to hear a semiconductor industry update from an executive of his caliber, absolutely.

The event starts at 9am on Thursday, September 17[SUP]th[/SUP]. After the ninety minute executive presentations there are 30 technical papers divided into three tracks for EDA, IP, and Services. The paper abstracts are now up on the OIP website. And of course there will be a vendor expo with 80 vendors bearing gifts and the latest news on design enablement. Rumor has it Solido Design will be giving away the elite SemiWiki.com stylus penlights so you may want to go there first.


Click HEREfor the event overview, agenda and registration

[TABLE] cellpadding=”4″ style=”width: 100%”
|-
| align=”center” style=”width: 15%” |
| align=”center” style=”width: 27%” | EDA Track

| align=”center” style=”width: 29%” | IP Track
| align=”center” style=”width: 29%” | EDA/IP/Services Track
|-
| 11:00 – 11:30
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Tackling coloring, cell pin access and variation at TSMC 10nm
|-
| align=”center” valign=”top” | Cadence
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Low power SERDES to concurrently enable HMCPCIe in 16FF
|-
| align=”center” valign=”top” | Analog Bits

|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Ultra Low Power OTP Design for Smart Connected Universe Applications

|-
| align=”center” valign=”top” | Sidense
|-

|-
| 11:30 – 12:00
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Exploring Custom Metal Stacks for Advanced Node IC Design Using Early StarRC Extraction
|-
| align=”center” valign=”top” | Synopsys
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Migrating ARM Cortex-A53 designs From 28HPM to 28HPC+ – Getting Two Designs Out of a Single Implementation
|-
| align=”center” valign=”top” | ARM
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Timing Closure Strategy with Massive Scenarios in Advanced Node
|-
| align=”center” valign=”top” | Dorado Design Automation
|-

|-
| 12:00 – 13:00
| colspan=”3″ align=”center” valign=”top” | Lunch
|-
| 13:00 – 13:30
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Thermal and Color-aware Reliability Verification for Sub-16nm FinFET Designs
|-
| align=”center” valign=”top” | Ansys Inc.
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Complexities in developing a high performance DDR subsystem at 3200 Mbps on 16FF+10FF
|-
| align=”center” valign=”top” | Cadence
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | High-Speed SerDes Design in Advanced TSMC Process: Architecture Implementation
|-
| align=”center” valign=”top” | GUC
|-

|-
| 13:30 – 14:00
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Custom Device Array- Place, Route, Simulate Prior to Layout
|-
| align=”center” valign=”top” | Cadence
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Implementing a Dual Modulation 56G SerDes IP platform in TSMC 16FF
|-
| align=”center” valign=”top” | Semtech Corporation – Snowbush IP
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Device Aging Simulation Considering Self-Heating Effect using TSMC N16 FinFET Process
|-
| align=”center” valign=”top” | Synopsys
|-

|-
| 14:00 – 14:30
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Hierarchical Fill Methodology for Advanced Nodes
|-
| align=”center” valign=”top” | Mentor Graphics
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Ultra-Low Power IoT Platforms from Silicon to Software
|-
| align=”center” valign=”top” | Synopsys
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | M31 Low-power IP Platform
|-
| align=”center” valign=”top” | M31 Technology
|-

|-
| 14:30 – 15:00
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | IC Packaging centric approach to design fanout-out WLCSP (InFO) designs
|-
| align=”center” valign=”top” | Cadence
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Rapid Implementation of IoT end-point sensor devices using ARM and TSMC IP
|-
| align=”center” valign=”top” | ARM
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | How to avoid blindness about power consumption during low-power SoC design?
|-
| align=”center” valign=”top” | Dolphin Integration
|-

|-
| 15:00 – 15:30
| colspan=”3″ align=”center” | Coffee Break
|-
| 15:30 – 16:00
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | 2-5X productivity improvement in converging to a DRC-clean cell design—Qualcomm’s experience with Calibre RealTime
|-
| align=”center” valign=”top” | Mentor Graphics
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Design of an integrated wireless 4K video camera SoC IP platform
|-
| align=”center” valign=”top” | Imagination Technologies
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Advanced Bump Routing Methodology for SoC Designs with flip chip
|-
| align=”center” valign=”top” | Open-Silicon
|-

|-
| 16:00 – 16:30
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Synopsys’ PrimeTime POCV Improve Productivity and PPA in FinFET Designs – NVIDIA Experience

|-
| align=”center” valign=”top” | Synopsys
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Resolving 10G Bandwidth Issues for High Performance Analog Circuits on TSMC 10FF
|-
| align=”center” valign=”top” | Cadence
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | A New Solution to Sensing Scheme Issues Revealed
|-
| align=”center” valign=”top” | Kilopass
|-

|-
| 16:30 – 17:00
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | TSMC Advanced Node EMIR analysis
|-
| align=”center” valign=”top” | Cadence
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Meeting IP Requirements of Next-Generation Automotive SoCs on FinFET Processes
|-
| align=”center” valign=”top” | Synopsys
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Extend trustworthy logic NVM solutions from 8″ to 12″ process nodes for various IoT applications
|-
| align=”center” valign=”top” | eMemory
|-

|-
| 17:00 – 17:30
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | IC Compiler II key in accelerating time-to-market for HiSilicon’s next-generation 10-nm advanced SoC’s
|-
| align=”center” valign=”top” | Synopsys
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Building Silicon IPs
Sub-systems for Automotive Infotainment ADAS Applications

|-
| align=”center” valign=”top” | Cadence
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Accelerating IP To IP Sub systems and Moore
|-
| align=”center” valign=”top” | Synopsys
|-

|-
| 17:30– 18:30
| colspan=”3″ align=”center” | Social Hour
|-

The TSMC OIP Ecosystem Forum brings together TSMC’s design ecosystem companies and our customers to share real case solutions to today’s design challenges. Success stories that illustrate best practices in TSMC’s design ecosystem will highlight the event.

More than 90% of last year’s attendees said that “the forum helped them better understand TSMC’s Open Innovation Platform” and that “they found it effective to hear directly from TSMC OIP member companies.”

This year’s event will prove equally valuable as you hear directly from TSMC OIP companies about how to apply their technologies to address your design challenges!

This year, the forum is a day-long conference kicking-off withtrend-setting addresses and announcements from TSMC and premier IC design company executives.

The technical sessions are dedicated to 30 selected technical papers from TSMC’s EDA, IP, Design Center Alliance and Value Chain Aggregator member companies, and an Ecosystem Pavilion feature up to 80 member companies showcasing their products and services.

Click HERE for the event overview, agenda and registration

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