From Tokens to Infrastructure: Why Compute, Memory, and Power Will Determine the Future of AIBased on Dylan Patel’s SEMI Industry Strategy Symposium…Read More
Intel 18A vs Intel 18A-P: What Is the Difference and Why Does It Matter?Intel’s 18A process technology has become one of…Read More
WEBINAR: Why Google Cloud NetApp Volumes Matter for Modern EDA WorkloadsIn this webinar, Google Cloud and NetApp explore…Read More
How to Free Yourself from Inconsistent Engineering Documentation Before It’s Too LateEmbedded systems programs often fail because critical engineering…Read More
COMPUTEX 2026: S2C and Andes Technology Showcase Hardcore "EDA+IP" Synergy for the AI EraCOMPUTEX 2026 officially concluded under the theme “AI…Read More
One challenge with security in systems is to ensure that there are not backdoors, either accidentally or maliciously inserted. Intel, ARM and others have various forms of trusted execution technology. Under the hood these are implemented by dividing the design into two parts, normal and secure, and implementing them with physical… Read More
In an interview (probably $) with the Wall Street Journal, Eric Schmidt, the chairman (and ex-CEO) of Google, said:“The adult way to run a business is to run it more like a country. They have disputes, yet they’ve actually been able to have huge trade with each other. They’re not sending bombs at each other. … It’s extremely curious… Read More
Wanna become the double patterning guru at your company? David Abercrombie, DFM Program Manager for Calibre, has written a series of articles detailing the multifaceted impacts of double patterning on advanced node design and verification. For designers struggling to understand the complexity and nuances of double patterning,… Read More
One of the decisions that needs to be made when using high-level synthesis (HLS) in general and Catapult in particular is what language to use as input. The choice is C++ or SystemC. Of course at some level SystemC is C++ with added libraries and templates, but in fact the semantics of the two languages end up being very different.
The… Read More
I’ve used FPGA vendor-supplied tools from both Xilinxand Lattice Semibefore, so I wanted to see what EDA tools Aldec has to offer for FPGA design. I read the Aldecwhite paper, Corporate Standardization of FPGA Design Flow, and summarize what I found.… Read More
I reviewed the book Mixed-Signal Methodology Guidein August of this year published by Cadence, and decided to follow up with one of the authors, Michael Henrie from ClioSoft, to learn more about the importance of Design Management for AMS. Michael is a Software Engineering Manager at ClioSoft and has worked at Zarlink Semi, Legerity,… Read More
If you pass by Grenoble tomorrow (Tuesday 4th Dec.) and go to IP-SoC 2012, then you should attend this panel at 4pm in the Auditorium (you can’t miss it, it’s the larger room at the registration level).
If you are Designer, Architect, Project Manager, Marketing… working for a chip maker, please prepare questions!… Read More
It seems that Ateris vs. Sonics war, initiated by Sonics in 2010 on the legal battle field, is now continuing on the marketing field, as far as I am concerned, I prefer the latter, as I am an engineer and not a lawyer, and I must say that playing in the marketing allow both companies to extract the most attractive features of their products.… Read More
ST Microelectronics announced yesterday that it would have a conference call on December 10th to announce its strategy going forward. ST has been struggling the last couple of years, with revenues down year to year. From 2010-2012 (the last an estimate of course) it did $10.3B, $9.6B and $8.4B so it has shrunk nearly 20% in 3 years.… Read More
IC designers using advanced nodes are acutely aware of how variation effects in the silicon itself are causing increased analysis and design efforts in order to yield chips at acceptable levels. Four authors from Solidoare so passionate about this topic that they combined their years of experience into a book that I had a chance… Read More
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Intel 18A vs Intel 18A-P: What Is the Difference and Why Does It Matter?