LRCX- Coulda been worse but wasn't so relief rally- Flattish is better than downLam put in good quarter with flattish guide-…Read More
From Space-Central to Space-Time Balanced - A Perspective for Moore’s Law 2.0 and A Holistic Paradigm for EmergenceA friend of SemiWiki published an article on…Read More
The credit here goes to Atrenta for surveying their customer base in an effort to open up new communication channels for in-demand content using Web 2.0 technologies. The results are not surprising to me but they may be to other semiconductor ecosystem executives who do not get Social Media at all!
I have been using LinkedIn for five+… Read More
There has been a lot of talk about the fluid role of IP in semiconductor design. With the Synopsys acquisition of Virage Logic the playing field has tilted substantially in favor of Synopsys… or maybe not!
At first glance this acquisition appears to be a huge threat to EDA and IP companies allowing Synopsys to “throw in” IP as… Read More
The big EDA news last week of course was the CNBC interview (HERE) with infamous corporate raider Carl Icahn. Carl is not happy with Mentor Executives, nor is Mentor investor Donald Drapkin who said, and I quote, “It’s just a sleepy company run like a country club”. Carl and Donald’s combined MENT investment is 20%+ … Read More
A growing number of reports highlight a class of design errors that is difficult to check using more traditional methods, and can potentially affect a wide range of IC designs, especially where high reliability is a must.By Matthew Hogan
Today’s IC designs are complex. They contain vast arrays of features and functionality in … Read More
Good news in a way: Merrill Lynch (or Bank of America Merrill Lynch as I suppose we have to get used to calling them) have re-started coverage of EDA with a 20 page report on the industry, much of which is spent on explaining how the industry segments out and who is strong in which segments, stuff that most people reading this site already… Read More
When I worked at Intel as a circuit design engineer I could talk directly with the technology development engineers to understand how to really push my DRAM designs and get the smallest possible memory cell layout that would still yield well, provide fast access time, and long refresh cycles.
(United States Patent 6661699. Inventor:… Read More
"Managing increasing complexity through higher-level of abstraction: What the past has taught us about the future" Dr. Ajoy Bose, Atrenta CEO
Here is the abstract:
Time to market and design complexity challenges are well-known; we have all seen the statistics and predictions. A well-defined strategy to address … Read More
During the most recent conference call (transcript), TSMC not only beat revised estimates and announced record spending levels for 2011, Morris Chang also officially announced that a 450mm fab (Fab 12 Phase VI) is currently in the planning stages with target production @ 20nm in 2015. This is HUGE!
According to Morris Chang:
“For… Read More
Cadence at DesignCon 2011
I met with Rahul Deokar, Product Manager this morning to review 9 slides that tell the story of Giga-gates and GigaHz systems design at Cadence. Their updated P&R system now completes jobs 2X faster for 28nm designs.
Silicon Realization Trends and Challenges:
Silicon Realization – end to end digital… Read More
Process Design Kit (PDK) development is one of the most entertaining things to watch in the semiconductor design world. It is kind of like the Golden Snitch in the game of Quidditch. No matter how rough EDA vendors play the game, no matter what the score is, it’s the vendor that “gets” the Golden PDK Snitch that wins the semiconductor… Read More
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