When I worked at Intel as a circuit design engineer I could talk directly with the technology development engineers to understand how to really push my DRAM designs and get the smallest possible memory cell layout that would still yield well, provide fast access time, and long refresh cycles.
(United States Patent 6661699. Inventor: Walker, Darryl Gene)
Today with the dominant fab-light model most IC designers need to work with a foundry to receive DRC decks plus DFM rules and guidelines.
Because DRC complexity have exploded to over 1,000 rules at the 65nm node and below, we must consider new techniques like 2D pattern-matching to speed up the checking.
Design For Manufacturing now covers multiple EDA tools, even Place & Route. The width of interconnect is now dependent on adjacent wires in two dimensions:
Chemical Mechanical Polishing is commonly used to make IC layouts more planar, which improves yield by keeping the layers parallel to the substrate. There are IC layout rules to ensure that CMP will work properly.
(IC cross-section. Left: Without CMP, Right: With CMP)
Drawing a transistor gate as a rectangle isn’t how it really ends up in silicon. By providing feedback to the circuit designer on how the non-ideal transistor will perform, it gives a more accurate way to simulate circuit performance.
On March 10 in Santa Clara at the EDA Tech Forum you can meet and learn from experts in these topics of: DRC+, DFM, CMP, Variabiity
This is an all-day seminar, and best of all the price is free. Just visit the site and register online to reserve your spot.Share this post via: