How many things are there anyways in an IC? (When viewed at sufficiently high resolution)

[M. Y. Zuo]

Hello everyone!

This is my first time asking a substantial question here.

I’ve always been curious about cataloguing all the various things (structures, features, anomalies, and so on) within an IC. I understand this is a big ask so I’m focusing on the very simplest real world example (I think!) .

The uln2003.

I am assuming a good quality 150 billion voxel scan (at 100 nm resolution) of an exemplar uln2003 has already been completed. The 600 GB file has been processed and is ready for viewing on appropriate machines.

Here is what I have so far:

Features​

• Active Transistors (14): 7 driver transistors and 7 power output transistors
• 
  
• Diffused Resistors (21): 7 input resistors, 7 pre-driver base-emitter bias resistors, and 7 power-stage base-emitter discharge resistors
• 
  
• Inductive Clamp Diodes (7): 1 freewheeling clamp diode per channel

External Bond Pads (16): 7 Input pads, 7 Output pads, 1 common GND pad, 1 common COM pad).

Independent Electrical Nodes (30): 7 input-to-resistor nets, 7 internal base nets, 7 output collector nets, 7 base-to-bias nets, 1 common ground net, and 1 common COM net

250 to 350 distinct structural features created during the fabrication process:
Epitaxial Wells (N-type) ~21 (3 per channel: Darlington, Resistor, and Clamp Diode islands
Buried Layers (N+) ~21 (One beneath each epi-well to minimize collector resistance)
Base Diffusions (P-type) ~42 (14 transistor bases, 21 resistor bodies, 7 diode anodes)
Emitter Diffusions (N+) ~60 - 80 (Includes interdigitated power emitter fingers and contact regions)
Contact Windows (Vias) ~150 - 250 (Individual oxide openings for metal-to-silicon contact)

Power transistor interdigitated finger structure (comb-like)
The exact number of emitter fingers (typically 3 to 5 per power ouput transistor).
The matching base fingers interleaving them.
The individual contact windows for each finger, allowing experts to calculate the emitter perimeter-to-area ratio.

Parasitic Collector-Emitter diode
Parasitic Input Substrate Junction

Foundry and Manufacturer Variations​

Layout Differences: Some foundries use different aspect ratios for the interdigitated fingers of the power transistor, varying numbers of emitter stripes, or different geometric routing for the ground lines. (from what I understand)

Material Changes: Modern versions may use different passivation materials or barrier metals.

Common Types of Anomalies​

Electromigration Voids and Hillocks:
Aluminium-Silicon Junction Spiking:
Oxide Step-Coverage Thinning:
Die-Attach and Packaging Voids:
Lithographic Alignment Error (Runout):

e..g. any sub-micron voids (empty pockets) where aluminum atoms have been swept away by high current densities, as well as aluminum "hillocks" (piles of accumulated metal atoms)

e.g. During the high-temperature metallization annealing step, aluminum can dissolve and diffuse into the underlying silicon. Experts can see if any "spikes" of aluminum have physically penetrated through the thin base region into the collector

Specific Anomalies​

Package-to-Die Interface (Macro-Mechanical)​

Epoxy Mold Compound (EMC) Silica Fillers: The scan resolves the exact size, angular geometry, and spatial distribution of every filler particle from 100 nm on up.

Delamination Gaps: visible as low-density (near-vacuum or air) gaps. At this resolution, the initiation points of package delamination are likely visible.

Lead Frame Anchoring Geometry: The microscopic surface roughness and mechanical locking teeth profile of the lead frame.

1. Mold Flow Voids: Microscopic air bubbles trapped during the transfer molding process, visible as spherical, low-density regions.

Bond Pads and Thermosonic Wire Bonds​

Bond Ball Deformity: The exact 3D geometry of the squashed ball bond, including the "nail-head" or wedge profile and any peripheral flash (excess squished metal).

Intermetallic Compound (IMC) Layers: The phase boundary between the wire and the pad. The growth of IMC phases like "white plague" or "purple plague" should be visible as intermediate-density bands at the interface.

1. Kirkendall Voiding: Sub-micron voids or porosity formed at the gold-aluminum interface due to the differential diffusion rates of the two metals under thermal stress, visible as irregular chains of low-density voxels.
2. 
   
3. Wire Sweep Deflection: The 3D trajectory of each bond wire, revealing any mechanical bending or sweeping caused by the flow of epoxy during packaging.
4. 
   
5. Probe Marks: Mechanical gouges on the surface of the bond pads left by needle probes during wafer-level testing prior to packaging.

Passivation and Die Surface Topography​

Passivation Thickness Profiling: Localized thickness variations in the CVD layers across the die.

Step Coverage Thinning: Thinning of the passivation layer at steep corners where metal lines climb over field oxide boundaries.

1. Passivation Pinholes and Micro-cracks: Sub-micron structural failures or cracks in the dielectric coating, visible as narrow, low-density channels extending down to the metallization layer.
2. 
   
3. Surface Contaminants: Any foreign particles (such as organic dust or silica shards) trapped beneath the passivation layer during the fabrication steps.

Metallization and Interconnect Network​

1. Aluminum Grain Boundaries: Under high phase-contrast imaging, the boundary interfaces between individual aluminum crystals (grains) are visible.
   
   
2. Silicon Nodule Precipitation: Over time or during thermal cycles, silicon can precipitate out of the alloy, forming high-density silicon nodules
   
   
3. Electromigration Voids: Microscopic empty spaces within the aluminum lines, particularly in the high-current ground paths, where aluminum atoms have been physically pushed downstream by high current densities.
4. 
   
5. Electromigration Hillocks: Protruding whiskers or mounds of accumulated aluminum atoms pushed out of the track boundaries, which can crack the overlying passivation.
6. 
   
7. Metal Slit Defects: Stress-induced voiding forming thin, transverse cracks across metal lines due to thermal mismatch stresses with the surrounding oxide.
8. 
   
9. Line Edge Roughness (LER): The microscopic jaggedness and geometric non-uniformity of the etched metal line edges.

Contact Windows and Ohmic Interfaces​

1. Contact Window Etch Geometry: The slope and symmetry of the contact holes etched through the layer. Asymmetrical contact profiles indicate lithographic or etching errors.
   
   
2. Under-Etched Contacts: Residual left at the bottom of a contact hole, visible as an intermediate-density barrier preventing direct contact between the aluminum and the silicon substrate.
3. Barrier Metal Profiling: In processes utilizing a thin barrier metal (such as Titanium/Titanium Nitride or Tungsten), these layers can be identified via density-contrast mapping due to the much higher atomic weight.
   
   
4. Aluminium-Silicon Spiking: The physical degradation where aluminum has dissolved into the silicon, forming microscopic spikes that project downward through the shallow diffusion junctions.
5. 
   
6. Contact Electromigration: The movement of silicon atoms into the aluminum contact window under high current stress, resulting in void formation at the silicon interface and eventual contact failure.

Active Semiconductor Regions (Silicon Junctions)​

1. Emitter Well Boundaries: The precise 3D cup-like shapes of the shallow phosphorus-doped emitter regions.
   
   
2. Base Well Boundaries: The boron-doped base wells surrounding the emitter wells, including the lateral diffusion profiles under the oxide mask edges.
   
   
3. Epitaxial Well Boundaries: The large isolated wells that define the collector regions, separating them from the bulk substrate.
   
   
4. Buried Layer Geometry: The highly doped antimony/arsenic sub-collector layers at the bottom of the epitaxial wells, revealing their thickness and lateral spread.
   
   
5. Isolation Diffusion Channels: The deep isolation walls driven from the surface down to the substrate, revealing their width and the continuity of the isolation grid.
   
   
6. Channel Stop/Guard Ring Boundaries: Heavily doped surface regions designed to prevent parasitic surface-inversion channels from forming beneath the oxide layers.
7. 
   
8. Resistor Body Paths: The meandering paths of the diffused resistors, revealing the exact length, width, and cross-sectional depth profile of the resistive tracks.

Substrate and Bulk Crystal Quality​

1. Crystalline Dislocations and Stacking Faults: Severe crystallographic defects or slip planes, often decorated with metallic impurity precipitates (such as copper or iron), which alter the local X-ray diffraction properties.
2. 
   
3. Die-Attach Voids: Large, irregular bubbles within the solder or silver-filled conductive epoxy adhesive used to bond the back of the silicon die to the copper lead frame paddle, visible as low-density voids.
4. 
   
5. Backside Metallization Integrity: Cracks or delamination in the gold or titanium-nickel-silver layers sputtered onto the back of the silicon wafer to facilitate ohmic contact and die bonding.
6. 
   
7. Micro-cracks (Chipping): Internal fractures radiating from the dicing streets (edges of the silicon die) caused by mechanical stress during the wafer sawing process.

Lithographic and Processing Variations​

1. Layer-to-Layer Misalignment (Overlay Error): The physical offset or shift between different masks (e.g., contact window mask relative to the emitter diffusion mask). This is measured as lateral displacement.
   
   
2. Mask Runout: Variations in the scaling or rotation of the masks across the die, visible as progressive alignment drifts from one corner of the chip to the other.
3. 
   
4. Critical Dimension (CD) Variation: Differences in the width of identical features (like identical resistor tracks or transistor fingers) across different regions of the die, reflecting spatial variations in the lithographic exposure or etching steps.
5. 
   
6. Over-Etch/Under-Etch Profiles: The side-wall angles of the etched oxide and metal lines, showing whether they are anisotropic (vertical walls) or isotropic (sloped, undercut walls).

Wearout, Degradation, and Over-Stress Footprints​

1. Silicon Fusion (Melted Regions): Localized regions where high-current overstress caused the silicon to reach its melting point. Upon cooling, the silicon re-crystallizes into a disordered, amorphous, or polycrystalline phase with a distinct microscopic density boundary.
   
   
2. Metal Runout/Melting: Open-circuit locations where aluminum tracks have melted and balled up due to localized Joule heating under excessive load currents.
3. 
   
4. Passivation Rupture Craters: Blow-out craters where the high pressure of vaporized metal or silicon during an ESD event has physically shattered and ejected the overlying passivation layer.
5. 
   
6. Junction Punch-Through: Localized thermal damage where the emitter-base or base-collector junctions have melted together, creating a permanent, low-resistance short circuit.

That’s all I have right now. Please let me know if I’ve missed anything or made any mistakes in this information!

Edit: Shortened title and some descriptors.