Semiconductor Quidditch @ DesignCon 2011!

Semiconductor Quidditch @ DesignCon 2011!
by Daniel Nenni on 01-26-2011 at 10:09 pm

Process Design Kit (PDK) development is one of the most entertaining things to watch in the semiconductor design world. It is kind of like the Golden Snitch in the game of Quidditch. No matter how rough EDA vendors play the game, no matter what the score is, it’s the vendor that “gets” the Golden PDK Snitch that wins the semiconductor process node. Vendor specific PDKs allow an EDA company to dominate a given market segment. Today, analog design PDKs are dominated by the Cadence Virtuoso franchise. Virtuoso maintains an 80%+ market share by locking customers into Cadence proprietary PDK technology, specifically, the Cadence PCell (parameterized cell) and the Skill scripting language.

PDKs for Analog IC Design – A Stakeholder Discussion
Speaker:Daniel Nenni (Moderator) (Moderator, SemiWiki), Mass Sivilotti (Chief Scientist, Tanner EDA), Yaron Kretchmer (Senior Manager, SJ Backend CAD, Altera), Tom Quan (Design Methodology & Service Marketing (DMSM), TSMC), John Stabenow (Group Director, Custom/Analog Product Management, Cadence Design Systems), Ed Lechner (Synopsys), Samir Chaudhry (TowerJazz Semiconductor)
Date/Time:Wednesday (February 2, 2011) 3:45pm — 5:00pm
Location (room):Ballroom F
Track:Special Events
Formats:75-Minute Technical Panel
Audience level:Introductory

PDK’s are THE communication link between semiconductor design and manufacturing. For every process node there will be multiple PDKs to support the different design types (Analog, Digital, etc…), different tool vendors and formats. Multiply that by dozens of process variations and you get millions of dollars in overhead expense passed onto the consumers of electronic devices, or more specifically, passed on to the parents of those consumers!

Presentation Abstract:
Process Design Kits (PDKs) are an essential component of the Analog Designers’ toolkit. Recent industry initiatives aimed at defining PDK standards and reducing the PDK maintenance overhead have been largely focused on process nodes that are biased towards leading-edge digital designs. The result is that Analog Designers are at risk of having the standards and process rules not meet their requirements. This panel discussion will outline and explore some of the key challenges facing Analog Designers related to PDKs. Opinions, perspectives and proposed mitigation strategies will be expressed by representatives from key stakeholder groups: Designers, EDA Tool Vendors, and Foundries.

This is your chance to be heard and interact with both sides of the PDK equation: Foundries, EDA Vendors, and even a power PDK customer, Yaron Kretchmer (Altera). Trust me on this one, adding Yaron to this panel is like starting your family BBQ with rocket fuel. There will be no slides, the panelists will make short position statements and we will take questions from the audience. Here are the position statements from TSMC, Cadence, TowerJazz, Tanner, and Synopsys:


“Three key attributes of PDK: (1) completeness, (2) robustness, and (3) availability. For analog design, completeness means having the right devices/components in the PDk for transistor-level design, and basic building blocks, such as current mirrors, diff pairs, etc. to speed up the design. Robustness means high quality, i.e. fully-qualified/validated by foundries to work with a set of pre-qualified design tools. Availability means the right PDK for the right process node is available when you need it for the next design. The PDK also must be interoperable between several EDA analog design tools/solutions, so designers can pick and choose the best-in-class design tools without sacrificing design quality and productivity or having to wait for the right PDK to be available.”


“EDA suppliers know that accuracy is the #1 necessity for the analog designer. The analog designer needs a tool set that can accurately reflect the probable realities of the silicon. Each vendor takes a different approach, both in the front end design and the back end design, to achieving this goal. It can be enhancing the “by hand” needs of the designers all the way to automation and optimization, and all EDA suppliers seek to differentiate their offerings. This is why high precision, high quality PDK’s will be unique to every vendor, and will be honed to fit like hand and glove with the software tools used for creation and implementation of the design.”


“Analog-intensive, mixed-signal (AIMS) ICs are defined as chips with a large analog content and a small digital content, and are designed for applications ranging from precision analog to high-performance radio frequency (RF) transceivers in communication systems. Over the last decade, the technology needs of AIMS ICs have diverged from those of digital ICs. The AIMS IC technology migration towards advanced nodes (sub-130-nanometer) has been slow. Instead, the need for higher performance analog components, such as SiGe bipolars, high-voltage metal-oxide semiconductor field-effect transistors (MOSFETs) and high-performance passives, coupled with the need for lower development costs, has necessitated the use of specialty process technologies at mature nodes. An often overlooked consideration by design teams while evaluating AIMS technology platforms relates to design automation. Design enablement tools, including silicon-verified device models and flexible design environments, allow IC design teams to test, modify and improve the functionality and yield of new products long before the first prototype is manufactured. To reduce time-to-market and prototyping costs, best-in-class design automation tools are essential.”


“The perfect storm of increasing analog content, decreasing process line-width, and shortening product design cycles has focused attention on a new bottleneck: analog design. Analog PDKs hold out the promise of both broadening the community of engineers doing analog design, and improving their productivity. It broadens the community by opening up high-performance design to a class of users who never previously considered themselves to be Analog Designers and are now facing analog-like design challenges. It is simultaneously benefiting “card-carrying” Analog Designers – as it provides silicon-proven standard models that aid productivity. Delivering on this promise requires that we overcome the challenge of accommodating diversity in design methodologies, foundry capabilities and EDA tool functionality. This is the manifold challenge we face in making sure PDKs allow for tool innovation. A good example is Tanner’s High Performance Device Generation tool. If we limit a PDK to the set of cells designed by the foundry, we limit the style and performance of the design. Extending the definition of PDK to allow silicon-qualified models for devices such as those in HiPer DevGen would bring tremendous value to both the Foundries and their customers.”

“Synopsys believes that applying standards to PDKs benefits all designers working at the transistor level. This spans custom digital, mainstream analog, high-precision analog and even RF. Lack of standards within the PDK domain have been a consistent impediment to designer productivity, EDA tool innovation, design reuse and design migration. Analog designers have told us they cannot take advantage of new EDA tools because the PDKs are proprietary and incompatible. They’ve also said migrating their designs is painful because of PDK incompatibilities. However, they have not expressed any concern regarding PDK standards negatively impacting their livelihood or restricting their creative needs. For this reason, Synopsys is investing in PDK standards – to help address these analog design issues.”

“The abstract for this panel session, suggests that analog design and advanced process nodes are mutually exclusive. This is not the case. Synopsys has partnered with leading foundries and semiconductor companies to implement PDKs on leading-edge process nodes because this is a natural transition point where new PDKs are being developed, new design starts are being kicked off and new flows are being defined on OpenAccess. Some of the toughest analog design challenges are emerging in these advanced processes. We know this because Synopsys has a large team designing complex, high-performance analog and mixed-signal IP on process technologies ranging from 180-nm down to 28-nm using interoperable PDKs based on IPL standards (iPDKs). We have also collaborated with foundries, IDMs and fabless companies to develop iPDKs at 40nm and below with accurate DFM capabilities is painful, if not impossible, to address using legacy PDK languages and techniques. Lastly, we have customers using standards-based iPDKs on older nodes for analog design with no loss of capability or functionality. Historically, analog design has been slow to change, but it’s already happening. The demonstrated benefits of iPDK standards far outweigh the speculative risks that often accompany change.”

I hope to see you there!