Architecture Exploration of Processors and SoC to trade off power and performance 5
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 3303
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 3303
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
)

DesignCon 2011 Trip Reports!

DesignCon 2011 Trip Reports!
by Daniel Payne on 02-01-2011 at 1:38 pm

Cadence at DesignCon 2011

I met with Rahul Deokar, Product Manager this morning to review 9 slides that tell the story of Giga-gates and GigaHz systems design at Cadence. Their updated P&R system now completes jobs 2X faster for 28nm designs.

Silicon Realization Trends and Challenges:

Silicon Realization – end to end digital flow. No more foucs on just point tools, instead we’re organized end to end flow based. Top 3 of best tool innovations at DesignCon (nominated).

Challenges (2) – Japanese key customers confirm the needs. How to get faster ARM cores, .8 to 1GHz.

Low Power, Mixed Signal – more automation (power shutoff, dynamic voltage scaling), tool interoperability

Adv tech – 3D, 20nm. How to make mobile video? There are node Migration risks.

3. Traditional tools are breaking, convergence issues (Physical synthesis), The 3D tool flow is very different from previous tool flows. Abstraction models at chip and package levels are new.

4. Intent-abstraction-convergence. Supports 28nm flow. Faster P&R (2x). New power intent architect (graphical UI), shipped in December.

Abstraction (patented) – gate level netlist analysis with logic and physical, compress db size of 80%, stores more efficiently. Renesas paper has numbers on db size. Hierarchical modeling of IP for power budget.

Convergence – Physical synthesis, ECO flow improvements to reduce the rework back into RTL. Promote an all-Cadence tool flow.

Litho hot spots, how to fix? In the past simulation approaches to litho with long run times. InDesign DFM from Clearshap a few years ago. DRC+ is a new technique with pattern-based, see Global Foundries press release. DFM and Litho is not an afterthought, using DRC+ and InDesign together.

Q: How does this compare to Mentor’s approach of DFM in the loop?
A: No comment on Mentor.

IC (Virtuoso), Package (Allegro) – all play together for 3D design.

Mixed-signal – how to do timing? Build macros. Tool now on the fly can traverse digital and do STA, mixed-signal optimization is done on the fly. Analog is still transistor-level optimization.

5. How to design 3D and analyze. 3D config file ties all the domains together. Beyond just 2 to 3 die stack, expect 7 stacks. Concurrent design now possible. Allegro shows the 3D view for 3D design. Interposer example has multiple routing levels in it. Foundries have new design rules (TSMC, Global Foundries) for 3D.

Thermal plot showing 2D and 3D views of gradients. Thermal results fed back to timing.
Q: How does this compare to Gradient DA or Apache DA?
A: No comment on competition.

6. ARM relationship, they used a Cadence flow. Out of box scripts, use Cadence services to increase the CPU core speeds.

8. Customer feedback

Q: Summary – can I still use OpenDoor partners?
A: Yes, We have a framework with OA, and CPF standards.

3D white paper is available.

DRC+ paper with Global Foundries

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