DAC News – A New Era of Electronic Design Begins with Siemens EDA AIAI is the centerpiece of DAC this year.…Read More
Arteris at the 2025 Design Automation Conference #62DACKey Takeaways: Expanded Multi-Die Solution: Arteris showcases its…Read More
Secure-IC at the 2025 Design Automation Conference #62DACSecure-IC at DAC 2025: Building Trust into Tomorrow’s…Read More
AVNET released their 15[SUP]th[/SUP] Xfest this year, a couple of months ago. It was here in Germany last week. It was a well organized event, rich with invaluable technical information and full of decent smart engineers and managers. If you missed it this year register for the next event as soon as you can.
It was a very successful… Read More
EDAC has a series of seminars for emerging companies with Jim Hogan. Jim has been in EDA since, like, forever. First at National, then at Cadence, then at Artisan (now ARM) and then as an investor first at Telos (Cadence’s VC arm) and more recently on his own at Vista Ventures. He has been involved with many EDA and semiconductor… Read More
In the world of sub-40nm IC design, as feature size decreases with each new process node, it becomes increasingly difficult to migrate a layout to a new process technology. Too many factors impact manufacturability and yield. At each new process node, to make sure that a given layout is manufacturable and yields well, it is subject… Read More
At EDPS in Monterey, Tom Spyrou of AMD talked about their compute environment in the context of parallel algorithms. I discovered that they are a big user of RTDA’s FlowTracer so I talked to Philip Steinke at AMD about how they used it.
He said that they largely use it as described in The Art of Flows as a graphical distributed … Read More
Since most of you have not heard of Novocellthis is more of an introduction but they have been around for 10+ years and are NVM (non-volitile memory) pioneers. NVM has evolved into a critical part of the semiconductor ecosystem which is why I sought them out. While SiDense and Kilopass bury each other in legal fees Novocell is doing… Read More
In April I blogged about a webinar on co-simulation hosted by Aldec and Tanner EDA where they showed how the RTL simulator (Riviera PRO) and SPICE simulator (T-Spice) had been connected together for IC designers wanting to do real AMS simulations.
The availability date of the co-simulation wasn’t clear, so today the press… Read More
Before going to Munich to attend to CDN-Live, I took a look at the agenda to figure out which presentations to attend, and I must say it was not so easy to choose: CDN Live agendais dense, with multiple tracks running in parallel (Custom Design, Digital Implementations, Design IP, Functional Verifications and Verification IP, PCB… Read More
Perhaps the most pertinent comment raised by an analyst at Intel’s Investor Forum last week came from Dan Hutcheson of VLSI Research to Brian Krzanich, the COO and head of global manufacturing and supply chain. He said: “I think you sold yourself short on Trigate, the benefit of fully depleted vs. planar and the impact on leakage.”… Read More
Yesterday’s SEMICO IP Ecosystem Conference was well worth the time. Everybody was there: ARM, Synopsys, Cadence, Mentor Graphics, GlobalFoundries, TSMC, MIPS, Tensilica, AMD, Atrenta, Sonics, and Tabula, everybody except Intel of course. What do Intel and I have in common? We don’t play well with others…
First up was… Read More
Talk about an unusual position. Intel finds themselves very much currently outside when it comes to mobile SoCs for phones and tablets. After several attempts at soul-searching and a true understanding of the term “low-power” (not meaning 3W, but instead < 1W), they finally have a part – in the form of “Medfield”, aka the Atom… Read More
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Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot