I will see you at the Substrate Vision Summit in Santa ClaraWIth packaging being one of the top sources…Read More
The Immensity of Software Development and the Challenges of Debugging Series (Part 4 of 4)The Impact of AI on Software and Hardware…Read More
Alchip is Paving the Way to Future 3D Design InnovationAt the recent TSMC OIP Ecosystem Forum in…Read More
Jasper has three seminars coming up in May in Hsinchu (Taiwan), Beijing and Shanghai. These are full-day seminars on how to solve critical verification challenges using state-of-the-art formal technology. Breakfast and lunch will be served.
This full-day tutorial will be given by technical experts for verification experts… Read More
You have probably heard something about ARM’s big.LITTLE architecture. This links a Cortex-A15 multi-core CPU with a Cortex-A7 CPU. The A15 is a high-performance processor and the A7 is a very low power processor. The basic idea is that when high-performance is required (playing a graphical video game on your smartphone,… Read More
Extrapolating the trends from last 20 years to the next ten suggests that we will be implementing a trillion transistors or more by 2020. At 20nm, with the chip sizes touching billions of transistors, the age old problem of how to implement a design in the most efficient manner remains unanswered. … Read More
I started a forum discussion about running Schematic Capture and SPICE on an iPad back in January, since then I bought an iPad 3rd generation and tried out that app.
It was easy to visit the App store, find the Spicy Schematic Capture app, download and start learning how to use their schematic and SPICE circuit simulator.… Read More
The technical program for DAC 2012 has an exceptional quality of technical papers, panels, special sessions, WACI (Wild and Crazy Ideas), WIP (Work In Progress), full day tutorials and user-track. The program is tailored for researchers and developers focused on electronic design automation (EDA) and embedded systems and … Read More
As I mentioned in my previous blog “NVIDIA Claims TSMC 20nm will not Scale?” Jen-Hsun Huang is a very entertaining guy. I always listen to the NVIDIA conference calls because you never know what he will say next. Clearly he is a smart guy so you have to ask yourself why all the rhetoric?
In the Forbes article NVIDIA: Intel should let us… Read More
I first met Betty Pokerwinski of Qualcomm at LinkedIn in the group called IC Layout Designers. I post frequently on LinkedIn and a blog article on an EDA tool called Visual Design Diff from ClioSoft created quite a discussion, enough so that I contacted Betty to learn more about her IC layout group at Qualcomm.
Questions and Answers… Read More
Part I (here) looked at a bit of the history of scripting, makefiles and other approaches to more formally specify and institutionalize EDA design flows.
The most sophisticated tool I know that looks at this issue is RTDA’s FlowTracer.… Read More
As Apple begins to flood the market with a full line of mobile devices sporting 4G LTE communications capability, starting with the iPAD and soon to follow with Ivy Bridge based MAC Book Pros and then in the Fall with iPhone 5s, one has to ask will the carriers be able to keep pace in order for customers to have a satisfied user experience.… Read More
These days, the flows that are used to build semiconductor designs are rightly regarded as part of the intellectual property of the company that developed and used them.
But it didn’t always used to be that way.… Read More
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