Those who have read the numerous articles I have written about MIPI, or PCIe, or the fusion of both named “Mobile Express” know my position: the question is not “Will Mobile devices support PCI Express?” but “When will we see Mobile devices integrating Mobile Express?” I was not really surprised by the Press Release that Cadence … Read More
Revolutionizing Hardware Design Debugging with Time Travel TechnologyIn the semiconductor industry High-Level Synthesis (HLS) and…Read More
Addressing Silent Data Corruption (SDC) with In-System Embedded Deterministic TestingSilent Data Corruption (SDC) represents a critical challenge…Read More
TSMC's 6th ESG AWARD Receives over 5,800 Proposals, Igniting Sustainability PassionTaiwan Semiconductor Manufacturing Company has once again demonstrated…Read More
Tiling Support in SiFive's AI/ML Software Stack for RISC-V Vector-Matrix ExtensionAt the 2025 RISC-V Summit North America, Min…Read More
TSMC based 3D Chips: Socionext Achieves Two Successful Tape-Outs in Just Seven Months!Socionext’s recent run of rapid 3D-IC tape-outs is…Read MoreFormal Verification of Power Intent
I can’t imagine that any SoC today is designed without taking intense interest in how much power the chip will consume, whether it is destined for a mobile phone or tethered in a cloud datacenter. One challenge with power is that adding features like voltage islands or power-down areas require changes to the netlist such as… Read More
Margaret Butler: One Woman’s Life in Science
46 years in Computing, 1945-1991
Margaret (Kampschaefer) Butler was a pioneer in technology, a ground-breaking woman who graduated with a B.S in Mathematics and Statistics in 1944, and followed a fascinating career path in the public sector starting in the earliest days of computers and nuclear energy. One of the early female… Read More
Standard Cell Library Characterization
Standard cell library characterization has been around for decades, Synopsys has been offering Liberty NCXand Cadence has Virtuoso Foundation IP Characterization. What’s new is that Mentor Graphics acquired the Z Circuit technology for library characterization and has integrated it with the Eldo Classic circuit … Read More
Ensuring timing of Custom Designs with large embedded memories – A big burden has solution!
In 1990s when designs were small, I was seeing design and EDA community struggling to improve upon huge time taken to verify the circuits, specifically with Spice and the like. I was myself working on developing tool for transistor level static timing analysis (STA) mainly to gain on time (eliminating the need of exhaustive set … Read More
EDPS Monterey. Agenda Now Available
For 20 years there has been the Electronic Design Process Symposium. It has been held each April and for the last few years at least has always been in Monterey at the Monterey Beach Resort. This year it is Thursday and Friday April 18th/19th.
The keynote on the first day is by Ivo Bolsens of Xilinx on The All-programmable SoC —… Read More
RTDA at Altera
I talked to Yaron Kretchmer of Altera to find out how they are using RTDA’s products. I believe that Altera are the oldest customer of RTDA, dating back over 15 years, originally used by the operations team around the test floor before propagating out in the EDA and software worlds more recently.
Altera use two RTDA tools, LicenceMonitor… Read More
Samsung and the New World Order!
The keynotes at CDNLive today were very interesting, but rather than cover the slides and bullet points let me share with you my personal view of Samsung and how they are changing the semiconductor industry. Before I continue remember I’m just a blogger who shares observations, experiences, and opinions. This blog is for entertainment… Read More
Virtual Platforms, Acceleration, Emulation, FPGA Prototypes, Chips
At CDNLive today Frank Schirrmeister presented a nice overview of Cadence’s verification capabilities. The problem with verification is that you can’t have everything you want. What you really want is very fast runtimes, very accurate fidelity to the hardware and everything available very early in the design … Read More
Visually Debugging IC Designs for AMS and Mixed-Languages
With an HDL-based design methodology many IC engineers code in text languages like SystemVerilog and VHDL, so it’s only natural to use a text-based debug methodology. The expression that, “A picture is worth a thousand words” comes to my mind and in this case a visual debug approach is worth considering for … Read More


Quantum Advantage is About the Algorithm, not the Computer