The most common question that I get each year at DAC is, “So, what’s new?” When I reviewed the exhibitor list I was pleasantly surprised to see how many EDA, IP and AI companies were attending that I didn’t know about. Here’s just a quick preview of what to expect in Long Beach from July 27-29. I’ll be walking the exhibit floor, visiting companies and blogging in more detail, so stay tuned.
Agentic Design Automation where EDA tools are run to pursue goals, interpreting results, making decisions, adjusting, then iterating to meet objectives. GPU acceleration used with reinforcement learning.
They offer power, energy and thermal management tools. EnergyLab LITE does power simulations and run-time measurements for NXP i.MX evaluation boards. EnergyLab PRO uses an IDE for power simulations and run-time measurements of any HW and SW, like Xilinx boards. Seed Power Manager gives embedded software/firmware users the run-time power, energy, latency and thermal numbers.
Instead of point tool acceleration, this company offers an Intent Engine to keep the spec and decisions connected and current, an Execution Engine for all teammates to use across all tools, and a Knowledge Engine that learns from every project to make the next project start quicker.
This firm helps other companies build the AI-native semiconductor stack, with clients like: InPSY, Quaxys, Rise Design Automation, ModelCat, CraftiFAI, softweb solutions, yieldWerx, Glide Systems, Axiomise, Tuple Tech, MachineWare.
Helps to shield your microelectronics from Cyberattacks, with end-to-end microelectronics security from simulation to silicon.
Their PLM is both open and adaptable, used by companies like: Toyota, Renesas. Competes with PLM from Siemens, Dassault and PTC.
Has an AI lab for the compute stack, starting with chip design acceleration for HW/SW co-design.
Checks your PCB details with a more thorough ERC flow. Used by Tomorrow Lab, StarFish Medical, Igor Institute, SGW, Puzzle Medical.
Add security agents for silicon verification so that you can find and fix any security vulnerabilities earlier in the design flow, driven by AI.
If you want to manufacture an electronics product without component shortages, compliance gaps or production delays, then check out what Cofactor has in their electronics supply chain infrastructure.
Prototyping and emulation that spans from a single FPGA card, to enterprise prototyping with up to 128 FPGA environments. Their team has over 30 years experience in this field.
Benefit from specialized IP like: RF Beamformers, RF front-end modules, low-noise LDOs and XOs, and general purpose MCUs.
Receive RF turnkey products in hardware and software or training through AI-enhanced designs for wireless communication, radar and satellite applications. Aiora Artemis is an AI-assisted optimizer for RF EDA tuning and application. Touchstone Viewer Studio lets your engineers view, analyze and customize Touchstone files.
They have AI-driven aerodynamic optimization, photonic IC design, CFD simulation, electromagnetics (RF) simulation, and integrated photonics simulation.
Big claim of using just a five-person design team with agent leverage to produce what a fifty-person design team used to require, starting with spec input and providing tape-out data ready for silicon. Agents for DV regression triage, IP adoption and derivation, PPA design space exploration, Coverage closure.
AI-based tools for silicon designers using full-stack AI agents working with a web or desktop GUI, with an initial focus on analog, RF and custom circuits.
More AI-powered semiconductor design and verification tools, with a roadmap that includes a tapeout assistant, post-silicon debug and VLSI training.
Experience AI-powered decision making systems for your enterprise through GPU-accelerated computing, deep learning and reinforcement learning in the InstaDeep tool. Their technology could benefit fab engineers.
Expect to see AI-acceleration applied to silicon verification, circuit model creation and multi-physics simulation with their Discovery Platform. Analog circuit modeling is their first focus.
Promising to help your IC design team go from spec to tapeout in spite of talent scarcity, complexity and time crunch. Tool roadmap includes: VerifAgent, DebugAgent, CoverageAgent, SpecAgent, SOCVerify.
AI optimization software to speed the design of analog ICs with the Spaceman tool to automated analog block sizing inside an existing EDA flow.
Offering a stack for complex IP and SoC verification, where you need to generate collateral from specs, speeding up the signoff process, finding edge cases that general purpose LLM and engineers miss.
The Oboe FPGA prototyping system lets you go from RTL to prototype in just minutes, accelerating verification and bug hunting, measure performance on real workloads and make architecture comparisons.
AI acceleration applied to PCB layout, producing results in just hours, not months by using a physics-driven approach to PCB placement and routing.
DRC and LVS for large chips takes a big effort, so Ramtera has a new approach for physical verification that claims to be both fast and accurate.
Quite the pedigree with talent from Google DeepMind, Anthropic, NVIDIA, Cadence, Apple, xAI, Stanford, MIT and Harvard. They are a frontier AI lab working on a self-improving system to speed chip design with $335M in startup money.
This company has AI hardware agents that can design, verify, debug and even document a semiconductor system, with a future promise of collaboration and autonomy.
One of the few startups with customer names like Tenstorrent and SiFive, this company enables frontend digital design teams to build better SoC and IPs faster with Silimate by autonomously finding and fixing critical front-end issues in a design.
With SuiEM you get EM extraction, analysis and optimization tools for complex modeling and simulation. Applications include 5G, RF/wireless systems, 3-D multi-die packaging and assemblies.
An approach to use spec-first agentic AI to turn specifications into RTL and executable verification plans, testbenches, assertions and coverage closure workflow.
Design Conductor is an autonomous agentic system using frontier models to design semiconductors end-to-end, from concept to GDS II.
In development are models and agents that can learn, evaluate, plan, experiment and interact with the physical world. Founders hail from Stanford, SAIL Researchers, Synopsys, Globalfoundries, Cadence.
Summary
This may be the largest collection of startup companies that I recall seeing at one DAC, so my time will be spent getting to learn more about some of these companies. In this list we see much AI technology, so let’s see how it gets proven in the field by design and verification teams. I hope to see you at DAC next month in California, and stop me in the halls to say hello, I’ll be carrying an iPad and looking to hear your thoughts on the industry.
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