While the SPIE Advanced Lithography conference is best known for IC manufacturing, computational lithography, mask preparation and other back-end topics, there is also a significant amount of interest in Design for Manufacturing (DFM) at the conference because some litho issues are best (or only) addressed by modifying the… Read More
PSS and UVM Work Together for System-Level VerificationIn the early days of the PSS rollout,…Read More
Will 50% of New High Performance Computing (HPC) Chip Designs be Multi-Die in 2025?Predictions in technology adoption often hinge on a…Read More
Webinar: Achieve Full Flow and Resource Management Visibility to Optimize Cost and Sustainability with InnovaThe lifecycle for complex chip design includes many…Read More
Design team in China also lead Network-on-Chip adoption…
I have mentioned NoC adoption explosion during the last two years, illustrated by the huge growth in revenue of a company like Arteris: if we consider only revenue coming from upfront license sales (not including royalties), Arteris growth has been geometric between 2011 and 2010, passing from 18 to 39 customers, which is more … Read More
A Brief History of Tanner EDA
While founder John Tanner, PhD, got his initial exposure to the TTL Cookbook and CMOS Cookbook as an undergraduate, it was his experience as a Caltech graduate student that forged his early path in EDA. In 1979, while enrolled in a VLSI design course at Caltech, John and his classmates received a pre-print of Carver Mead’s seminal… Read More
Time in a model: xtUML and concurrency
Most embedded programming strategies involve decomposing the embedded application into chunks, which can then be executed as independent tasks. More advanced applications involve some type of data flow, and may attempt to execute operations in parallel where possible.… Read More
Cadence, Synopsys, and Mentor on FinFETs
In my opinion, FinFETs will be the most significant piece of technology we, as semiconductor ecosystem people, will experience this decade. Seriously this is exciting stuff and one of the top search terms on SemiWiki for 6 months running. Here is a quick peek at what the top EDA companies will be talking about at the Common Platform… Read More
How GLOBALFOUNDRIES is Differentiating in 2013
GLOBALFOUNDRIES changed the landscape of the foundry business in 2009 with a simple but ambitious plan to become the world’s first truly global foundry. At the Common Platform Technology Forum February 5th in the Santa Clara Convention Center GF Executive Vice President Michael Noonen will give an update on how that is … Read More
High Performance or Cycle Accuracy? You can have both
SoC designers have always wanted to simulate hardware and software together during new product development, so one practical question has been how to trade off performance versus accuracy when creating an early model of the hardware. The creative minds at Carbon Design Systems and ARM have combined to offer us some hope and relief… Read More
Apple Makes More on iPhone Than Samsung on Everything
Apple’s stock is down 10% after they announced “disappointing” results. They are only disappointing in the sense that some analysts expected even bigger profits. At $13.08 billion it is the largest quarterly profit for any corporation that is not in the oil business ever. According to wikipedia, even the … Read More
A Brief History of Sidense
Sidense Corp. is a leading developer of embedded non-volatile memory (NVM) intellectual property (IP) for the semiconductor IC market. The company is headquartered in Ottawa, Canada, and has a global presence with sales offices worldwide.
The company was founded in 2004 by CTO Wlodek Kurjanowicz, a MoSys fellow and co-founder… Read More
Power, Signal and Thermal Updates from ANSYS at DesignCon
DesignConis next week in Santa Clara, so today I spoke with Mark Ravenstahlfrom ANSYS to get an idea of what to expect at the conference and trade show.
Will 50% of New High Performance Computing (HPC) Chip Designs be Multi-Die in 2025?