CAST Compression IP Webinar 800x100 (2)

DAC: Calypto Insight Presentation

DAC: Calypto Insight Presentation
by Paul McLellan on 05-01-2013 at 5:39 pm

DAC has several “Insight Presentations” on Wednesday June 5th. Bryan Bowyer from Calypto will be presenting from 2-4pm that day (don’t know where, the DAC website doesn’t have a room number specified yet). The topic is Reducing Design and Debug Time with Synthesizable TLM. TLM, of course, stands for… Read More


DAC Keynotes: 5 This Year

DAC Keynotes: 5 This Year
by Paul McLellan on 05-01-2013 at 2:38 pm

DAC is in Austin this year, as I’m sure you know, and DAC has keynotes by CEOs of two Austin-based companies Freescale Semiconductor and National Instrument. Two more keynotes (one split into two) are focused on mobile, which has become the major driver of semiconductor today. A fifth keynote, including presentation of … Read More


Accelerating Design Debug in an ASIC Prototype

Accelerating Design Debug in an ASIC Prototype
by Daniel Nenni on 04-30-2013 at 8:15 pm

ASIC prototyping in FPGAs is starting to trend on SemiWiki. As FPGA technology becomes more advanced customers tell me that the traditional debug tools are inadequate. Faced with the very restrictive debugging capabilities and very long synthesis/place/route times the debugging cycle in these prototype platforms are quite… Read More


(Must Read) Arteris Blog activity: IP, 20 nm node and CTO interview

(Must Read) Arteris Blog activity: IP, 20 nm node and CTO interview
by Eric Esteve on 04-30-2013 at 8:10 pm

I just read three very interesting blogs from Arteris. In the first “The Semiconductor Industry Needs an IP Switzerland”, Kurt Shuler, VP of Marketing for Arteris, enjoys about the fact that four big IP players (ARM, Synopsys, Imagination and Cadence) are emerging after years of fragmentation within the semiconductor IP industry.… Read More


Crossfire – Builds Quality with Design

Crossfire – Builds Quality with Design
by Pawan Fangaria on 04-30-2013 at 8:05 pm

Very often we talk about increasing design complexities and verification challenges of SoCs. With ever growing design sizes and multiple IPs on a single SoC, it’s a fact that SoC design has become heterogeneous, being developed by multiple teams, either in-house or outsourced. Considering economic advantage amid pressure … Read More


A Programmable Electrical Rule Checker

A Programmable Electrical Rule Checker
by Daniel Payne on 04-29-2013 at 11:21 pm

IC designers involved with physical design are familiar with acronyms like DRC (Design Rule Check), LVS (Layout Versus Schematic) and DFM (Design For Manufacturing), but how would you go about checking for compliance with ESD (Electro Static Discharge) rules? You may be able to kludge something together with your DRC tool and… Read More


Recovery in 2013 Semiconductor Capex

Recovery in 2013 Semiconductor Capex
by Bill Jewell on 04-29-2013 at 11:00 pm

Semiconductor manufacturing equipment has been on an upswing for the last few months. Combined data from Semiconductor Equipment and Materials International (SEMI) and Semiconductor Equipment Association of Japan (SEAJ) shows three-month-average bookings have increased for five consecutive months through March 2013.… Read More


Hot Topic – CMOS Image Sensor Verification!

Hot Topic – CMOS Image Sensor Verification!
by Daniel Nenni on 04-29-2013 at 7:30 pm

Mobile applications require CMOS image sensor devices that have a low signal-to-noise ratio (SNR), low power, small area, high resolution, high dynamic range, and high frame rate. CMOS image sensor imaging performance is noise limited requiring accurate noise analysis on the pixel array electronics and column readout circuitry.… Read More


Beyond one FPGA comfort zone

Beyond one FPGA comfort zone
by Don Dingee on 04-29-2013 at 5:00 pm

Unless you are a small company with one design team, the chance you have standardized on one FPGA vendor for all your needs, forever and ever, is unlikely. No doubt you probably have a favorite, because of the specific class of part you use most often or the tool you are most familiar with, but I’d bet you use more than one FPGA vendor routinely.… Read More


Transient Noise Analysis (TNA)

Transient Noise Analysis (TNA)
by Rupindermand on 04-29-2013 at 4:21 pm

Tanner EDA Applications Engineers see a broad range of technical challenges that our users are trying to overcome. Here’s one worth sharing – it deals with transient noise analysis (TNA) for a comparator design. The customer is a producer of advanced flow measurement devices for application in medicine and research. The designer… Read More