By Chris Mack, CTO, Fractilia 07.18.2025
The Stochastics resolution gap costs chipmakers billions in delayed yield ramps, compromised performance, and unrealized revenue at 2nm and below.
In semiconductor manufacturing, the laws of physics don’t negotiate. They don’t care about roadmaps or quarterly earnings. Currently, one of these laws is quietly rewriting the rules of high-volume manufacturing at the most advanced nodes.
It’s called stochastic variability – the randomness baked into processes as we operate at atomic and molecular scales. And it has opened up a resolution gap between what we can print in the lab and what we can reliably manufacture in the fab.
This “Stochastics Resolution Gap” is now costing chipmakers billions in delayed yield ramps, compromised performance, and unrealized revenue at the 2nm node and below. In this era of $20 billion fabs and wafer-thin margins for error, we can no longer afford to treat stochastics as an R&D curiosity or something to be addressed after we begin to ramp up. It’s time to address it with the seriousness and rigor it deserves.
The Stochastics Resolution Gap for EUV is on the order of 5 nm today. (Source: Fractilia)
When it comes to challenges, recent headlines dominated by geopolitical issues —export bans, import tariffs, and government subsidies — are reshaping the global semiconductor landscape.
As EE Times has reported, these political headwinds can impact global competition and semiconductor growth. But while geopolitics dominates the news, there’s another limit creeping in under the radar – one driven not by policy, but by physics.
With the adoption of EUV lithography, manufacturers have hit a new kind of wall. Despite the scanner’s optical capability to print sub-12nm features in R&D, high-volume manufacturing yields drop significantly before achieving those limits.
The culprit? Stochastics – random patterning errors like line-edge roughness (LER), local CD variation (LCDU), edge placement error (EPE), and breaking or bridging features (defects). These aren’t tool-calibration problems. They aren’t deposition non-uniformities, focus, or dose drifts. They are an unavoidable byproduct of trying to control individual molecules and photons, which only obey probabilistic laws.
The smaller the feature, the more pronounced the stochastic variation becomes. And unlike other process defects, these errors don’t scale even close to linearly. In one recent study, reducing the EUV feature size from 18nm to 16nm increased stochastic defectivity tenfold.¹
The most advanced tools in the world can print smaller features, but stochastics prevent those features from surviving on the fab floor. This is a Stochastics Resolution Gap.
The traditional process control methods, which rely on global averages and standard deviations, are ill-equipped to detect or mitigate these errors. Instead, we need a new model: one that is rooted in local statistics. Treat variability as a probability distribution to be managed, rather than minimizing it to a single value.
Here is where things become uncomfortable for many fabs, as managing stochastic variation requires facing it head-on. It means measuring it precisely, modeling it accurately, and designing processes that account for its statistical nature.
In short, it means rethinking the way we approach design and manufacturing. It is not news to many in the semiconductor industry, but the full import of this change in perspective has yet to be felt.
The Fractilia Inverse Linescan Model (FILM) technology eliminates the noise bias in SEM measurements and reveals the true nature of stochastic effects – with the kind of accuracy and precision needed to build predictive probabilistic models and close the loop between design, patterning, and yield.
The whitepaper, “Closing the Stochastics Resolution Gap,” sets out to quantify not only the problem but also the opportunity. While this gap is real, it’s not immutable.
With improved measurement and modeling, fabs may selectively choose higher-dose exposures to suppress photon shot noise. Fabs can select resists with better absorption profiles. They can design etch processes that smooth rather than amplify roughness. Furthermore, they can use optical proximity correction (OPC) and design rules that account for local stochastics, not just global variations. And they can apply process control that distinguishes between local randomness and global drift. They can find the stochastics metrics that correlate with yield and performance.
All of this is possible, but only if we stop treating stochastics as a nuisance that impedes our existing approaches and start addressing it as a core manufacturing challenge.
We’ve already seen manufacturers reach 12nm half-pitch in the lab using EUV tools. But in production, most are stuck at 16–18nm. That 4-6nm gap doesn’t sound like much until you realize how much chip area it represents, how many more dice could fit per wafer, and how much faster a design could run. Then it adds up to lost revenue. Fast.
The tragedy is that most fabs still don’t measure stochastics correctly in their production lines. Not because they don’t care, but because they’ve lacked the tools to do so. That’s changing.
By providing process engineers, designers, OPC teams, and suppliers with a shared language to describe random variability and quantify its impact, we’re seeing entire organizations become smarter and faster. People are making better decisions because they’re finally working with real, unbiased data. When the etch team and the litho team are in the same room, they no longer have to argue about the data and its interpretation; they can focus on developing solutions.
In an industry that thrives on optimization, this is long overdue.
There’s a lot of talk about who will win the 2nm and below race. In my opinion, the winners will be those who understand—and control—the randomness that resides at the edge of resolution.
Chris A. Mack is recognized worldwide as a leading expert in lithography and pattern roughness. In 2003 he received the SEMI Award for North America for his efforts in lithography simulation and education and in 2009 he received the SPIE Frits Zernike Award for Microlithography, the industry’s most prestigious lithography award.
The Stochastics resolution gap costs chipmakers billions in delayed yield ramps, compromised performance, and unrealized revenue at 2nm and below.
In semiconductor manufacturing, the laws of physics don’t negotiate. They don’t care about roadmaps or quarterly earnings. Currently, one of these laws is quietly rewriting the rules of high-volume manufacturing at the most advanced nodes.
It’s called stochastic variability – the randomness baked into processes as we operate at atomic and molecular scales. And it has opened up a resolution gap between what we can print in the lab and what we can reliably manufacture in the fab.
This “Stochastics Resolution Gap” is now costing chipmakers billions in delayed yield ramps, compromised performance, and unrealized revenue at the 2nm node and below. In this era of $20 billion fabs and wafer-thin margins for error, we can no longer afford to treat stochastics as an R&D curiosity or something to be addressed after we begin to ramp up. It’s time to address it with the seriousness and rigor it deserves.
The Stochastics Resolution Gap for EUV is on the order of 5 nm today. (Source: Fractilia)
When it comes to challenges, recent headlines dominated by geopolitical issues —export bans, import tariffs, and government subsidies — are reshaping the global semiconductor landscape.
As EE Times has reported, these political headwinds can impact global competition and semiconductor growth. But while geopolitics dominates the news, there’s another limit creeping in under the radar – one driven not by policy, but by physics.
Hidden barrier to scaling
For decades, scaling followed a well-worn formula: shrink the pattern, fix the process variations, ramp the yield, ship the chips. And while there were bumps along the way, the basic model held – until it didn’t.With the adoption of EUV lithography, manufacturers have hit a new kind of wall. Despite the scanner’s optical capability to print sub-12nm features in R&D, high-volume manufacturing yields drop significantly before achieving those limits.
The culprit? Stochastics – random patterning errors like line-edge roughness (LER), local CD variation (LCDU), edge placement error (EPE), and breaking or bridging features (defects). These aren’t tool-calibration problems. They aren’t deposition non-uniformities, focus, or dose drifts. They are an unavoidable byproduct of trying to control individual molecules and photons, which only obey probabilistic laws.
The smaller the feature, the more pronounced the stochastic variation becomes. And unlike other process defects, these errors don’t scale even close to linearly. In one recent study, reducing the EUV feature size from 18nm to 16nm increased stochastic defectivity tenfold.¹
The most advanced tools in the world can print smaller features, but stochastics prevent those features from surviving on the fab floor. This is a Stochastics Resolution Gap.
Different kind of variability
The chip industry has spent decades perfecting its control over systematic process variation and defects that come from identifiable sources. However, stochastic variability is something entirely different. You cannot reduce stochastic defects by identifying and eliminating their sources. They are inherently random, making them unrepeatable. It unfolds in a probability space that can be understood and characterized, albeit not in the traditional sense.The traditional process control methods, which rely on global averages and standard deviations, are ill-equipped to detect or mitigate these errors. Instead, we need a new model: one that is rooted in local statistics. Treat variability as a probability distribution to be managed, rather than minimizing it to a single value.
Here is where things become uncomfortable for many fabs, as managing stochastic variation requires facing it head-on. It means measuring it precisely, modeling it accurately, and designing processes that account for its statistical nature.
In short, it means rethinking the way we approach design and manufacturing. It is not news to many in the semiconductor industry, but the full import of this change in perspective has yet to be felt.
Bridging the stochastics gap
The work done by Fractilia over the last eight years has resulted in metrology methods that allow fabs to do exactly that – adopt a fully stochastics perspective.The Fractilia Inverse Linescan Model (FILM) technology eliminates the noise bias in SEM measurements and reveals the true nature of stochastic effects – with the kind of accuracy and precision needed to build predictive probabilistic models and close the loop between design, patterning, and yield.
The whitepaper, “Closing the Stochastics Resolution Gap,” sets out to quantify not only the problem but also the opportunity. While this gap is real, it’s not immutable.
With improved measurement and modeling, fabs may selectively choose higher-dose exposures to suppress photon shot noise. Fabs can select resists with better absorption profiles. They can design etch processes that smooth rather than amplify roughness. Furthermore, they can use optical proximity correction (OPC) and design rules that account for local stochastics, not just global variations. And they can apply process control that distinguishes between local randomness and global drift. They can find the stochastics metrics that correlate with yield and performance.
All of this is possible, but only if we stop treating stochastics as a nuisance that impedes our existing approaches and start addressing it as a core manufacturing challenge.
Cost of doing nothing
Consider a fab running at 2nm that is unable to use its scanner’s full resolution potential because of stochastic defects. Vast amounts of money are being left on the table with fewer dies per wafer, slower yield ramps, extra mask spins, and performance-reducing design compromises.We’ve already seen manufacturers reach 12nm half-pitch in the lab using EUV tools. But in production, most are stuck at 16–18nm. That 4-6nm gap doesn’t sound like much until you realize how much chip area it represents, how many more dice could fit per wafer, and how much faster a design could run. Then it adds up to lost revenue. Fast.
The tragedy is that most fabs still don’t measure stochastics correctly in their production lines. Not because they don’t care, but because they’ve lacked the tools to do so. That’s changing.
New language for yield
One of the most surprising results of deploying stochastic metrology in advanced fabs is not just the improvement in yield – it’s the improvement in collaboration.By providing process engineers, designers, OPC teams, and suppliers with a shared language to describe random variability and quantify its impact, we’re seeing entire organizations become smarter and faster. People are making better decisions because they’re finally working with real, unbiased data. When the etch team and the litho team are in the same room, they no longer have to argue about the data and its interpretation; they can focus on developing solutions.
In an industry that thrives on optimization, this is long overdue.
The bottom line
Stochastic variability is no longer a fringe concern; it’s the defining challenge of advanced semiconductor manufacturing. The companies that recognize this – and act on it – will lead the next generation of scaling. Those that don’t will find themselves fighting physics with hope, telling their engineers to work harder.There’s a lot of talk about who will win the 2nm and below race. In my opinion, the winners will be those who understand—and control—the randomness that resides at the edge of resolution.
- 1. Yi-Pei Tsai, Chieh-Miao Chang, Yi-Han Chang, Apoorva Oak, Darko Trivkovic, Ryoung-Han Kim, “Study of EUV stochastic defect on wafer yield,” Proc. SPIE 12954, DTCO and Computational Patterning III, 1295404 (10 April 2024); https://doi.org/10.1117/12.3010858.
Chris A. Mack is recognized worldwide as a leading expert in lithography and pattern roughness. In 2003 he received the SEMI Award for North America for his efforts in lithography simulation and education and in 2009 he received the SPIE Frits Zernike Award for Microlithography, the industry’s most prestigious lithography award.
