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Let the FinFET Yield Controversy Begin!

Let the FinFET Yield Controversy Begin!
by Daniel Nenni on 11-03-2014 at 8:00 am

It never ceases to amaze me how people point fingers and create controversy to cover their mistakes. It happened at 40nm, 28nm, and again at 20nm and now it is time for the regularly scheduled yield controversy. Of course any conversation about semiconductor yield generates clicks for SemiWiki so I’m happy to play along.

It generally… Read More


DAC Deadlines: Action This Day

DAC Deadlines: Action This Day
by Paul McLellan on 11-02-2014 at 7:00 am

DAC is coming up. OK, it’s not actually until next June. It is June 7-11th 2015 at the Moscone Center here in San Francisco. But there are lots of important deadlines coming up for papers, panels and more. The 52[SUP]nd[/SUP] DAC will focus on five key tracks:

  • automotive
  • IP design
  • embedded systems
  • hardware/software security
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Semiconductor IP Forecast 2014 – 2020

Semiconductor IP Forecast 2014 – 2020
by Daniel Nenni on 11-01-2014 at 10:00 pm

Given that the majority of my 30+ years in Silicon Valley has revolved around semiconductor IP it should be of no surprise that IP is a big part of SemiWiki and our first book “Fabless: The Transformation of the Semiconductor Industry”. That is also why one of my first round blogger draft choices was IP expert Dr. Eric Esteve. Eric has… Read More


What Presentations to Attend During IP-SoC 2014 ?

What Presentations to Attend During IP-SoC 2014 ?
by Eric Esteve on 11-01-2014 at 11:00 am

Will you go to Grenoble next week to attend to IP-SoC? I will do it and will certainly listen to these Keynote Talks:

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Noise & Reliability of FinFET Designs – Success Stories!

Noise & Reliability of FinFET Designs – Success Stories!
by Pawan Fangaria on 11-01-2014 at 7:00 am

I think by now there has been good level of discussion on FinFET technology at sub-20 nm process nodes and this is an answer to ultra dense, high performance, low power, and billion+ gate SoC designs within the same area. However, it comes with some of the key challenges with respect to power, noise and reliability of the design. A FinFET… Read More


Debugging a 10 bit SAR ADC

Debugging a 10 bit SAR ADC
by Daniel Payne on 10-31-2014 at 4:00 pm

SMIC (Semiconductor Manufacturing International Corporation) is a China-based foundry with technology ranging from 0.35 micron to 28 nm, and we’ve blogged about them before on SemiWiki. I’ve been reading about SMIC recently because they created a technical presentation for the MunEDA Technical Forum Shanghai… Read More


GNSS, dead reckoning, and MEMS IMUs

GNSS, dead reckoning, and MEMS IMUs
by Don Dingee on 10-31-2014 at 4:00 pm

GNSS is a wonderful invention, and low cost receivers have crept into smartphones and other mobile devices. However, GNSS does not solve all problems, especially in urban environments. The canyon effect blocks signals at street level between tall buildings, and signals do not penetrate to the interior of parking garages, tunnels,… Read More


Effective Bug Tracking with IP Sub-systems

Effective Bug Tracking with IP Sub-systems
by Daniel Payne on 10-31-2014 at 7:00 am

Designing an SoC sounds way more exciting than bug tracking, but let’s face it – any bug has the potential to make your silicon fail, so we need to take a serious look at the approaches to bug tracking. When using an IP or an IP subsystem in a design, the SoC integrators require some critical knowledge about this IP. The actual… Read More


Silvaco at the TSMC 2014 Open Innovation Platform

Silvaco at the TSMC 2014 Open Innovation Platform
by Daniel Payne on 10-31-2014 at 7:00 am

The success of our semiconductor eco-system depends on collaboration, so the annual TSMC OIP Event just held on September 30 at the San Jose Convention Center was a prime example of that. I didn’t attend this year, but I did follow up with Amit Nandaof Silvaco this week to hear about what they presented. As a consultant I’ve… Read More


Improving Verification by Combining Emulation with ABV

Improving Verification by Combining Emulation with ABV
by Tom Simon on 10-30-2014 at 4:00 pm

Chip deadlines and the time to achieve sufficient verification coverage run continuously in a tight loop like a dog chasing its tail. Naturally it is exciting when innovative technologies can be combined so that verification can gain an advantage. Software based design simulators have been the mainstay of verification methodologies.… Read More