Designers tend to put tons of energy into pre-silicon verification of SoCs, with millions of dollars on the line if a piece of silicon fails due to a design flaw. Are programmable logic designers, particularly those working with an SoC such as the Xilinx Zynq, flirting with danger by not putting enough effort into verification?… Read More





Semiconductors negative in 2016, positive in 2017
Note: the table and text below have been revised from an earlier post to correct the numbers for STMicroelectronics.
Semiconductor companies posted a wide range of results in 2nd quarter 2016. Intel, Micron Technology and Renesas Electronics all had declines in revenue in 2Q 2016 versus 1Q 2016. Samsung Semiconductor, Qualcomm… Read More
Design IP Growth Is Fueling 94% of EDA Expansion
Last June, the ESD Alliance (ESDA) has released Q1 2016 results for EDA (CAE, PCB & MCM and IC Physical), Silicon IP (SIP) and Services. Not a surprise for Semiwiki readers since 2013, the SIP category is recognized as the largest with $689 million revenues for the quarter, and four-quarters moving average increasing by 11.6… Read More
Solido Saves Silicon with Six Sigma Simulation
When pushing the boundaries of power and performance in leading edge memory designs, yield is always an issue. The only way to ensure that memory chips will yield is through aggressive simulation, especially at process corners to predict the effects of variation. In a recent video posted on the Solido website, John Barth of Invecas… Read More
Are Your Transistor Models Good Enough?
SoC designers can now capture their design ideas with high-level languages like C and SystemC, then synthesize those abstractions down into RTL code or gates, however in the end the physical IC is implemented using cell libraries made up of transistors. Circuit designers use simulation tools like SPICE on these transistor-level… Read More
Real Artificial Neurons
Neural nets are a hot topic these days and encourage us to think of solutions to complex tasks like image recognition in terms of how the human brain handles that task. But our model today for this neuromorphic computing is several steps removed from how neurons actually work. We’re still using conventional digital computation … Read More
Semi execs look at IoT tradeoffs a bit differently
What happens when you get a panel of four executives together with an industry-leading journalist to discuss tradeoffs in IoT designs? After the obligatory introductions, Ed Sperling took this group into questions on power, performance, and integration.… Read More
Rigid-Flex Cabling is Cool! (and requires unique EDA support)
The three F’s of electronic product development are: form, fit, and function. Although the F/F/F assessment typically refers to the selection of the right component, it most definitely also refers to the selection of the proper cabling between assemblies. The requirements for cables are varied, and demanding: ability… Read More
Catching low-power simulation bugs earlier and faster
I’ve owned and used many generations of cell phones, starting back in the 1980’s with the Motorola DynaTAC phone and the biggest usability factor has always been the battery life, just how many hours of standby time will this phone provide and how many minutes of actual talk time before the battery needs to be recharged… Read More
Further delays in KLAM deal not a good omen
Deal likely getting worse as time & remedies go by…
Just a couple of short weeks ago on the earnings conference call, Lam management was adamant about the KLAM deal getting done and done by the Oct 20th deadline. Martin Anstice, the CEO , went to great lengths to tell us that the deal was under control, was going to happen, … Read More
Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet