Audi announced its piloted driving technology at CES 2015. The Audi Prologue includes the Advanced Driver Assistance System Platform (zFAS), co-developed with TTTech. The zFAS board is based on four devices: an Nvidia k1 processor and Infineon Aurix processor, Mobileye’s EyeQ3 for vision processing, and an Altera Cyclone … Read More




100 Million Miles Per Hour!
Back When We Loved Discovery
As anyone who reads and follows my blog posts will know, I’m a believer in innovation. It’s what drives my passion for the Internet of Things. That interest started when I was an “Apollo” kid during the 1960’s and 1970’s. Those decades offered a very different landscape for creativity, exploration and… Read More
Scalable Infrastructure for Digital Businesses
Building Digital businesses is tough. The run-time changes rapidly (browser – apps – bots), and standards for the digital architecture/stack gets refined constantly. Pace of innovation is accelerating due to massive war-chest of the top digital players like Google, Facebook, Apple and Amazon. For the Fortune… Read More
Will TSMC be alone at 10nm and 7nm?!?!?
Now that the dust has settled let’s talk about the recent TSMC OIP Ecosystem Forum. This was the 6[SUP]th[/SUP] annual OIP which hosts more than 1,000 attendees from TSMC’s top customers and partners. Presenting this year were TSMC VP and CTO Dr. Jack Sun, TSMC VP of R&D Dr. Cliff Hou, and ARM EVP of Incubation Businesses Dr. Dipesh… Read More
CCIX shows up in ARM CMN-600 interconnect
All the hubbub about FPGA-accelerated servers prompts a big question about cache coherency. Performance gains from external acceleration hardware can be wiped out if the system CPU cluster is frequently taking hits from cache misses after data is worked on by an accelerator.
ARM’s latest third-generation CoreLink CMN-600 … Read More
Meet the POWER9 Chip Family
When you looked at a chip in the past you primarily were concerned with two things: the speed of the chip, usually expressed in GHz, and how much power it consumed. Today the IBM engineers preparing the newest POWER chip, the 14nm POWER9, are tweaking the chips for the different workloads it might run, such as cognitive or cloud, and… Read More
Low power physical design in the age of FinFETs
Low power is now a goal for most digital circuit designs. This is to reduce costs for packaging, cooling, and electricity; to increase battery life; and to improve performance without overheating. I talked to the experts on physical design for ultra-low power at Mentor Graphics recently about the challenges to P&R tools and… Read More
Cadence DSPs float for efficiency in complex apps
Floating-point computation has been a staple of mainframe, minicomputer, supercomputer, workstation, and PC platforms for decades. Almost all modern microprocessor IP supports the IEEE 754 floating-point standard. Embedded design, for reasons of power and area and thereby cost, often eschews floating-point hardware… Read More
16nm HBM Implementation Presentation Highlights CoWoS During TSMC’s OIP
Once a year, during the TSMC’s Open Innovation Platform (OIP) Forum you can expect to see cutting edge technical achievements by TSMC and their partners. This year was no exception, with Open-Silicon presenting its accomplishments in implementing an HBM reference design in 16nm. It’s well understood that HBM offers huge benefits… Read More
Power Exploration at RTL Design with Mentor PowerPro
There was a comment recently that design for low power is not an event, it’s a process; that comment is absolutely correct. Power is affected by everything in the electronic ecosystem, from application software all the way down to layout and process choices. Yet power as a metric is much more challenging to model and control than … Read More
Weebit Nano Moves into the Mainstream with Customer Adoption