I. Introduction
In the FinFET and DUV era, considering the need for multiple exposures (more than 4 photomasks) in photolithography processes, the difficulty of FEOL lies in the fin, MEOL in the contact and contact via, and BEOL in the layers before the metal line and the layers before the via.
For BEOL, the via is a circular hole pattern. In terms of process, it is more difficult to create than the line pattern, both in photolithography and etching. Therefore, although the pitch of the via in BEOL may not be as small as that of the metal line, the number of photomasks required can sometimes be similar. However, we will mainly discuss the metal line part below and will not mention the via.
II. 14nm/12nm Process
In 14nm/12nm processes, the first layer of BEOL is M1. Its characteristic is that its metal line direction is in both the X and Y directions, like the M1 in Samsung's 8nm process shown in Figure 2.
Generally speaking, from the emergence of 7nm to the present, the first layer of BEOL is M0, and each metal line is unidirectional and perpendicular to the next layer, as shown in the figure. However, before 7nm, the first layer was M1, which combined both horizontal and vertical directions.
As can be seen, the process methods used for each layer of 14/12nm are different. Because it is necessary to take into account both directions, including the process development time, the first three metal layers of 14nm use pitch split double exposure LELE (litho-etch-litho-etch) instead of SADP+cut mask.
At 12nm, the first layer M1 at 56nm still uses LELE, but theoretically, with M2 at 51nm, it should be close to the edge of using triple-exposure LELELE. However, the 12nm M2 is changed to unidirectional, and the first layer of BEOL usually has the highest layout complexity (e.g., tip-to-tip spacing requirements or pattern types). Therefore, although the pitch of the second layer M2 reaches 51nm, it can still use LELE.
PS. Generally, whether it's photolithography or etching, when it's necessary to accommodate two directional patterns or even line/hole patterns, the process performance will be compromised, and neither side will reach its best limit.
III. N+1/N+2 Processes and SADP vs SALELE
Entering the 7nm advanced nodes N+1 and N+2, BEOL begins to change so that the first layer starts from M0, and each layer is unidirectional, perpendicular to the next layer. N+1 and N+2 are roughly the same size. As mentioned before, N+2 is an improved version of N+1, and can be considered as N+1P. Within the smallest M0-M3 series, there is actually little difference between the two.
The manufacturing process is shown in the image above. Based on the actual decapsulated image, M0 has many complex and numerous small-sized tip-to-tip spacing breaks, with small intervals between these breaks. The manufacturing process should be 1 DUV SADP + 3 cut masks (4 exposures). M1 also has many densely packed small-sized breaks, and the manufacturing process is also 1 DUV SADP + 3 cut masks.
The tip-to-tip breaks in M2/M3 vary in size. Small breaks indicate that a cut mask is still needed, but their number is small and the spacing between them is large (meaning the cut mask does not need to be split into multiple photomasks). Therefore, the process will use three exposures of SALELE + 1 cut mask, in the order of Self-align Line 1 + cut mask + line 2. Most of the large breaks can be provided by line 1/line 2 itself.
Here we can also see that the process technology between N+1 and N+2 remains unchanged; it simply moves towards the smallest size achievable with each layer of exposure. You can think of N+1 as a conservative version, while N+2 further explores the potential of that process.
PS. Traditional SADP/SAQP, while achieving a very dense pitch with only one exposure, requires an additional cut/block mask for each breakpoint, regardless of its size. This can sometimes lead to issues with insufficient breakpoint spacing, necessitating mask splitting, even for large breakpoints.
SALELE, on the other hand, achieves double the pitch through two LELE exposures, while SADP only requires one. Its advantage over SADP is that if the breakpoint size requirement is not high, it can use the LE process itself to create the breakpoints. Therefore, even with small breakpoint requirements, the additional cut mask may not encounter breakpoint spacing issues requiring mask splitting (see Figure 4).
PS2. However, the SALELE method described above is a traditional approach. The difference between this type of salele and LELE is that Line 1 has a spacer, making it self-aligned. Its dimensions are protected by the spacer. Even if Line 2 has issues with the OVL or alignment of Line 1, it doesn't matter, as the space between Line 1 and Line 2 is defined by the spacer. Therefore, it's an improved version of LELE. (As shown in Figure 5, even though the light green Line 2 is almost touching the light blue Line 1, the actual spacing between lines after processing remains the same as the target value, defined by the Line 1 spacer.)
Unlike SADP/SAQP, this type of salele's spacer doesn't define the line pitch. Its pitch capability is derived from the pitch breakdown of LELE; the spacer is only used to protect Line 1.
IV. N+3 Process / TSMC DUV 5nm
However, if a self-aligned block (SAB) mask with high etch selectivity is used, it may be possible to achieve 1 DUV SAQP + 3 cut masks, maintaining 4 exposures with N+2.
The key point is whether to use a SAB with high etch selectivity.
Simply put, a SAB with high etch selectivity involves using different hard mask layers or backfilling with spacers of different etch material properties after the second spacer layer is deposited during SAQP. This allows different etch gases to be used to create breakpoints when the cut mask is opened, increasing the cut mask size without causing unexpected breakpoint damage and reducing the need for mask pitch splitting.
A detailed explanation is shown in Figure 6. Considering the pitch and tip-to-tip resolution of the cut mask pattern, the M0 of complex breakpoints needs to be split into four masks: cut mask 1, 2, 3, and 4. However, if the lines in the diagram become those in Figure 7 (different colored lines represent different etching resistance), then the number of cut masks needed to create the same breakpoint as in Figure 6 can be reduced to two. This is because the lines that can be etched are different when cut masks 1 and 2 are opened respectively, so the M0 layout with the same complex breakpoint can be obtained in the end.
Let's take the SAQP variant patent of Sicarrier in Figure 8 as an example. However, it puts the first cut mask in when the first spacer is formed. After the second spacer with different etching properties is backfilled, the second cut mask is used for selective cutting.
P.S. Although the patent from Sicarrier indicates that 28nm track pitch M0 can be achieved using 2 cut masks and a total of 3 DUVs, considering the requirements for tip-to-tip spacing, an example like the one in Figure (b) below may occur. Therefore, unless there are restrictions on customer design rules, 3 cut masks should be a more reasonable choice.
Furthermore, when discussing SAB, we must return to TSMC's 5nm DUV M0 (see image below, appearing in the 2019 IEDM paper). You can see that TSMC mentioned using 5 DUV layers, which reasonably suggests 1 SAQP layer + 4 cut masks. The image also shows only 4 tracks, while the actual N5 M0 uses 5 tracks with a 28nm pitch. Therefore, the track pitch of this full DUV version in the image is 35nm.
However, as you can see in the red box in the image below, the breakpoint shape looks very poor. This is because when the main pitch is reduced, in order to avoid cutting where it shouldn't break, the size of the mask to be exposed needs to be reduced, as shown in the image below. But reducing the immersion size will cause problems. Even if you want to make a rectangular pattern, when the length is reduced to a shorter rectangle, the actual exposed pattern will look like an ellipse or even a circle, such as the left side of Figure 11. This part is irrelevant no matter how OPC modifies the mask shape. Then, circular cuts will have potential problems, such as cutting out horns like the upper right diagram in Figure 11, or even cutting at an angle due to OVL displacement. This part may cause subsequent electrical or yield problems.
SAB cut can alleviate this problem because, as we mentioned above, different etching options can be used to make the cut mask pattern larger. This allows for a long, straight cut, as shown in the lower right diagram, ensuring that the cut size and shape are as expected.
Therefore, based on the above analysis, the M0 process of N+3 is divided into a pessimistic version with 5 exposures and an optimistic version with 4 exposures. Finally, let's return to the remaining M1/M2/M3 processes of N+3.
Although M1/M2 have the same 38nm pitch, the N+3 chips cut this time show that M1, like N+2, has very dense small-sized breakpoints. Its process is judged to be 1 DUV SAQP + 3 cut mask quadruple exposure. While M2 also has a 38nm pitch, the breakpoint size is larger and more spacious, with small breakpoints present but spaced far apart. Therefore, the process is judged to be SALELE + 1 cut mask triple exposure. Finally, the situation for M3 is the same as M2, with the process also being SALELE + 1 cut mask triple exposure.
V. N+3 Yield and Lithography Machine Requirements
Continuing from the above, considering only the BEOL metal line, the only thing that could potentially cause yield problems is the pessimistic version of M0 with 5 exposures. Four out of five exposures involving cut masks (LELELELE) not only introduce alignment issues, but the multiple etches and wets can also cause defects that negatively impact yield. Furthermore, the elliptical/circular cut patterns resulting from the 30nm mainline pitch also pose a problem.
Additionally, the two spacer depositions and etchings in SAQP present significant challenges in dimensional control. The pitch walk shown in the image is an example; the low yield of Intel 7 is rumored to be due to the difficulty in controlling SAQP. This puts SMIC's capabilities to the test.
Finally, there are the requirements for the lithography machine. In reality, the difficulty of SAQP lies more in the precision of the spacer deposition thickness and the dimensional control caused by multiple etching processes. These aspects may be higher than the control requirements of the first main line exposure in SAQP. Taking the N+3 BEOL metal line as an example, the only difference from N+2, requiring higher performance on the lithography machine, is probably the pessimistic version of the M0's five-fold exposure scenario.
Looking at the complete transition from FEOL to BEOL, compared with nodes like TSMC N7 and Intel 7 that were developed and mass-produced using NXT 1970/1980i, the N+3 fin pitch and CPP are not significantly smaller (see the initial N+3 density link for details). Therefore, for lithography, the remaining challenges might be:
(1) MEOL's contact and contact via. The via is uncertain, but because the cell height of the contact is reduced from 240nm in N7 to 228nm in N+3, the length in the Y direction will be smaller (while the pitch in the X direction remains the same at 57nm). (2) M0, as mentioned above, the pessimistic version requires one more exposure than N+2, and the resulting image may not be as good.
(3) The V0 via connecting M0/M1 to the BEOL may require one more exposure than the V0 via of N+2 (however, the number of exposures for the BEOL V0 of N+3 should not be higher than the contact via of N+2, so it may not be a major challenge for 1980i).
PS. The STD cell height/SRAM cell height is smaller than N7, indicating that N+3 may have a smaller MOS-MOS SP in the FEOL, but not by much, and it's not a particularly difficult point for DUV.
For the definition of MOS-MOS SP, please refer to the M0 knowledge link at the beginning above.
VI. Conclusion and Outlook
While the performance requirements for lithography machines in N+3 are indeed higher than in N+2 for some critical layers, the density remains the same. The critical dimension G57H228 doesn't offer a significant improvement over the G57H240 of the N7 family (N7/N7+/N6). SMIC openly has at least five 2000i and four 2050i lithography machines (the extent of their operational capacity is unknown), which is more than sufficient to handle the run capacity of those N+3 layers. Unless there are extremely unforeseen circumstances causing multiple machines to fail simultaneously, the lithography machine capacity should be adequate, even considering the PM time for each machine.
However, why does the yield rate for N+3 still appear so poor? As I mentioned above, besides the potentially higher requirements for lithography machines in a few critical layers, the increased number of layers required for SAQP (Self-Quality Processing) may also be a problem, introducing too many variables into process control.
Another recurring issue is that unless SMIC is technically inferior in MEOL (Metal-on-a-Loop) lithography, it's clear that SMIC can achieve 54nm CPP (Cell Proportion Processing) using the same Intel 7 chipset (1980i), while N+3 has only reached 57nm. Therefore, SMIC's slow CPP miniaturization isn't necessarily related to lithography machines, as mentioned before (see the MEOL/Performance & Power Consumption explanation above).
As for the recent article, even mentioning N3-level technology by 2027? Keep in mind that TSMC's N3 has nearly double the density of N+3. Given SMIC's slow progress in CPP/Cell height and the accompanying yield rate, do you find this reasonable and possible?
(Even Samsung's true SF3 only offers a ~60% density improvement compared to N+3…)
This N+3 125mtr incident has already taught everyone a lesson: many process rumors should be taken with a grain of salt. Only through actual process progress and analysis can we reliably predict future developments. My assessment of process evolution is as follows:
2027-2028 DUV version N+4 (used in products available in 2028-2029) —> 2028 EUV version N+4 (used in chips available in 2029) —> 2030 EUV version N+5 or 3nm chips