The difficulty of managing the power domains on a complex SoC led to the development of a power format file description, to serve as the repository for data needed for functional and electrical analysis (e.g., CPF, UPF). Yet, what about complex printed circuit boards? How can the power domain information be effectively represented… Read More



Searching for Extraterrestrials
Since the beginning of time, people on Earth have peered into the night sky, pondering if they were alone in the universe. Today, we have a large group of scientists that are working to answer that question. The precision required for their search often depends on the performance of a key piece of technology – the analog-to-digital… Read More
New Protocol (NB- IoT) Requires New DSP IP and New Business Model
If we agree on the definition of IoT as a distributed set of services based on sensing, sharing and controlling through new nodes, we realize that these nodes are a big hardware opportunity. The chip makers and IP vendors have to create innovative SoC, delivering high performance at low cost and low energy. Moreover, the new systems… Read More
What You Don’t Know about Parasitic Extraction for IC Design
Out of college my first job was doing circuit design at the transistor-level with Intel, and to get accurate SPICE netlists for simulation we had to manually count the squares of parasitic interconnect for diffusion, poly-silicon and metal layers. Talk about a burden and chance for mistakes, I’m so thankful that EDA companies… Read More
Power and Performance Optimization for Embedded FPGA’s
Last month, I made a “no-brainer” forecast that 2017 would be the year in which embedded FPGA (eFPGA) IP would emerge as a key differentiator for new SoC designs (link to the earlier article here).
The fusion of several technical and market factors are motivating design teams to incorporate programmable logic functionality… Read More
Zero Power Sensing
We’ve become pretty good at reducing power in IoT edge devices, to the point that some are expected to run for up to 10 years on a single battery charge. But what if you wanted to go lower still or if, perhaps, your design can’t push power down to a level that would meet that goal? One area in systems where it can be challenging to further … Read More
"Ten-hut!" Attending the Signal Integrity Bootcamp
The engineering team for the design and analysis of a complex system consists of a diverse set of skills — with the increasing emphasis on both high-speed interface design and multi-domain power management, a critical constituent of the team is the group of signal integrity (SI) and power integrity (PI) engineers.
The training… Read More
Plasmonics Integrates Photonics and Electronics
In the last year we have seen a marked increase in activity around the integrated photonics space, especially around silicon-based photonics. Last year the American Institute for Manufacturing of Photonics (better known as AIM Photonics) was started to boot-strap U.S. efforts in integrated photonics. We also saw multiple … Read More
Mentor gets Busy at DVCon
You’d expect Mentor to be covering a lot of bases at DVCon and you wouldn’t be wrong. They’re hosting tutorials, a lunch, papers, posters, there’s a panel and of course they’ll be on the exhibit floor. I’ll start with an important tutorial that you really should attend, Monday morning, on creating Portable Stimulus Models… Read More
CEO Interview: Srinath Anantharaman of ClioSoft
It will soon be 20 years since ClioSoft started its journey of selling design management software for the semiconductor industry. It was a slow start considering that designs were relatively small and only digital front-end designers had begun to realize the importance of version control and design management. With open source… Read More
Should Intel be Split in Half?