In a SemiWiki EXCLUSIVE – GLOBALFOUNDRIES has now disclosed the key metrics for their 7nm process. As I previously discussed in my 14nm, 16nm, 10nm and 7nm – What we know now blog GLOBALFOUNDRIES licensed their 14nm process from Samsung and decided to skip 10nm because they thought it would be a short-lived node. At 7nm GLOBALFOUNDRIES has taken advantage of the additional technical resources they acquired from IBM to develop their own process.
As Dan Nenni previously discussed in his GlobalFoundries 7nm and EUV Update! blog 7LP (Leading Performance) will offer a greater than 40% performance improvement relative to 14nm or greater than 60% lower power. Area scaling will be approximately 2x and the die cost reduction will be greater than 30%, with greater than 45% in target segments. Initial customer products on 7LP are expected to launch in the first half of 2018 with volume production in the second half of 2018.
The 7LP process will be produced with optical lithography and what we now know is the Contacted Poly Pitch (CPP) will be 56nm and the Minimum Metal Pitch (MMP) will be 40nm produced with Self-Aligned Double Patterning (SADP). A 6-track cell will be offered with a cell height of 240nm. The high density 6T SRAM cell size is 0.0269 microns squared. A 7LP+ process is also planned that will take advantage of EUV when it is ready to offer improved performance and density.
GLOBALFOUNDRIES is also in the unique position of providing an in-house ASIC platform FX-7 on their 7LP process. FX-7 provides a comprehensive suite of tailored interface IP including High Speed SerDes (60G, 112G), differentiated memory solutions including low-voltage SRAM, high-performance embedded TCAM, integrated DACs/ADCs, ARM processors, and advanced packaging options such as 2.5D/3D
Comparison to other processes
In my 14nm, 16nm, 10nm and 7nm – What we know now blog I looked at Intel’s 10nm process compared to Samsung and TSMC’s 7nm processes. Due to the lack of available information on GLOBALFOUNDRIES 7nm process I didn’t include it, I can now add it to the comparison but first I need to make a few updates to the data previously discussed.
Previously I used a 44nm CPP for Samsung basing it off the IBM, Samsung, GLOBALFOUNDRIES IEDM 2016 paper. I am now hearing their actual CPP is 54nm. Of the 4 processes being compared Samsung is the only process that will use EUV initially and therefore the process has the latest risk production date of the four and likely the highest risk of missing that date (something Samsung appears to recognize with their recent announcement of an optically based 8nm process due to enter risk production in late 2017). The use of EUV should result in a lower mask count that the competing processes and we are currently forecasting Samsung will use EUV for contacts, vias and metal block masks as part of a Self-Aligned Quadruple (SAQP) Patterning scheme for 1x metal layers.
In the same article, I used 54nm for TSMC’s CPP and although that is a claimed value for the process, I am hearing that their actual libraries have a 57nm CPP.
The following table compares the latest data we have for 10nm/7nm:
The data in the table illustrates the need for design-technology co-optimization (DTCO) at the leading edge. Intel and Samsung have the smallest CPP and MMP values but because GLOBALFOUNDRIES and TSMC offer 6T cells, they achieve smaller cell heights and ultimately GLOBALFOUNDRIES has the smallest CPP x Cell Height value. Samsung achieves the smallest SRAM cell size and through the use of EUV we expect Samsung to have the lowest mask count.
GLOBALFOUNDRIES 7LP adds a competitive 7nm process to customer options for leading edge design and production. The process parameters are competitive across the board and provide leading density. The availability of the FX-7 ASIC platforms offers customers an additional engagement path not available at other foundries.