OpenAI’s Jalapeño is a custom accelerator designed specifically for AI inference, particularly the low-latency, multi-chip workloads behind interactive and agentic systems. Its central idea is that useful performance cannot be reduced to peak floating-point operations or memory bandwidth. What matters is how quickly … Read More
Analog Bits Targets the Power Challenge at the Heart of Next-Generation ChipsAnalog Bits is expanding its role in advanced…Read More
Broadcom’s AI Engine Shifts Into OverdriveBroadcom’s fiscal third-quarter 2026 results show how artificial-intelligence…Read More
TSMC’s CoWoS Capacity to Double by 2028—and Rivals Will Still Win OrdersTSMC reportedly plans to double its Chip-on-Wafer-on-Substrate capacity…Read More
The Invisible Bottleneck Is Costing You Time You Can't Get BackBy Joel Jorgensen, FlowAccel. The 2026 Siemens EDA…Read MoreKeysight EDA update at DAC 2026
On the last day of #DAC2026 I stopped by the Keysight booth to chat with Nilesh Kamdar, GM of EDA Business to get an update. He has spent 27 years in the industry, and this made 25 DAC trips for him. For Keysight the application areas of focus are serving designers of high frequency and high-speed digital, RF, and mm/uwave designs. An … Read More
2026 Ceva Edge Symposium: Building Intelligence Beyond the Cloud
The 2026 Ceva Edge Symposium will bring together engineers, technology leaders, ecosystem partners, and innovators to explore a major shift in computing: moving artificial intelligence from distant cloud infrastructure into the devices that interact directly with the physical world. Scheduled for November 2 in Hsinchu,… Read More
HBM’s Second Act: When Memory Starts Thinking
Samsung’s Hot Chips 2026 presentation, “HBM Base Die: How HBM Will Evolve Using Advanced Logic Processes,” argues that the base die beneath a High Bandwidth Memory stack is about to become far more than a communications layer. Traditionally, an HBM base die mainly connects stacked DRAM dies to a GPU, TPU, or other processor and … Read More
NVIDIA Vera: Rebuilding the CPU for Agentic AI
Source: Jonathon Evans and Polychronis Xekalakis, “NVIDIA Vera CPU,” Hot Chips 2026. Performance figures are NVIDIA claims, and several results were based on preproduction or unofficial testing.
NVIDIA’s Vera CPU is a server processor designed specifically for agentic AI, where language models repeatedly observe, reason,… Read More
Fail-Safe Frames: Why Chips&Media’s ASIL-B Video IP Matters
As vehicles evolve into software-defined, increasingly autonomous platforms, video processing is becoming part of the safety-critical computing chain. Camera feeds support functions ranging from surround-view monitoring and driver assistance to object detection and automated driving. If the hardware processing those… Read More
High-NA EUV Moves From Experiment to Manufacturing
Intel Foundry and ASML say high-numerical-aperture extreme-ultraviolet lithography has crossed an important boundary: it is no longer only a development tool, but a production technology. At the SPIE Photomask Technology and Extreme Ultraviolet Lithography conference, the companies reported that Intel has processed … Read More
ASML and TSMC’s 12-Inch Photomask Initiative: Technical Significance
ASML and TSMC’s proposed shift from 6-inch to 12-inch photomasks is an attempt to redesign a critical but often overlooked part of advanced semiconductor manufacturing. Photomasks are precision plates carrying the circuit patterns projected by a lithography scanner onto a silicon wafer. In extreme-ultraviolet lithography,… Read More
AI Memory Gap at DAC 2026
On Tuesday at #DAC2026 I attended the exhibitor presentation, Synopsys: How Silicon Startups are Addressing the AI Memory Gap. Vikram Bhatia from Synopsys introduced the two presentations from Wenbo Yin, SVP of IC Design at TetraMem and R. Scott Hills, VP of Business Development at ANAFLASH. Datacenters consume large amounts… Read More
When Design Gets Faster, the Bottleneck Moves Through the Physical Stack
AI can compress the path to tape-out. The next challenge is compressing physical realization.
Something important is beginning to happen in semiconductor development: the design cycle itself is becoming compressible.
AI-assisted engineering can accelerate architecture exploration, RTL development, verification, physical… Read More



Why ASML Is Racing to Build 110 EUV Machines