Chips&Media CFrame60 is a next-generation frame compression hardware IP designed to address the growing bandwidth and memory challenges in modern SoCs targeting imaging, video, AI, and display applications. Unlike conventional compression architectures that prioritize either bandwidth reduction or image quality,… Read More
If You Struggle with Up-To-Date Documentation llmda.ai Can HelpAccurate, complete, and consistent technical documentation is a…Read More
Siemens EDA Expands AI and Advanced Packaging Collaboration with TSMCAt the recent TSMC Technology Symposium 2026, Siemens…Read MoreQuantum Simulation Using Decision Diagrams. Innovation in Verification
Quantum gate simulation complexity explodes as qubit counts increase. One way to manage this complexity in simulation on classical computers is through use of decision diagrams in place of matrices. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer… Read More
SoC PLANNER: A New Generation of SoC Design Exploration Solution Managing Cost-effectiveness and Sustainability
With over a trillion chips manufactured every year and application requirements evolving faster than ever (across automotive, HPC, and AI), the pressure on SoC design teams has never been higher with design space keeps growing and schedules keep shrinking.
Indeed, for a complex SoC project, the number of possible configurations… Read More
Engineering the Next Era of Semiconductor Innovation
The semiconductor industry is entering a transformative new phase, driven by the convergence of artificial intelligence, cloud computing, and increasingly complex chip architectures. That message took center stage during the keynote talks at the Siemens EDA User2User 2026 North America conference. Executives from Siemens,… Read More
SRAM compilers targeting automotive SoCs on advanced nodes
Processor IP garners the most attention in SoC design, but it’s not the only IP category begging for smart choices. Every processor core needs to be fed with data; however, frequent off-chip DRAM access incurs a large clock-cycle penalty each time. Architects now want SRAM blocks distributed throughout an SoC, putting data close… Read More
CEVA Accelerates Wireless Edge Innovation with Bluetooth HDT and Integrated RF Design Win
CEVA, the leading licensor of wireless connectivity and smart sensing technologies, is advancing its full-stack wireless strategy with the introduction of next-generation Bluetooth High Data Throughput (HDT) capabilities and a major integrated RF subsystem design win. The announcement underscores CEVA’s growing role… Read More
Trusted Convergence Governance: Preserving Admissibility Integrity Across Heterogeneous Semiconductor Systems
As semiconductor systems evolve toward heterogeneous integration, chiplets, 2.5D and 3D packaging, distributed observability, runtime adaptation, Fleet Learning, and lifecycle convergence governance, the industry is entering a fundamentally new operational reality.
Convergence decisions are no longer driven only… Read More
Are You Ready for Spec-Driven Verification?
Quick recap: verification is checking that your implementation of a design matches the in-house design/test specification. In contrast, validation means checking that the implementation matches design intent as defined by a customer specification, use cases, etc. Let’s focus on verification; for simplicity I’ll use “design… Read More
TSMC Powers Up: 408,000 Batteries Get a Safety Intelligence Upgrade
As semiconductor manufacturing becomes increasingly dependent on uninterrupted power and energy efficiency, battery reliability has emerged as a critical operational issue for advanced fabs. Taiwan Semiconductor Manufacturing Company, better known as TSMC, is addressing this challenge through an ambitious global initiative… Read More
Library Characterization gets a Boost from AI
The semiconductor industry creates increasingly complex SoC and chiplets using lots of IP and all of that IP needs to be characterized at the cell level. As we design with 3nm and 2nm nodes, the sheer volume of data required for accurate static timing analysis (STA) is greatly increasing. Modern design flows rely on characterized… Read More




ASML High-NA EUV is Not Ready for High-Volume Production