Extending hardware acceleration to formal verification is a powerful idea to extend hardware acceleration to a verification domain that has not got much attention for acceleration. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford,… Read More
TSMC CoPoS Versus Intel EMIB Semiconductor PackagingTSMC’s CoPoS, generally described as Chip-on-Panel-on-Substrate, and Intel’s…Read More
Agentrys Designs a Real Chip with its Multi-Agent WorkforceThe face of EDA is changing. For forty…Read MorePreviewing FMS 2026: The Next Frontier of Enterprise Memory, CXL, and AI-Era Storage
For anyone tracking enterprise infrastructure, the storage landscape is moving at a breakneck pace. The explosive growth of generative AI, multi-million token context windows, and massive data-centric workloads have pushed traditional memory and storage architectures to their absolute limits.
This August, the industry… Read More
ASIC-to-FPGA Turnkey Prototyping Bundle: A Practical Path to Earlier Hardware Validation
For ASIC design teams, the gap between RTL simulation and first silicon remains one of the most consequential stages of the development cycle. Simulation provides controllability and visibility, but it cannot always reproduce the software workloads, interface behavior, clock interactions, and sustained system activity… Read More
WAVE-J: Redefining High-Performance JPEG for the 8K Era
Chips&Media WAVE-J is a high-performance JPEG codec intellectual property core designed for advanced imaging systems that require very large image support, high throughput, flexible pixel formats, and integrated pre- and post-processing. It succeeds the CODAJ12V architecture while retaining compatibility with … Read More
Interview with Simon Davidmann, AI + EDA Researcher and Former CEO of Imperas
Simon Davidmann is a renowned EDA industry pioneer and serial technology entrepreneur with more than 40 years of experience in simulation and verification. After Synopsys acquired Imperas, which he founded in 2005, he was Synopsys Vice President responsible for Processor Modeling and Simulation. He left Synopsys in 2025 and… Read More
Quadric Extends Series C to $46 Million as Edge AI Demand Accelerates
Quadric has extended its Series C financing to $46 million through a second close led by the International Finance Corporation, the private-sector investment arm of the World Bank Group. The transaction raises Quadric’s total capital secured to approximately $90 million and strengthens its ability to commercialize programmable… Read More
Security by Design: Arteris Expands Its Partnership with Arm
Arteris has expanded its partnership with Arm to deploy Cycuity Radix hardware security assurance technology across additional next-generation Arm central processing unit (CPU) programs. The expansion follows five years of collaboration and successful use of Cycuity Radix on select Arm CPU designs, and it moves hardware… Read More
How early symmetry validation eliminates costly late-stage respins
By Mauli Shah, Product Engineer, Siemens
Analog and mixed-signal design teams face a persistent challenge that directly impacts tape-out schedules and project predictability: symmetry violations discovered at signoff trigger expensive respins, delay schedules and create unpredictable iteration cycles. Despite symmetry… Read More
Rethinking Formal Verification in the AI Era
By Kanav Arora, ML Researcher at ChipAgents
Most hardware teams already understand why formal verification matters. It can expose corner cases that simulation may never reach and establish critical behaviors across the modeled state space.
The unresolved question is not whether formal works. It is why formal remains a specialist… Read More
CEO Interview with Ann Wu and Akash Levy of Silimate
Ann Wu is Co-founder & CEO of Silimate. Before Silimate, Ann designed several generations of custom silicon at Apple, helped manage inference ASIC programs at Meta, and led product strategy and execution at Celestial AI. Ann has a M.S. in Electrical Engineering from Stanford University and a B.S. in Electrical Engineering… Read More



Previewing FMS 2026: The Next Frontier of Enterprise Memory, CXL, and AI-Era Storage