If integrating an embedded FPGA (eFPGA) into your ASIC or SoC design strikes you as odd, it shouldn’t. ICs have been absorbing almost every component on a circuit board for decades, starting with transistors, resistors, and capacitors — then progressing to gates, ALUs, microprocessors, and memories. FPGAs are simply one more… Read More





RISC-V Ready (Tools) Set (Security) Go (Build)
The second Bay Area RISC-V Meetup event was held at the DoubleTree Hilton in Burlingame on June 19 with about 150 attendees. This event was hosted by SiFive and started with a networking session. The topics and speakers for the evening were:
- Commercial Software Tools – Larry Lapides, Imperas
- Securing RISC-V Processors –
Integrity, Reliability Shift Left with ICC
There is a nice serendipity in discovering that two companies I cover are working together. Good for them naturally but makes my job easier because I already have a good idea about the benefits of the partnership. Synopsys and ANSYS announced a collaboration at DAC 2017 for accelerating design optimization for HPS, mobile and automotive.… Read More
7nm Networking Platform Delivers Data Center ASICs
We all know IP is critical for advanced ASIC design. Well-designed and carefully tested IP blocks and subsystems are the lifeblood of any advanced chip project. Those IP suppliers who can measure up to the need, especially at advanced process nodes, will do well, absolutely.
It is interesting to note that eSilicon now has a very … Read More
Leveraging AI to help build AI SOCs
When I first started working in the semiconductor industry back in 1982, I realized that there was a race going on between the complexity of the system being designed and the capabilities of the technology in the tools and systems used to design them. The technology used to design the next generation of hardware was always lagging… Read More
Cadence in the Cloud!
The first clue was cloud vendors (Amazon, Google, IBM, etc…) at 55DAC for the first time ever with lots of cloud content including a Design on Cloud Pavilion. The second clue was the pre-briefing from Cadence last week. There has also been a lot of cloud chatter in the semiconductor ecosystem so yes, I saw this coming and EDA will get… Read More
7nm, 5nm and 3nm Logic, current and projected processes
There has been a lot of new information available about the leading-edge logic processes lately. Papers from IEDM in December 2017, VLSIT this month, the TSMC and Samsung Foundry forums, etc. have all filled in a lot of information. In this article I will summarize what is currently known.… Read More
Semiconductor Cycles Always End the Same Way
It appears the current cycle has rolled over? The reason is memory & could be worsened by trade Figuring out length, depth and impact of the downturn? We had said that AMAT “called” the top of the cycle on their last conference call even though they may not think so. Semiconductor cycles always ends the same way. The… Read More
Mentor at the 55th Design Automation Conference
It’s hard to believe that this is the 55th DAC and even harder to believe that this will be my 35th. So much has changed in 35 years, with DAC back in San Francisco I expect a VERY big crowd and even bigger announcements, absolutely.
Not only is this an epic time for semiconductors, I would say that EDA is exciting again and the Mentor… Read More
Folklore Around the HP 35 LED Development and the Nobel Prize
This is the third in the series of “20 Questions with Wally Rhines”
In the early 1970s I was working on a PhD thesis based upon GaAs light emitting diodes, or LEDs. Many of my predecessors in the Materials Science and Engineering Department at Stanford had worked on other aspects of III-V compounds and some of them went… Read More
Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet